[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / rk3188.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3188";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1608000 1350000
				1416000 1250000
				1200000 1150000
				1008000 1075000
				 816000  975000
				 600000  950000
				 504000  925000
				 312000  875000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x3>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x8000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	i2s0: i2s@1011a000 {
		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3188-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3188-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmu>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@2000a000 {
			compatible = "rockchip,rk3188-gpio-bank0";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg_pull_up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg_pull_down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_pwr: sd0-pwr {
				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};
	};
};

&emac {
	compatible = "rockchip,rk3188-emac";
};

&global_timer {
	interrupts = <GIC_PPI 11 0xf04>;
};

&local_timer {
	interrupts = <GIC_PPI 13 0xf04>;
};

&i2c0 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
};
Commit	Line	Data
6bcf60f8 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <dt-bindings/gpio/gpio.h>
	17	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	18	#include <dt-bindings/clock/rk3188-cru.h>
6bcf60f8	19	#include "rk3xxx.dtsi"
6bcf60f8 HS	20
	21	/ {
	22	compatible = "rockchip,rk3188";
	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
26ab69cb	27	enable-method = "rockchip,rk3066-smp";
6bcf60f8	28
be8a77c5	29	cpu0: cpu@0 {
6bcf60f8 HS	30	device_type = "cpu";
	31	compatible = "arm,cortex-a9";
	32	next-level-cache = <&L2>;
	33	reg = <0x0>;
be8a77c5 HS	34	operating-points = <
	35	/* kHz uV */
	36	1608000 1350000
	37	1416000 1250000
	38	1200000 1150000
	39	1008000 1075000
	40	816000 975000
	41	600000 950000
	42	504000 925000
	43	312000 875000
	44	>;
	45	clock-latency = <40000>;
	46	clocks = <&cru ARMCLK>;
6bcf60f8 HS	47	};
	48	cpu@1 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a9";
	51	next-level-cache = <&L2>;
	52	reg = <0x1>;
	53	};
	54	cpu@2 {
	55	device_type = "cpu";
	56	compatible = "arm,cortex-a9";
	57	next-level-cache = <&L2>;
	58	reg = <0x2>;
	59	};
	60	cpu@3 {
	61	device_type = "cpu";
	62	compatible = "arm,cortex-a9";
	63	next-level-cache = <&L2>;
	64	reg = <0x3>;
	65	};
	66	};
	67
c3030d30 HS	68	sram: sram@10080000 {
	69	compatible = "mmio-sram";
	70	reg = <0x10080000 0x8000>;
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	ranges = <0 0x10080000 0x8000>;
	74
	75	smp-sram@0 {
	76	compatible = "rockchip,rk3066-smp-sram";
	77	reg = <0x0 0x50>;
6bcf60f8	78	};
c3030d30 HS	79	};
c3030d30 HS	80
5fe62b83 JC	81	i2s0: i2s@1011a000 {
	82	compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
	83	reg = <0x1011a000 0x2000>;
	84	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	85	#address-cells = <1>;
	86	#size-cells = <0>;
	87	pinctrl-names = "default";
	88	pinctrl-0 = <&i2s0_bus>;
	89	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	90	dma-names = "tx", "rx";
	91	clock-names = "i2s_hclk", "i2s_clk";
	92	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	93	status = "disabled";
	94	};
	95
c3030d30 HS	96	cru: clock-controller@20000000 {
	97	compatible = "rockchip,rk3188-cru";
	98	reg = <0x20000000 0x1000>;
	99	rockchip,grf = <&grf>;
	100
	101	#clock-cells = <1>;
	102	#reset-cells = <1>;
	103	};
6bcf60f8	104
6e4b3b4b	105	pinctrl: pinctrl {
c3030d30 HS	106	compatible = "rockchip,rk3188-pinctrl";
	107	rockchip,grf = <&grf>;
	108	rockchip,pmu = <&pmu>;
	109
	110	#address-cells = <1>;
	111	#size-cells = <1>;
	112	ranges;
	113
6df127f3	114	gpio0: gpio0@2000a000 {
c3030d30 HS	115	compatible = "rockchip,rk3188-gpio-bank0";
	116	reg = <0x2000a000 0x100>;
	117	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	118	clocks = <&cru PCLK_GPIO0>;
	119
	120	gpio-controller;
	121	#gpio-cells = <2>;
	122
	123	interrupt-controller;
	124	#interrupt-cells = <2>;
6bcf60f8 HS	125	};
6bcf60f8 HS	126
6df127f3	127	gpio1: gpio1@2003c000 {
c3030d30 HS	128	compatible = "rockchip,gpio-bank";
	129	reg = <0x2003c000 0x100>;
	130	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	131	clocks = <&cru PCLK_GPIO1>;
de18e014	132
c3030d30 HS	133	gpio-controller;
	134	#gpio-cells = <2>;
	135
	136	interrupt-controller;
	137	#interrupt-cells = <2>;
de18e014 HS	138	};
de18e014 HS	139
c3030d30 HS	140	gpio2: gpio2@2003e000 {
	141	compatible = "rockchip,gpio-bank";
	142	reg = <0x2003e000 0x100>;
	143	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	144	clocks = <&cru PCLK_GPIO2>;
	145
	146	gpio-controller;
	147	#gpio-cells = <2>;
b13d2a7b	148
c3030d30 HS	149	interrupt-controller;
c3030d30 HS	150	#interrupt-cells = <2>;
b13d2a7b HS	151	};
b13d2a7b HS	152
c3030d30 HS	153	gpio3: gpio3@20080000 {
	154	compatible = "rockchip,gpio-bank";
	155	reg = <0x20080000 0x100>;
	156	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	157	clocks = <&cru PCLK_GPIO3>;
56f2b894	158
c3030d30 HS	159	gpio-controller;
c3030d30 HS	160	#gpio-cells = <2>;
6bcf60f8	161
c3030d30 HS	162	interrupt-controller;
	163	#interrupt-cells = <2>;
	164	};
6bcf60f8	165
c3030d30 HS	166	pcfg_pull_up: pcfg_pull_up {
	167	bias-pull-up;
	168	};
6bcf60f8	169
c3030d30 HS	170	pcfg_pull_down: pcfg_pull_down {
	171	bias-pull-down;
	172	};
6bcf60f8	173
c3030d30 HS	174	pcfg_pull_none: pcfg_pull_none {
	175	bias-disable;
	176	};
6bcf60f8	177
4ff4ae12 HS	178	emmc {
4ff4ae12 HS	179	emmc_clk: emmc-clk {
bee1cef6	180	rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
4ff4ae12 HS	181	};
	182
	183	emmc_cmd: emmc-cmd {
bee1cef6	184	rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
4ff4ae12 HS	185	};
	186
	187	emmc_rst: emmc-rst {
bee1cef6	188	rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
4ff4ae12 HS	189	};
	190
	191	/*
	192	* The data pins are shared between nandc and emmc and
	193	* not accessible through pinctrl. Also they should've
	194	* been already set correctly by firmware, as
	195	* flash/emmc is the boot-device.
	196	*/
	197	};
	198
18ec91e1 RP	199	emac {
	200	emac_xfer: emac-xfer {
	201	rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
	202	<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
	203	<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
	204	<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
	205	<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
	206	<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
	207	<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
	208	<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
	209	};
	210
	211	emac_mdio: emac-mdio {
	212	rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
	213	<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
	214	};
	215	};
	216
9cdffd8c HS	217	i2c0 {
	218	i2c0_xfer: i2c0-xfer {
	219	rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
	220	<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
	221	};
	222	};
	223
	224	i2c1 {
	225	i2c1_xfer: i2c1-xfer {
	226	rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
	227	<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
	228	};
	229	};
	230
	231	i2c2 {
	232	i2c2_xfer: i2c2-xfer {
	233	rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
	234	<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
	235	};
	236	};
	237
	238	i2c3 {
	239	i2c3_xfer: i2c3-xfer {
	240	rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
	241	<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
	242	};
	243	};
	244
	245	i2c4 {
	246	i2c4_xfer: i2c4-xfer {
	247	rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
	248	<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
	249	};
	250	};
	251
550c7f4e BG	252	pwm0 {
	253	pwm0_out: pwm0-out {
	254	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
	255	};
	256	};
	257
	258	pwm1 {
	259	pwm1_out: pwm1-out {
	260	rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
	261	};
	262	};
	263
	264	pwm2 {
	265	pwm2_out: pwm2-out {
	266	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
	267	};
	268	};
	269
	270	pwm3 {
	271	pwm3_out: pwm3-out {
	272	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
	273	};
	274	};
	275
39c2bd78 HS	276	spi0 {
	277	spi0_clk: spi0-clk {
	278	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
	279	};
	280	spi0_cs0: spi0-cs0 {
	281	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
	282	};
	283	spi0_tx: spi0-tx {
	284	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
	285	};
	286	spi0_rx: spi0-rx {
	287	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
	288	};
	289	spi0_cs1: spi0-cs1 {
	290	rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
	291	};
	292	};
	293
	294	spi1 {
	295	spi1_clk: spi1-clk {
	296	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
	297	};
	298	spi1_cs0: spi1-cs0 {
	299	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
	300	};
	301	spi1_rx: spi1-rx {
	302	rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
	303	};
	304	spi1_tx: spi1-tx {
	305	rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
	306	};
	307	spi1_cs1: spi1-cs1 {
	308	rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
	309	};
	310	};
	311
c3030d30 HS	312	uart0 {
	313	uart0_xfer: uart0-xfer {
	314	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
	315	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
	316	};
6bcf60f8	317
c3030d30 HS	318	uart0_cts: uart0-cts {
c3030d30 HS	319	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	320	};
6bcf60f8 HS	321
c3030d30 HS	322	uart0_rts: uart0-rts {
	323	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
	324	};
	325	};
6bcf60f8	326
c3030d30 HS	327	uart1 {
	328	uart1_xfer: uart1-xfer {
	329	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
	330	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
	331	};
6bcf60f8	332
c3030d30 HS	333	uart1_cts: uart1-cts {
c3030d30 HS	334	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	335	};
6bcf60f8 HS	336
c3030d30 HS	337	uart1_rts: uart1-rts {
	338	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
	339	};
	340	};
6bcf60f8	341
c3030d30 HS	342	uart2 {
	343	uart2_xfer: uart2-xfer {
	344	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
	345	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
	346	};
	347	/* no rts / cts for uart2 */
	348	};
6bcf60f8	349
c3030d30 HS	350	uart3 {
	351	uart3_xfer: uart3-xfer {
	352	rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
	353	<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	354	};
6bcf60f8 HS	355
c3030d30 HS	356	uart3_cts: uart3-cts {
c3030d30 HS	357	rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	358	};
6bcf60f8 HS	359
c3030d30 HS	360	uart3_rts: uart3-rts {
c3030d30 HS	361	rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	362	};
c3030d30	363	};
6bcf60f8	364
c3030d30 HS	365	sd0 {
	366	sd0_clk: sd0-clk {
	367	rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	368	};
6bcf60f8 HS	369
c3030d30 HS	370	sd0_cmd: sd0-cmd {
	371	rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
	372	};
6bcf60f8	373
c3030d30 HS	374	sd0_cd: sd0-cd {
	375	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
	376	};
6bcf60f8	377
c3030d30 HS	378	sd0_wp: sd0-wp {
c3030d30 HS	379	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	380	};
6bcf60f8 HS	381
c3030d30 HS	382	sd0_pwr: sd0-pwr {
	383	rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	384	};
6bcf60f8	385
c3030d30 HS	386	sd0_bus1: sd0-bus-width1 {
	387	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
	388	};
6bcf60f8	389
c3030d30 HS	390	sd0_bus4: sd0-bus-width4 {
	391	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	392	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
	393	<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
	394	<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	395	};
c3030d30	396	};
6bcf60f8	397
c3030d30 HS	398	sd1 {
	399	sd1_clk: sd1-clk {
	400	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	401	};
6bcf60f8 HS	402
c3030d30 HS	403	sd1_cmd: sd1-cmd {
	404	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
	405	};
6bcf60f8	406
c3030d30 HS	407	sd1_cd: sd1-cd {
	408	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
	409	};
6bcf60f8	410
c3030d30 HS	411	sd1_wp: sd1-wp {
c3030d30 HS	412	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	413	};
6bcf60f8 HS	414
c3030d30 HS	415	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	416	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	417	};
6bcf60f8 HS	418
c3030d30 HS	419	sd1_bus4: sd1-bus-width4 {
	420	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
	421	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
	422	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
	423	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	424	};
6bcf60f8 HS	425	};
5fe62b83 JC	426
	427	i2s0 {
	428	i2s0_bus: i2s0-bus {
	429	rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
	430	<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
	431	<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
	432	<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
	433	<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
	434	<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
	435	};
	436	};
6bcf60f8 HS	437	};
6bcf60f8 HS	438	};
fcbbf965	439
18ec91e1 RP	440	&emac {
	441	compatible = "rockchip,rk3188-emac";
	442	};
	443
fcbbf965 HS	444	&global_timer {
	445	interrupts = <GIC_PPI 11 0xf04>;
	446	};
	447
	448	&local_timer {
	449	interrupts = <GIC_PPI 13 0xf04>;
	450	};
	451
9cdffd8c HS	452	&i2c0 {
	453	compatible = "rockchip,rk3188-i2c";
	454	pinctrl-names = "default";
	455	pinctrl-0 = <&i2c0_xfer>;
	456	};
	457
	458	&i2c1 {
	459	compatible = "rockchip,rk3188-i2c";
	460	pinctrl-names = "default";
	461	pinctrl-0 = <&i2c1_xfer>;
	462	};
	463
	464	&i2c2 {
	465	compatible = "rockchip,rk3188-i2c";
	466	pinctrl-names = "default";
	467	pinctrl-0 = <&i2c2_xfer>;
	468	};
	469
	470	&i2c3 {
	471	compatible = "rockchip,rk3188-i2c";
	472	pinctrl-names = "default";
	473	pinctrl-0 = <&i2c3_xfer>;
	474	};
	475
	476	&i2c4 {
	477	compatible = "rockchip,rk3188-i2c";
	478	pinctrl-names = "default";
	479	pinctrl-0 = <&i2c4_xfer>;
	480	};
	481
550c7f4e BG	482	&pwm0 {
	483	pinctrl-names = "default";
	484	pinctrl-0 = <&pwm0_out>;
	485	};
	486
	487	&pwm1 {
	488	pinctrl-names = "default";
	489	pinctrl-0 = <&pwm1_out>;
	490	};
	491
	492	&pwm2 {
	493	pinctrl-names = "default";
	494	pinctrl-0 = <&pwm2_out>;
	495	};
	496
	497	&pwm3 {
	498	pinctrl-names = "default";
	499	pinctrl-0 = <&pwm3_out>;
	500	};
	501
39c2bd78 HS	502	&spi0 {
	503	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	504	pinctrl-names = "default";
	505	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	506	};
	507
	508	&spi1 {
	509	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	510	pinctrl-names = "default";
	511	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	512	};
	513
fcbbf965 HS	514	&uart0 {
	515	pinctrl-names = "default";
	516	pinctrl-0 = <&uart0_xfer>;
	517	};
	518
	519	&uart1 {
	520	pinctrl-names = "default";
	521	pinctrl-0 = <&uart1_xfer>;
	522	};
	523
	524	&uart2 {
	525	pinctrl-names = "default";
	526	pinctrl-0 = <&uart2_xfer>;
	527	};
	528
	529	&uart3 {
	530	pinctrl-names = "default";
	531	pinctrl-0 = <&uart3_xfer>;
	532	};
eb2b9d47 HS	533
	534	&wdt {
	535	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
	536	};