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fce152a6 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
6bcf60f8 HS |
2 | /* |
3 | * Copyright (c) 2013 MundoReader S.L. | |
4 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6bcf60f8 HS |
5 | */ |
6 | ||
7 | #include <dt-bindings/gpio/gpio.h> | |
8 | #include <dt-bindings/pinctrl/rockchip.h> | |
b13d2a7b | 9 | #include <dt-bindings/clock/rk3188-cru.h> |
e6e1869f | 10 | #include <dt-bindings/power/rk3188-power.h> |
6bcf60f8 | 11 | #include "rk3xxx.dtsi" |
6bcf60f8 HS |
12 | |
13 | / { | |
14 | compatible = "rockchip,rk3188"; | |
15 | ||
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
26ab69cb | 19 | enable-method = "rockchip,rk3066-smp"; |
6bcf60f8 | 20 | |
be8a77c5 | 21 | cpu0: cpu@0 { |
6bcf60f8 HS |
22 | device_type = "cpu"; |
23 | compatible = "arm,cortex-a9"; | |
24 | next-level-cache = <&L2>; | |
25 | reg = <0x0>; | |
be8a77c5 HS |
26 | clock-latency = <40000>; |
27 | clocks = <&cru ARMCLK>; | |
abcee7a8 | 28 | operating-points-v2 = <&cpu0_opp_table>; |
0222aac4 | 29 | resets = <&cru SRST_CORE0>; |
6bcf60f8 | 30 | }; |
66dc478a | 31 | cpu1: cpu@1 { |
6bcf60f8 HS |
32 | device_type = "cpu"; |
33 | compatible = "arm,cortex-a9"; | |
34 | next-level-cache = <&L2>; | |
35 | reg = <0x1>; | |
abcee7a8 | 36 | operating-points-v2 = <&cpu0_opp_table>; |
0222aac4 | 37 | resets = <&cru SRST_CORE1>; |
6bcf60f8 | 38 | }; |
66dc478a | 39 | cpu2: cpu@2 { |
6bcf60f8 HS |
40 | device_type = "cpu"; |
41 | compatible = "arm,cortex-a9"; | |
42 | next-level-cache = <&L2>; | |
43 | reg = <0x2>; | |
abcee7a8 | 44 | operating-points-v2 = <&cpu0_opp_table>; |
0222aac4 | 45 | resets = <&cru SRST_CORE2>; |
6bcf60f8 | 46 | }; |
66dc478a | 47 | cpu3: cpu@3 { |
6bcf60f8 HS |
48 | device_type = "cpu"; |
49 | compatible = "arm,cortex-a9"; | |
50 | next-level-cache = <&L2>; | |
51 | reg = <0x3>; | |
abcee7a8 | 52 | operating-points-v2 = <&cpu0_opp_table>; |
0222aac4 | 53 | resets = <&cru SRST_CORE3>; |
abcee7a8 HS |
54 | }; |
55 | }; | |
56 | ||
57 | cpu0_opp_table: opp_table0 { | |
58 | compatible = "operating-points-v2"; | |
59 | opp-shared; | |
60 | ||
61 | opp-312000000 { | |
62 | opp-hz = /bits/ 64 <312000000>; | |
63 | opp-microvolt = <875000>; | |
64 | clock-latency-ns = <40000>; | |
65 | }; | |
66 | opp-504000000 { | |
67 | opp-hz = /bits/ 64 <504000000>; | |
68 | opp-microvolt = <925000>; | |
69 | }; | |
70 | opp-600000000 { | |
71 | opp-hz = /bits/ 64 <600000000>; | |
72 | opp-microvolt = <950000>; | |
73 | opp-suspend; | |
74 | }; | |
75 | opp-816000000 { | |
76 | opp-hz = /bits/ 64 <816000000>; | |
77 | opp-microvolt = <975000>; | |
78 | }; | |
79 | opp-1008000000 { | |
80 | opp-hz = /bits/ 64 <1008000000>; | |
81 | opp-microvolt = <1075000>; | |
82 | }; | |
83 | opp-1200000000 { | |
84 | opp-hz = /bits/ 64 <1200000000>; | |
85 | opp-microvolt = <1150000>; | |
86 | }; | |
87 | opp-1416000000 { | |
88 | opp-hz = /bits/ 64 <1416000000>; | |
89 | opp-microvolt = <1250000>; | |
90 | }; | |
91 | opp-1608000000 { | |
92 | opp-hz = /bits/ 64 <1608000000>; | |
93 | opp-microvolt = <1350000>; | |
6bcf60f8 HS |
94 | }; |
95 | }; | |
96 | ||
0fff1428 HS |
97 | display-subsystem { |
98 | compatible = "rockchip,display-subsystem"; | |
99 | ports = <&vop0_out>, <&vop1_out>; | |
100 | }; | |
101 | ||
c3030d30 HS |
102 | sram: sram@10080000 { |
103 | compatible = "mmio-sram"; | |
104 | reg = <0x10080000 0x8000>; | |
105 | #address-cells = <1>; | |
106 | #size-cells = <1>; | |
107 | ranges = <0 0x10080000 0x8000>; | |
108 | ||
109 | smp-sram@0 { | |
110 | compatible = "rockchip,rk3066-smp-sram"; | |
111 | reg = <0x0 0x50>; | |
6bcf60f8 | 112 | }; |
c3030d30 HS |
113 | }; |
114 | ||
0fff1428 HS |
115 | vop0: vop@1010c000 { |
116 | compatible = "rockchip,rk3188-vop"; | |
117 | reg = <0x1010c000 0x1000>; | |
118 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
119 | clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; | |
120 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
e6e1869f | 121 | power-domains = <&power RK3188_PD_VIO>; |
0fff1428 HS |
122 | resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; |
123 | reset-names = "axi", "ahb", "dclk"; | |
124 | status = "disabled"; | |
125 | ||
126 | vop0_out: port { | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | }; | |
130 | }; | |
131 | ||
132 | vop1: vop@1010e000 { | |
133 | compatible = "rockchip,rk3188-vop"; | |
134 | reg = <0x1010e000 0x1000>; | |
135 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
136 | clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; | |
137 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
e6e1869f | 138 | power-domains = <&power RK3188_PD_VIO>; |
0fff1428 HS |
139 | resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; |
140 | reset-names = "axi", "ahb", "dclk"; | |
141 | status = "disabled"; | |
142 | ||
143 | vop1_out: port { | |
144 | #address-cells = <1>; | |
145 | #size-cells = <0>; | |
146 | }; | |
147 | }; | |
148 | ||
627988a6 AK |
149 | timer3: timer@2000e000 { |
150 | compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; | |
151 | reg = <0x2000e000 0x20>; | |
152 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
153 | clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; | |
154 | clock-names = "timer", "pclk"; | |
155 | }; | |
156 | ||
157 | timer6: timer@200380a0 { | |
158 | compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; | |
159 | reg = <0x200380a0 0x20>; | |
160 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
161 | clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; | |
162 | clock-names = "timer", "pclk"; | |
163 | }; | |
164 | ||
5fe62b83 JC |
165 | i2s0: i2s@1011a000 { |
166 | compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; | |
167 | reg = <0x1011a000 0x2000>; | |
168 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
169 | #address-cells = <1>; | |
170 | #size-cells = <0>; | |
171 | pinctrl-names = "default"; | |
172 | pinctrl-0 = <&i2s0_bus>; | |
173 | dmas = <&dmac1_s 6>, <&dmac1_s 7>; | |
174 | dma-names = "tx", "rx"; | |
175 | clock-names = "i2s_hclk", "i2s_clk"; | |
176 | clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; | |
e241657d SZ |
177 | rockchip,playback-channels = <2>; |
178 | rockchip,capture-channels = <2>; | |
812b3dc3 | 179 | #sound-dai-cells = <0>; |
5fe62b83 JC |
180 | status = "disabled"; |
181 | }; | |
182 | ||
39b37ce2 SS |
183 | spdif: sound@1011e000 { |
184 | compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; | |
185 | reg = <0x1011e000 0x2000>; | |
186 | #sound-dai-cells = <0>; | |
187 | clock-names = "hclk", "mclk"; | |
188 | clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; | |
189 | dmas = <&dmac1_s 8>; | |
190 | dma-names = "tx"; | |
191 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
192 | pinctrl-names = "default"; | |
193 | pinctrl-0 = <&spdif_tx>; | |
194 | status = "disabled"; | |
195 | }; | |
196 | ||
c3030d30 HS |
197 | cru: clock-controller@20000000 { |
198 | compatible = "rockchip,rk3188-cru"; | |
199 | reg = <0x20000000 0x1000>; | |
200 | rockchip,grf = <&grf>; | |
201 | ||
202 | #clock-cells = <1>; | |
203 | #reset-cells = <1>; | |
204 | }; | |
6bcf60f8 | 205 | |
4b0d98ae | 206 | efuse: efuse@20010000 { |
85b72602 | 207 | compatible = "rockchip,rk3188-efuse"; |
4b0d98ae CW |
208 | reg = <0x20010000 0x4000>; |
209 | #address-cells = <1>; | |
210 | #size-cells = <1>; | |
211 | clocks = <&cru PCLK_EFUSE>; | |
212 | clock-names = "pclk_efuse"; | |
213 | ||
66914092 | 214 | cpu_leakage: cpu_leakage@17 { |
4b0d98ae CW |
215 | reg = <0x17 0x1>; |
216 | }; | |
217 | }; | |
218 | ||
760bb977 HS |
219 | usbphy: phy { |
220 | compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; | |
221 | rockchip,grf = <&grf>; | |
222 | #address-cells = <1>; | |
223 | #size-cells = <0>; | |
224 | status = "disabled"; | |
225 | ||
a8f0fa27 | 226 | usbphy0: usb-phy@10c { |
760bb977 HS |
227 | #phy-cells = <0>; |
228 | reg = <0x10c>; | |
229 | clocks = <&cru SCLK_OTGPHY0>; | |
230 | clock-names = "phyclk"; | |
0ace8217 | 231 | #clock-cells = <0>; |
760bb977 HS |
232 | }; |
233 | ||
a8f0fa27 | 234 | usbphy1: usb-phy@11c { |
760bb977 HS |
235 | #phy-cells = <0>; |
236 | reg = <0x11c>; | |
237 | clocks = <&cru SCLK_OTGPHY1>; | |
238 | clock-names = "phyclk"; | |
0ace8217 | 239 | #clock-cells = <0>; |
760bb977 HS |
240 | }; |
241 | }; | |
242 | ||
6e4b3b4b | 243 | pinctrl: pinctrl { |
c3030d30 HS |
244 | compatible = "rockchip,rk3188-pinctrl"; |
245 | rockchip,grf = <&grf>; | |
246 | rockchip,pmu = <&pmu>; | |
247 | ||
248 | #address-cells = <1>; | |
249 | #size-cells = <1>; | |
250 | ranges; | |
251 | ||
6df127f3 | 252 | gpio0: gpio0@2000a000 { |
c3030d30 HS |
253 | compatible = "rockchip,rk3188-gpio-bank0"; |
254 | reg = <0x2000a000 0x100>; | |
255 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
256 | clocks = <&cru PCLK_GPIO0>; | |
257 | ||
258 | gpio-controller; | |
259 | #gpio-cells = <2>; | |
260 | ||
261 | interrupt-controller; | |
262 | #interrupt-cells = <2>; | |
6bcf60f8 HS |
263 | }; |
264 | ||
6df127f3 | 265 | gpio1: gpio1@2003c000 { |
c3030d30 HS |
266 | compatible = "rockchip,gpio-bank"; |
267 | reg = <0x2003c000 0x100>; | |
268 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
269 | clocks = <&cru PCLK_GPIO1>; | |
de18e014 | 270 | |
c3030d30 HS |
271 | gpio-controller; |
272 | #gpio-cells = <2>; | |
273 | ||
274 | interrupt-controller; | |
275 | #interrupt-cells = <2>; | |
de18e014 HS |
276 | }; |
277 | ||
c3030d30 HS |
278 | gpio2: gpio2@2003e000 { |
279 | compatible = "rockchip,gpio-bank"; | |
280 | reg = <0x2003e000 0x100>; | |
281 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
282 | clocks = <&cru PCLK_GPIO2>; | |
283 | ||
284 | gpio-controller; | |
285 | #gpio-cells = <2>; | |
b13d2a7b | 286 | |
c3030d30 HS |
287 | interrupt-controller; |
288 | #interrupt-cells = <2>; | |
b13d2a7b HS |
289 | }; |
290 | ||
c3030d30 HS |
291 | gpio3: gpio3@20080000 { |
292 | compatible = "rockchip,gpio-bank"; | |
293 | reg = <0x20080000 0x100>; | |
294 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
295 | clocks = <&cru PCLK_GPIO3>; | |
56f2b894 | 296 | |
c3030d30 HS |
297 | gpio-controller; |
298 | #gpio-cells = <2>; | |
6bcf60f8 | 299 | |
c3030d30 HS |
300 | interrupt-controller; |
301 | #interrupt-cells = <2>; | |
302 | }; | |
6bcf60f8 | 303 | |
c3030d30 HS |
304 | pcfg_pull_up: pcfg_pull_up { |
305 | bias-pull-up; | |
306 | }; | |
6bcf60f8 | 307 | |
c3030d30 HS |
308 | pcfg_pull_down: pcfg_pull_down { |
309 | bias-pull-down; | |
310 | }; | |
6bcf60f8 | 311 | |
c3030d30 HS |
312 | pcfg_pull_none: pcfg_pull_none { |
313 | bias-disable; | |
314 | }; | |
6bcf60f8 | 315 | |
4ff4ae12 HS |
316 | emmc { |
317 | emmc_clk: emmc-clk { | |
bee1cef6 | 318 | rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>; |
4ff4ae12 HS |
319 | }; |
320 | ||
321 | emmc_cmd: emmc-cmd { | |
bee1cef6 | 322 | rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>; |
4ff4ae12 HS |
323 | }; |
324 | ||
325 | emmc_rst: emmc-rst { | |
bee1cef6 | 326 | rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>; |
4ff4ae12 HS |
327 | }; |
328 | ||
329 | /* | |
330 | * The data pins are shared between nandc and emmc and | |
331 | * not accessible through pinctrl. Also they should've | |
332 | * been already set correctly by firmware, as | |
333 | * flash/emmc is the boot-device. | |
334 | */ | |
335 | }; | |
336 | ||
18ec91e1 RP |
337 | emac { |
338 | emac_xfer: emac-xfer { | |
339 | rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ | |
340 | <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ | |
341 | <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ | |
342 | <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */ | |
343 | <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ | |
344 | <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ | |
345 | <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ | |
346 | <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */ | |
347 | }; | |
348 | ||
349 | emac_mdio: emac-mdio { | |
350 | rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>, | |
351 | <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>; | |
352 | }; | |
353 | }; | |
354 | ||
9cdffd8c HS |
355 | i2c0 { |
356 | i2c0_xfer: i2c0-xfer { | |
357 | rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>, | |
358 | <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>; | |
359 | }; | |
360 | }; | |
361 | ||
362 | i2c1 { | |
363 | i2c1_xfer: i2c1-xfer { | |
364 | rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>, | |
365 | <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>; | |
366 | }; | |
367 | }; | |
368 | ||
369 | i2c2 { | |
370 | i2c2_xfer: i2c2-xfer { | |
371 | rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>, | |
372 | <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>; | |
373 | }; | |
374 | }; | |
375 | ||
376 | i2c3 { | |
377 | i2c3_xfer: i2c3-xfer { | |
378 | rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>, | |
379 | <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>; | |
380 | }; | |
381 | }; | |
382 | ||
383 | i2c4 { | |
384 | i2c4_xfer: i2c4-xfer { | |
385 | rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>, | |
386 | <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>; | |
387 | }; | |
388 | }; | |
389 | ||
0fff1428 HS |
390 | lcdc1 { |
391 | lcdc1_dclk: lcdc1-dclk { | |
392 | rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; | |
393 | }; | |
394 | ||
395 | lcdc1_den: lcdc1-den { | |
396 | rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; | |
397 | }; | |
398 | ||
399 | lcdc1_hsync: lcdc1-hsync { | |
400 | rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; | |
401 | }; | |
402 | ||
403 | lcdc1_vsync: lcdc1-vsync { | |
404 | rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; | |
405 | }; | |
406 | ||
407 | lcdc1_rgb24: ldcd1-rgb24 { | |
408 | rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, | |
409 | <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, | |
410 | <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, | |
411 | <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, | |
412 | <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, | |
413 | <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, | |
414 | <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, | |
415 | <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, | |
416 | <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, | |
417 | <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, | |
418 | <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, | |
419 | <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, | |
420 | <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, | |
421 | <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, | |
422 | <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, | |
423 | <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, | |
424 | <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, | |
425 | <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, | |
426 | <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, | |
427 | <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, | |
428 | <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, | |
429 | <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, | |
430 | <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, | |
431 | <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; | |
432 | }; | |
433 | }; | |
434 | ||
550c7f4e BG |
435 | pwm0 { |
436 | pwm0_out: pwm0-out { | |
437 | rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>; | |
438 | }; | |
439 | }; | |
440 | ||
441 | pwm1 { | |
442 | pwm1_out: pwm1-out { | |
443 | rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>; | |
444 | }; | |
445 | }; | |
446 | ||
447 | pwm2 { | |
448 | pwm2_out: pwm2-out { | |
449 | rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>; | |
450 | }; | |
451 | }; | |
452 | ||
453 | pwm3 { | |
454 | pwm3_out: pwm3-out { | |
455 | rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>; | |
456 | }; | |
457 | }; | |
458 | ||
39c2bd78 HS |
459 | spi0 { |
460 | spi0_clk: spi0-clk { | |
461 | rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>; | |
462 | }; | |
463 | spi0_cs0: spi0-cs0 { | |
464 | rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>; | |
465 | }; | |
466 | spi0_tx: spi0-tx { | |
467 | rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>; | |
468 | }; | |
469 | spi0_rx: spi0-rx { | |
470 | rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>; | |
471 | }; | |
472 | spi0_cs1: spi0-cs1 { | |
473 | rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>; | |
474 | }; | |
475 | }; | |
476 | ||
477 | spi1 { | |
478 | spi1_clk: spi1-clk { | |
479 | rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>; | |
480 | }; | |
481 | spi1_cs0: spi1-cs0 { | |
482 | rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>; | |
483 | }; | |
484 | spi1_rx: spi1-rx { | |
485 | rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>; | |
486 | }; | |
487 | spi1_tx: spi1-tx { | |
488 | rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>; | |
489 | }; | |
490 | spi1_cs1: spi1-cs1 { | |
491 | rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>; | |
492 | }; | |
493 | }; | |
494 | ||
c3030d30 HS |
495 | uart0 { |
496 | uart0_xfer: uart0-xfer { | |
497 | rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, | |
498 | <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; | |
499 | }; | |
6bcf60f8 | 500 | |
c3030d30 HS |
501 | uart0_cts: uart0-cts { |
502 | rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
503 | }; |
504 | ||
c3030d30 HS |
505 | uart0_rts: uart0-rts { |
506 | rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; | |
507 | }; | |
508 | }; | |
6bcf60f8 | 509 | |
c3030d30 HS |
510 | uart1 { |
511 | uart1_xfer: uart1-xfer { | |
512 | rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, | |
513 | <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; | |
514 | }; | |
6bcf60f8 | 515 | |
c3030d30 HS |
516 | uart1_cts: uart1-cts { |
517 | rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
518 | }; |
519 | ||
c3030d30 HS |
520 | uart1_rts: uart1-rts { |
521 | rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; | |
522 | }; | |
523 | }; | |
6bcf60f8 | 524 | |
c3030d30 HS |
525 | uart2 { |
526 | uart2_xfer: uart2-xfer { | |
527 | rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, | |
528 | <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; | |
529 | }; | |
530 | /* no rts / cts for uart2 */ | |
531 | }; | |
6bcf60f8 | 532 | |
c3030d30 HS |
533 | uart3 { |
534 | uart3_xfer: uart3-xfer { | |
535 | rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, | |
536 | <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
537 | }; |
538 | ||
c3030d30 HS |
539 | uart3_cts: uart3-cts { |
540 | rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
541 | }; |
542 | ||
c3030d30 HS |
543 | uart3_rts: uart3-rts { |
544 | rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 | 545 | }; |
c3030d30 | 546 | }; |
6bcf60f8 | 547 | |
c3030d30 HS |
548 | sd0 { |
549 | sd0_clk: sd0-clk { | |
550 | rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
551 | }; |
552 | ||
c3030d30 HS |
553 | sd0_cmd: sd0-cmd { |
554 | rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; | |
555 | }; | |
6bcf60f8 | 556 | |
c3030d30 HS |
557 | sd0_cd: sd0-cd { |
558 | rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; | |
559 | }; | |
6bcf60f8 | 560 | |
c3030d30 HS |
561 | sd0_wp: sd0-wp { |
562 | rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
563 | }; |
564 | ||
c3030d30 HS |
565 | sd0_pwr: sd0-pwr { |
566 | rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; | |
567 | }; | |
6bcf60f8 | 568 | |
c3030d30 HS |
569 | sd0_bus1: sd0-bus-width1 { |
570 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; | |
571 | }; | |
6bcf60f8 | 572 | |
c3030d30 HS |
573 | sd0_bus4: sd0-bus-width4 { |
574 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, | |
575 | <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, | |
576 | <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, | |
577 | <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 | 578 | }; |
c3030d30 | 579 | }; |
6bcf60f8 | 580 | |
c3030d30 HS |
581 | sd1 { |
582 | sd1_clk: sd1-clk { | |
583 | rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
584 | }; |
585 | ||
c3030d30 HS |
586 | sd1_cmd: sd1-cmd { |
587 | rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; | |
588 | }; | |
6bcf60f8 | 589 | |
c3030d30 HS |
590 | sd1_cd: sd1-cd { |
591 | rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; | |
592 | }; | |
6bcf60f8 | 593 | |
c3030d30 HS |
594 | sd1_wp: sd1-wp { |
595 | rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
596 | }; |
597 | ||
c3030d30 HS |
598 | sd1_bus1: sd1-bus-width1 { |
599 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
600 | }; |
601 | ||
c3030d30 HS |
602 | sd1_bus4: sd1-bus-width4 { |
603 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, | |
604 | <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, | |
605 | <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, | |
606 | <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
607 | }; |
608 | }; | |
5fe62b83 JC |
609 | |
610 | i2s0 { | |
611 | i2s0_bus: i2s0-bus { | |
612 | rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>, | |
613 | <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>, | |
614 | <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>, | |
615 | <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>, | |
616 | <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>, | |
617 | <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>; | |
618 | }; | |
619 | }; | |
39b37ce2 SS |
620 | |
621 | spdif { | |
622 | spdif_tx: spdif-tx { | |
623 | rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>; | |
624 | }; | |
625 | }; | |
6bcf60f8 HS |
626 | }; |
627 | }; | |
fcbbf965 | 628 | |
18ec91e1 RP |
629 | &emac { |
630 | compatible = "rockchip,rk3188-emac"; | |
631 | }; | |
632 | ||
fcbbf965 | 633 | &global_timer { |
2e1aa605 | 634 | interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
500d0aa9 | 635 | status = "disabled"; |
fcbbf965 HS |
636 | }; |
637 | ||
638 | &local_timer { | |
2e1aa605 | 639 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
fcbbf965 HS |
640 | }; |
641 | ||
4fcac83b HS |
642 | &gpu { |
643 | compatible = "rockchip,rk3188-mali", "arm,mali-400"; | |
644 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
645 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
646 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
647 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
648 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
649 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
650 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
651 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
652 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
653 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
654 | interrupt-names = "gp", | |
655 | "gpmmu", | |
656 | "pp0", | |
0133c492 | 657 | "ppmmu0", |
4fcac83b | 658 | "pp1", |
0133c492 | 659 | "ppmmu1", |
4fcac83b | 660 | "pp2", |
0133c492 | 661 | "ppmmu2", |
4fcac83b | 662 | "pp3", |
0133c492 | 663 | "ppmmu3"; |
e6e1869f | 664 | power-domains = <&power RK3188_PD_GPU>; |
4fcac83b HS |
665 | }; |
666 | ||
9cdffd8c HS |
667 | &i2c0 { |
668 | compatible = "rockchip,rk3188-i2c"; | |
669 | pinctrl-names = "default"; | |
670 | pinctrl-0 = <&i2c0_xfer>; | |
671 | }; | |
672 | ||
673 | &i2c1 { | |
674 | compatible = "rockchip,rk3188-i2c"; | |
675 | pinctrl-names = "default"; | |
676 | pinctrl-0 = <&i2c1_xfer>; | |
677 | }; | |
678 | ||
679 | &i2c2 { | |
680 | compatible = "rockchip,rk3188-i2c"; | |
681 | pinctrl-names = "default"; | |
682 | pinctrl-0 = <&i2c2_xfer>; | |
683 | }; | |
684 | ||
685 | &i2c3 { | |
686 | compatible = "rockchip,rk3188-i2c"; | |
687 | pinctrl-names = "default"; | |
688 | pinctrl-0 = <&i2c3_xfer>; | |
689 | }; | |
690 | ||
691 | &i2c4 { | |
692 | compatible = "rockchip,rk3188-i2c"; | |
693 | pinctrl-names = "default"; | |
694 | pinctrl-0 = <&i2c4_xfer>; | |
695 | }; | |
696 | ||
e6e1869f HS |
697 | &pmu { |
698 | power: power-controller { | |
699 | compatible = "rockchip,rk3188-power-controller"; | |
700 | #power-domain-cells = <1>; | |
701 | #address-cells = <1>; | |
702 | #size-cells = <0>; | |
703 | ||
704 | pd_vio@RK3188_PD_VIO { | |
705 | reg = <RK3188_PD_VIO>; | |
706 | clocks = <&cru ACLK_LCDC0>, | |
707 | <&cru ACLK_LCDC1>, | |
708 | <&cru DCLK_LCDC0>, | |
709 | <&cru DCLK_LCDC1>, | |
710 | <&cru HCLK_LCDC0>, | |
711 | <&cru HCLK_LCDC1>, | |
712 | <&cru SCLK_CIF0>, | |
713 | <&cru ACLK_CIF0>, | |
714 | <&cru HCLK_CIF0>, | |
715 | <&cru ACLK_IPP>, | |
716 | <&cru HCLK_IPP>, | |
717 | <&cru ACLK_RGA>, | |
718 | <&cru HCLK_RGA>; | |
719 | pm_qos = <&qos_lcdc0>, | |
720 | <&qos_lcdc1>, | |
721 | <&qos_cif0>, | |
e6e1869f HS |
722 | <&qos_ipp>, |
723 | <&qos_rga>; | |
724 | }; | |
725 | ||
726 | pd_video@RK3188_PD_VIDEO { | |
727 | reg = <RK3188_PD_VIDEO>; | |
728 | clocks = <&cru ACLK_VDPU>, | |
729 | <&cru ACLK_VEPU>, | |
730 | <&cru HCLK_VDPU>, | |
731 | <&cru HCLK_VEPU>; | |
732 | pm_qos = <&qos_vpu>; | |
733 | }; | |
734 | ||
735 | pd_gpu@RK3188_PD_GPU { | |
736 | reg = <RK3188_PD_GPU>; | |
737 | clocks = <&cru ACLK_GPU>; | |
738 | pm_qos = <&qos_gpu>; | |
739 | }; | |
740 | }; | |
741 | }; | |
742 | ||
550c7f4e BG |
743 | &pwm0 { |
744 | pinctrl-names = "default"; | |
745 | pinctrl-0 = <&pwm0_out>; | |
746 | }; | |
747 | ||
748 | &pwm1 { | |
749 | pinctrl-names = "default"; | |
750 | pinctrl-0 = <&pwm1_out>; | |
751 | }; | |
752 | ||
753 | &pwm2 { | |
754 | pinctrl-names = "default"; | |
755 | pinctrl-0 = <&pwm2_out>; | |
756 | }; | |
757 | ||
758 | &pwm3 { | |
759 | pinctrl-names = "default"; | |
760 | pinctrl-0 = <&pwm3_out>; | |
761 | }; | |
762 | ||
39c2bd78 HS |
763 | &spi0 { |
764 | compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; | |
765 | pinctrl-names = "default"; | |
766 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
767 | }; | |
768 | ||
769 | &spi1 { | |
770 | compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; | |
771 | pinctrl-names = "default"; | |
772 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
773 | }; | |
774 | ||
fcbbf965 | 775 | &uart0 { |
ec7c98ec | 776 | compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; |
fcbbf965 HS |
777 | pinctrl-names = "default"; |
778 | pinctrl-0 = <&uart0_xfer>; | |
779 | }; | |
780 | ||
781 | &uart1 { | |
ec7c98ec | 782 | compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; |
fcbbf965 HS |
783 | pinctrl-names = "default"; |
784 | pinctrl-0 = <&uart1_xfer>; | |
785 | }; | |
786 | ||
787 | &uart2 { | |
ec7c98ec | 788 | compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; |
fcbbf965 HS |
789 | pinctrl-names = "default"; |
790 | pinctrl-0 = <&uart2_xfer>; | |
791 | }; | |
792 | ||
793 | &uart3 { | |
ec7c98ec | 794 | compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; |
fcbbf965 HS |
795 | pinctrl-names = "default"; |
796 | pinctrl-0 = <&uart3_xfer>; | |
797 | }; | |
eb2b9d47 HS |
798 | |
799 | &wdt { | |
800 | compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; | |
801 | }; |