[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / rk3188.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3188";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x3>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x8000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3188-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3188-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmu>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@0x2000a000 {
			compatible = "rockchip,rk3188-gpio-bank0";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@0x2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg_pull_up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg_pull_down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_default>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_pwr: sd0-pwr {
				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
			};
		};
	};
};

&global_timer {
	interrupts = <GIC_PPI 11 0xf04>;
};

&local_timer {
	interrupts = <GIC_PPI 13 0xf04>;
};

&i2c0 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
};
Commit	Line	Data
6bcf60f8 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <dt-bindings/gpio/gpio.h>
	17	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	18	#include <dt-bindings/clock/rk3188-cru.h>
6bcf60f8	19	#include "rk3xxx.dtsi"
6bcf60f8 HS	20
	21	/ {
	22	compatible = "rockchip,rk3188";
	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
26ab69cb	27	enable-method = "rockchip,rk3066-smp";
6bcf60f8 HS	28
	29	cpu@0 {
	30	device_type = "cpu";
	31	compatible = "arm,cortex-a9";
	32	next-level-cache = <&L2>;
	33	reg = <0x0>;
	34	};
	35	cpu@1 {
	36	device_type = "cpu";
	37	compatible = "arm,cortex-a9";
	38	next-level-cache = <&L2>;
	39	reg = <0x1>;
	40	};
	41	cpu@2 {
	42	device_type = "cpu";
	43	compatible = "arm,cortex-a9";
	44	next-level-cache = <&L2>;
	45	reg = <0x2>;
	46	};
	47	cpu@3 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a9";
	50	next-level-cache = <&L2>;
	51	reg = <0x3>;
	52	};
	53	};
	54
c3030d30 HS	55	sram: sram@10080000 {
	56	compatible = "mmio-sram";
	57	reg = <0x10080000 0x8000>;
	58	#address-cells = <1>;
	59	#size-cells = <1>;
	60	ranges = <0 0x10080000 0x8000>;
	61
	62	smp-sram@0 {
	63	compatible = "rockchip,rk3066-smp-sram";
	64	reg = <0x0 0x50>;
6bcf60f8	65	};
c3030d30 HS	66	};
	67
	68	cru: clock-controller@20000000 {
	69	compatible = "rockchip,rk3188-cru";
	70	reg = <0x20000000 0x1000>;
	71	rockchip,grf = <&grf>;
	72
	73	#clock-cells = <1>;
	74	#reset-cells = <1>;
	75	};
6bcf60f8	76
6e4b3b4b	77	pinctrl: pinctrl {
c3030d30 HS	78	compatible = "rockchip,rk3188-pinctrl";
	79	rockchip,grf = <&grf>;
	80	rockchip,pmu = <&pmu>;
	81
	82	#address-cells = <1>;
	83	#size-cells = <1>;
	84	ranges;
	85
	86	gpio0: gpio0@0x2000a000 {
	87	compatible = "rockchip,rk3188-gpio-bank0";
	88	reg = <0x2000a000 0x100>;
	89	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	90	clocks = <&cru PCLK_GPIO0>;
	91
	92	gpio-controller;
	93	#gpio-cells = <2>;
	94
	95	interrupt-controller;
	96	#interrupt-cells = <2>;
6bcf60f8 HS	97	};
6bcf60f8 HS	98
c3030d30 HS	99	gpio1: gpio1@0x2003c000 {
	100	compatible = "rockchip,gpio-bank";
	101	reg = <0x2003c000 0x100>;
	102	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	103	clocks = <&cru PCLK_GPIO1>;
de18e014	104
c3030d30 HS	105	gpio-controller;
	106	#gpio-cells = <2>;
	107
	108	interrupt-controller;
	109	#interrupt-cells = <2>;
de18e014 HS	110	};
de18e014 HS	111
c3030d30 HS	112	gpio2: gpio2@2003e000 {
	113	compatible = "rockchip,gpio-bank";
	114	reg = <0x2003e000 0x100>;
	115	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	116	clocks = <&cru PCLK_GPIO2>;
	117
	118	gpio-controller;
	119	#gpio-cells = <2>;
b13d2a7b	120
c3030d30 HS	121	interrupt-controller;
c3030d30 HS	122	#interrupt-cells = <2>;
b13d2a7b HS	123	};
b13d2a7b HS	124
c3030d30 HS	125	gpio3: gpio3@20080000 {
	126	compatible = "rockchip,gpio-bank";
	127	reg = <0x20080000 0x100>;
	128	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	129	clocks = <&cru PCLK_GPIO3>;
56f2b894	130
c3030d30 HS	131	gpio-controller;
c3030d30 HS	132	#gpio-cells = <2>;
6bcf60f8	133
c3030d30 HS	134	interrupt-controller;
	135	#interrupt-cells = <2>;
	136	};
6bcf60f8	137
c3030d30 HS	138	pcfg_pull_up: pcfg_pull_up {
	139	bias-pull-up;
	140	};
6bcf60f8	141
c3030d30 HS	142	pcfg_pull_down: pcfg_pull_down {
	143	bias-pull-down;
	144	};
6bcf60f8	145
c3030d30 HS	146	pcfg_pull_none: pcfg_pull_none {
	147	bias-disable;
	148	};
6bcf60f8	149
4ff4ae12 HS	150	emmc {
	151	emmc_clk: emmc-clk {
	152	rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_default>;
	153	};
	154
	155	emmc_cmd: emmc-cmd {
	156	rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_default>;
	157	};
	158
	159	emmc_rst: emmc-rst {
	160	rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_default>;
	161	};
	162
	163	/*
	164	* The data pins are shared between nandc and emmc and
	165	* not accessible through pinctrl. Also they should've
	166	* been already set correctly by firmware, as
	167	* flash/emmc is the boot-device.
	168	*/
	169	};
	170
9cdffd8c HS	171	i2c0 {
	172	i2c0_xfer: i2c0-xfer {
	173	rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
	174	<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
	175	};
	176	};
	177
	178	i2c1 {
	179	i2c1_xfer: i2c1-xfer {
	180	rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
	181	<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
	182	};
	183	};
	184
	185	i2c2 {
	186	i2c2_xfer: i2c2-xfer {
	187	rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
	188	<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
	189	};
	190	};
	191
	192	i2c3 {
	193	i2c3_xfer: i2c3-xfer {
	194	rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
	195	<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
	196	};
	197	};
	198
	199	i2c4 {
	200	i2c4_xfer: i2c4-xfer {
	201	rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
	202	<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
	203	};
	204	};
	205
550c7f4e BG	206	pwm0 {
	207	pwm0_out: pwm0-out {
	208	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
	209	};
	210	};
	211
	212	pwm1 {
	213	pwm1_out: pwm1-out {
	214	rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
	215	};
	216	};
	217
	218	pwm2 {
	219	pwm2_out: pwm2-out {
	220	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
	221	};
	222	};
	223
	224	pwm3 {
	225	pwm3_out: pwm3-out {
	226	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
	227	};
	228	};
	229
39c2bd78 HS	230	spi0 {
	231	spi0_clk: spi0-clk {
	232	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
	233	};
	234	spi0_cs0: spi0-cs0 {
	235	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
	236	};
	237	spi0_tx: spi0-tx {
	238	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
	239	};
	240	spi0_rx: spi0-rx {
	241	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
	242	};
	243	spi0_cs1: spi0-cs1 {
	244	rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
	245	};
	246	};
	247
	248	spi1 {
	249	spi1_clk: spi1-clk {
	250	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
	251	};
	252	spi1_cs0: spi1-cs0 {
	253	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
	254	};
	255	spi1_rx: spi1-rx {
	256	rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
	257	};
	258	spi1_tx: spi1-tx {
	259	rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
	260	};
	261	spi1_cs1: spi1-cs1 {
	262	rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
	263	};
	264	};
	265
c3030d30 HS	266	uart0 {
	267	uart0_xfer: uart0-xfer {
	268	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
	269	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
	270	};
6bcf60f8	271
c3030d30 HS	272	uart0_cts: uart0-cts {
c3030d30 HS	273	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	274	};
6bcf60f8 HS	275
c3030d30 HS	276	uart0_rts: uart0-rts {
	277	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
	278	};
	279	};
6bcf60f8	280
c3030d30 HS	281	uart1 {
	282	uart1_xfer: uart1-xfer {
	283	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
	284	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
	285	};
6bcf60f8	286
c3030d30 HS	287	uart1_cts: uart1-cts {
c3030d30 HS	288	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	289	};
6bcf60f8 HS	290
c3030d30 HS	291	uart1_rts: uart1-rts {
	292	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
	293	};
	294	};
6bcf60f8	295
c3030d30 HS	296	uart2 {
	297	uart2_xfer: uart2-xfer {
	298	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
	299	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
	300	};
	301	/* no rts / cts for uart2 */
	302	};
6bcf60f8	303
c3030d30 HS	304	uart3 {
	305	uart3_xfer: uart3-xfer {
	306	rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
	307	<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	308	};
6bcf60f8 HS	309
c3030d30 HS	310	uart3_cts: uart3-cts {
c3030d30 HS	311	rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	312	};
6bcf60f8 HS	313
c3030d30 HS	314	uart3_rts: uart3-rts {
c3030d30 HS	315	rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	316	};
c3030d30	317	};
6bcf60f8	318
c3030d30 HS	319	sd0 {
	320	sd0_clk: sd0-clk {
	321	rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	322	};
6bcf60f8 HS	323
c3030d30 HS	324	sd0_cmd: sd0-cmd {
	325	rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
	326	};
6bcf60f8	327
c3030d30 HS	328	sd0_cd: sd0-cd {
	329	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
	330	};
6bcf60f8	331
c3030d30 HS	332	sd0_wp: sd0-wp {
c3030d30 HS	333	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	334	};
6bcf60f8 HS	335
c3030d30 HS	336	sd0_pwr: sd0-pwr {
	337	rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	338	};
6bcf60f8	339
c3030d30 HS	340	sd0_bus1: sd0-bus-width1 {
	341	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
	342	};
6bcf60f8	343
c3030d30 HS	344	sd0_bus4: sd0-bus-width4 {
	345	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	346	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
	347	<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
	348	<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	349	};
c3030d30	350	};
6bcf60f8	351
c3030d30 HS	352	sd1 {
	353	sd1_clk: sd1-clk {
	354	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	355	};
6bcf60f8 HS	356
c3030d30 HS	357	sd1_cmd: sd1-cmd {
	358	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
	359	};
6bcf60f8	360
c3030d30 HS	361	sd1_cd: sd1-cd {
	362	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
	363	};
6bcf60f8	364
c3030d30 HS	365	sd1_wp: sd1-wp {
c3030d30 HS	366	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	367	};
6bcf60f8 HS	368
c3030d30 HS	369	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	370	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	371	};
6bcf60f8 HS	372
c3030d30 HS	373	sd1_bus4: sd1-bus-width4 {
	374	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
	375	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
	376	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
	377	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	378	};
	379	};
	380	};
	381	};
fcbbf965 HS	382
	383	&global_timer {
	384	interrupts = <GIC_PPI 11 0xf04>;
	385	};
	386
	387	&local_timer {
	388	interrupts = <GIC_PPI 13 0xf04>;
	389	};
	390
9cdffd8c HS	391	&i2c0 {
	392	compatible = "rockchip,rk3188-i2c";
	393	pinctrl-names = "default";
	394	pinctrl-0 = <&i2c0_xfer>;
	395	};
	396
	397	&i2c1 {
	398	compatible = "rockchip,rk3188-i2c";
	399	pinctrl-names = "default";
	400	pinctrl-0 = <&i2c1_xfer>;
	401	};
	402
	403	&i2c2 {
	404	compatible = "rockchip,rk3188-i2c";
	405	pinctrl-names = "default";
	406	pinctrl-0 = <&i2c2_xfer>;
	407	};
	408
	409	&i2c3 {
	410	compatible = "rockchip,rk3188-i2c";
	411	pinctrl-names = "default";
	412	pinctrl-0 = <&i2c3_xfer>;
	413	};
	414
	415	&i2c4 {
	416	compatible = "rockchip,rk3188-i2c";
	417	pinctrl-names = "default";
	418	pinctrl-0 = <&i2c4_xfer>;
	419	};
	420
550c7f4e BG	421	&pwm0 {
	422	pinctrl-names = "default";
	423	pinctrl-0 = <&pwm0_out>;
	424	};
	425
	426	&pwm1 {
	427	pinctrl-names = "default";
	428	pinctrl-0 = <&pwm1_out>;
	429	};
	430
	431	&pwm2 {
	432	pinctrl-names = "default";
	433	pinctrl-0 = <&pwm2_out>;
	434	};
	435
	436	&pwm3 {
	437	pinctrl-names = "default";
	438	pinctrl-0 = <&pwm3_out>;
	439	};
	440
39c2bd78 HS	441	&spi0 {
	442	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	443	pinctrl-names = "default";
	444	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	445	};
	446
	447	&spi1 {
	448	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	449	pinctrl-names = "default";
	450	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	451	};
	452
fcbbf965 HS	453	&uart0 {
	454	pinctrl-names = "default";
	455	pinctrl-0 = <&uart0_xfer>;
	456	};
	457
	458	&uart1 {
	459	pinctrl-names = "default";
	460	pinctrl-0 = <&uart1_xfer>;
	461	};
	462
	463	&uart2 {
	464	pinctrl-names = "default";
	465	pinctrl-0 = <&uart2_xfer>;
	466	};
	467
	468	&uart3 {
	469	pinctrl-names = "default";
	470	pinctrl-0 = <&uart3_xfer>;
	471	};
eb2b9d47 HS	472
	473	&wdt {
	474	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
	475	};