projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 9848ebeb JC |
1 | /* |
| 2 | * This file is dual-licensed: you can use it either under the terms | |
| 3 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 4 | * licensing only applies to this file, and not this project as a | |
| 5 | * whole. | |
| 6 | * | |
| 7 | * a) This file is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of the | |
| 10 | * License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This file is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * Or, alternatively, | |
| 18 | * | |
| 19 | * b) Permission is hereby granted, free of charge, to any person | |
| 20 | * obtaining a copy of this software and associated documentation | |
| 21 | * files (the "Software"), to deal in the Software without | |
| 22 | * restriction, including without limitation the rights to use, | |
| 23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 24 | * sell copies of the Software, and to permit persons to whom the | |
| 25 | * Software is furnished to do so, subject to the following | |
| 26 | * conditions: | |
| 27 | * | |
| 28 | * The above copyright notice and this permission notice shall be | |
| 29 | * included in all copies or substantial portions of the Software. | |
| 30 | * | |
| 31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 38 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 39 | */ | |
| 40 | ||
| 41 | #include <dt-bindings/gpio/gpio.h> | |
| 42 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 44 | #include <dt-bindings/pinctrl/rockchip.h> | |
| 45 | #include <dt-bindings/clock/rk3228-cru.h> | |
| 7796031e | 46 | #include <dt-bindings/thermal/thermal.h> |
| 9848ebeb JC |
47 | |
| 48 | / { | |
| 0193273d JMC |
49 | #address-cells = <1>; |
| 50 | #size-cells = <1>; | |
| 51 | ||
| 9848ebeb JC |
52 | interrupt-parent = <&gic>; |
| 53 | ||
| 54 | aliases { | |
| 55 | serial0 = &uart0; | |
| 56 | serial1 = &uart1; | |
| 57 | serial2 = &uart2; | |
| 58 | }; | |
| 59 | ||
| 60 | cpus { | |
| 61 | #address-cells = <1>; | |
| 62 | #size-cells = <0>; | |
| 63 | ||
| 64 | cpu0: cpu@f00 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "arm,cortex-a7"; | |
| 67 | reg = <0xf00>; | |
| 68 | resets = <&cru SRST_CORE0>; | |
| 9f12da43 | 69 | operating-points-v2 = <&cpu0_opp_table>; |
| 7796031e | 70 | #cooling-cells = <2>; /* min followed by max */ |
| 9848ebeb JC |
71 | clock-latency = <40000>; |
| 72 | clocks = <&cru ARMCLK>; | |
| 0ae92144 | 73 | enable-method = "psci"; |
| 9848ebeb JC |
74 | }; |
| 75 | ||
| 76 | cpu1: cpu@f01 { | |
| 77 | device_type = "cpu"; | |
| 78 | compatible = "arm,cortex-a7"; | |
| 79 | reg = <0xf01>; | |
| 80 | resets = <&cru SRST_CORE1>; | |
| 9f12da43 | 81 | operating-points-v2 = <&cpu0_opp_table>; |
| 0ae92144 | 82 | enable-method = "psci"; |
| 9848ebeb JC |
83 | }; |
| 84 | ||
| 85 | cpu2: cpu@f02 { | |
| 86 | device_type = "cpu"; | |
| 87 | compatible = "arm,cortex-a7"; | |
| 88 | reg = <0xf02>; | |
| 89 | resets = <&cru SRST_CORE2>; | |
| 9f12da43 | 90 | operating-points-v2 = <&cpu0_opp_table>; |
| 0ae92144 | 91 | enable-method = "psci"; |
| 9848ebeb JC |
92 | }; |
| 93 | ||
| 94 | cpu3: cpu@f03 { | |
| 95 | device_type = "cpu"; | |
| 96 | compatible = "arm,cortex-a7"; | |
| 97 | reg = <0xf03>; | |
| 98 | resets = <&cru SRST_CORE3>; | |
| 9f12da43 | 99 | operating-points-v2 = <&cpu0_opp_table>; |
| 0ae92144 | 100 | enable-method = "psci"; |
| 9f12da43 FX |
101 | }; |
| 102 | }; | |
| 103 | ||
| 104 | cpu0_opp_table: opp_table0 { | |
| 105 | compatible = "operating-points-v2"; | |
| 106 | opp-shared; | |
| 107 | ||
| 108 | opp-408000000 { | |
| 109 | opp-hz = /bits/ 64 <408000000>; | |
| 110 | opp-microvolt = <950000>; | |
| 111 | clock-latency-ns = <40000>; | |
| 112 | opp-suspend; | |
| 113 | }; | |
| 114 | opp-600000000 { | |
| 115 | opp-hz = /bits/ 64 <600000000>; | |
| 116 | opp-microvolt = <975000>; | |
| 117 | }; | |
| 118 | opp-816000000 { | |
| 119 | opp-hz = /bits/ 64 <816000000>; | |
| 120 | opp-microvolt = <1000000>; | |
| 121 | }; | |
| 122 | opp-1008000000 { | |
| 123 | opp-hz = /bits/ 64 <1008000000>; | |
| 124 | opp-microvolt = <1175000>; | |
| 125 | }; | |
| 126 | opp-1200000000 { | |
| 127 | opp-hz = /bits/ 64 <1200000000>; | |
| 128 | opp-microvolt = <1275000>; | |
| 9848ebeb JC |
129 | }; |
| 130 | }; | |
| 131 | ||
| 132 | amba { | |
| 2ef7d5f3 | 133 | compatible = "simple-bus"; |
| 9848ebeb JC |
134 | #address-cells = <1>; |
| 135 | #size-cells = <1>; | |
| 136 | ranges; | |
| 137 | ||
| 138 | pdma: pdma@110f0000 { | |
| 139 | compatible = "arm,pl330", "arm,primecell"; | |
| 140 | reg = <0x110f0000 0x4000>; | |
| 141 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
| 142 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
| 143 | #dma-cells = <1>; | |
| 144 | clocks = <&cru ACLK_DMAC>; | |
| 145 | clock-names = "apb_pclk"; | |
| 146 | }; | |
| 147 | }; | |
| 148 | ||
| 149 | arm-pmu { | |
| 150 | compatible = "arm,cortex-a7-pmu"; | |
| 151 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
| 152 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, | |
| 153 | <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, | |
| 154 | <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 155 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; | |
| 156 | }; | |
| 157 | ||
| 0ae92144 FW |
158 | psci { |
| 159 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
| 160 | method = "smc"; | |
| 161 | }; | |
| 162 | ||
| 9848ebeb JC |
163 | timer { |
| 164 | compatible = "arm,armv7-timer"; | |
| 165 | arm,cpu-registers-not-fw-configured; | |
| 166 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 167 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 168 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 169 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 170 | clock-frequency = <24000000>; | |
| 171 | }; | |
| 172 | ||
| 173 | xin24m: oscillator { | |
| 174 | compatible = "fixed-clock"; | |
| 175 | clock-frequency = <24000000>; | |
| 176 | clock-output-names = "xin24m"; | |
| 177 | #clock-cells = <0>; | |
| 178 | }; | |
| 179 | ||
| ccada248 XZ |
180 | i2s1: i2s1@100b0000 { |
| 181 | compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; | |
| 182 | reg = <0x100b0000 0x4000>; | |
| 183 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| 184 | #address-cells = <1>; | |
| 185 | #size-cells = <0>; | |
| 186 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 187 | clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; | |
| 188 | dmas = <&pdma 14>, <&pdma 15>; | |
| 189 | dma-names = "tx", "rx"; | |
| 190 | pinctrl-names = "default"; | |
| 191 | pinctrl-0 = <&i2s1_bus>; | |
| 192 | status = "disabled"; | |
| 193 | }; | |
| 194 | ||
| 195 | i2s0: i2s0@100c0000 { | |
| 196 | compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; | |
| 197 | reg = <0x100c0000 0x4000>; | |
| 198 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 199 | #address-cells = <1>; | |
| 200 | #size-cells = <0>; | |
| 201 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 202 | clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; | |
| 203 | dmas = <&pdma 11>, <&pdma 12>; | |
| 204 | dma-names = "tx", "rx"; | |
| 205 | status = "disabled"; | |
| 206 | }; | |
| 207 | ||
| 4b456d20 SZ |
208 | spdif: spdif@100d0000 { |
| 209 | compatible = "rockchip,rk3228-spdif"; | |
| 210 | reg = <0x100d0000 0x1000>; | |
| 211 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 212 | clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; | |
| 213 | clock-names = "mclk", "hclk"; | |
| 214 | dmas = <&pdma 10>; | |
| 215 | dma-names = "tx"; | |
| 216 | pinctrl-names = "default"; | |
| 217 | pinctrl-0 = <&spdif_tx>; | |
| 218 | status = "disabled"; | |
| 219 | }; | |
| 220 | ||
| ccada248 XZ |
221 | i2s2: i2s2@100e0000 { |
| 222 | compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; | |
| 223 | reg = <0x100e0000 0x4000>; | |
| 224 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 225 | #address-cells = <1>; | |
| 226 | #size-cells = <0>; | |
| 227 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 228 | clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; | |
| 229 | dmas = <&pdma 0>, <&pdma 1>; | |
| 230 | dma-names = "tx", "rx"; | |
| 231 | status = "disabled"; | |
| 232 | }; | |
| 233 | ||
| 9848ebeb | 234 | grf: syscon@11000000 { |
| 3880af45 | 235 | compatible = "syscon", "simple-mfd"; |
| 9848ebeb | 236 | reg = <0x11000000 0x1000>; |
| 3880af45 WW |
237 | #address-cells = <1>; |
| 238 | #size-cells = <1>; | |
| 239 | ||
| 83086adf DW |
240 | io_domains: io-domains { |
| 241 | compatible = "rockchip,rk3228-io-voltage-domain"; | |
| 242 | status = "disabled"; | |
| 243 | }; | |
| 244 | ||
| 3880af45 WW |
245 | u2phy0: usb2-phy@760 { |
| 246 | compatible = "rockchip,rk3228-usb2phy"; | |
| 247 | reg = <0x0760 0x0c>; | |
| 248 | clocks = <&cru SCLK_OTGPHY0>; | |
| 249 | clock-names = "phyclk"; | |
| 250 | clock-output-names = "usb480m_phy0"; | |
| 251 | #clock-cells = <0>; | |
| 252 | status = "disabled"; | |
| 253 | ||
| 254 | u2phy0_otg: otg-port { | |
| 255 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 256 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 257 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
| 258 | interrupt-names = "otg-bvalid", "otg-id", | |
| 259 | "linestate"; | |
| 260 | #phy-cells = <0>; | |
| 261 | status = "disabled"; | |
| 262 | }; | |
| 263 | ||
| 264 | u2phy0_host: host-port { | |
| 265 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 266 | interrupt-names = "linestate"; | |
| 267 | #phy-cells = <0>; | |
| 268 | status = "disabled"; | |
| 269 | }; | |
| 270 | }; | |
| 271 | ||
| 272 | u2phy1: usb2-phy@800 { | |
| 273 | compatible = "rockchip,rk3228-usb2phy"; | |
| 274 | reg = <0x0800 0x0c>; | |
| 275 | clocks = <&cru SCLK_OTGPHY1>; | |
| 276 | clock-names = "phyclk"; | |
| 277 | clock-output-names = "usb480m_phy1"; | |
| 278 | #clock-cells = <0>; | |
| 279 | status = "disabled"; | |
| 280 | ||
| 281 | u2phy1_otg: otg-port { | |
| 282 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 283 | interrupt-names = "linestate"; | |
| 284 | #phy-cells = <0>; | |
| 285 | status = "disabled"; | |
| 286 | }; | |
| 287 | ||
| 288 | u2phy1_host: host-port { | |
| 289 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 290 | interrupt-names = "linestate"; | |
| 291 | #phy-cells = <0>; | |
| 292 | status = "disabled"; | |
| 293 | }; | |
| 294 | }; | |
| 9848ebeb JC |
295 | }; |
| 296 | ||
| 297 | uart0: serial@11010000 { | |
| 298 | compatible = "snps,dw-apb-uart"; | |
| 299 | reg = <0x11010000 0x100>; | |
| 300 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
| 301 | clock-frequency = <24000000>; | |
| 302 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
| 303 | clock-names = "baudclk", "apb_pclk"; | |
| 304 | pinctrl-names = "default"; | |
| 305 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
| 306 | reg-shift = <2>; | |
| 307 | reg-io-width = <4>; | |
| 308 | status = "disabled"; | |
| 309 | }; | |
| 310 | ||
| 311 | uart1: serial@11020000 { | |
| 312 | compatible = "snps,dw-apb-uart"; | |
| 313 | reg = <0x11020000 0x100>; | |
| 314 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 315 | clock-frequency = <24000000>; | |
| 316 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
| 317 | clock-names = "baudclk", "apb_pclk"; | |
| 318 | pinctrl-names = "default"; | |
| 319 | pinctrl-0 = <&uart1_xfer>; | |
| 320 | reg-shift = <2>; | |
| 321 | reg-io-width = <4>; | |
| 322 | status = "disabled"; | |
| 323 | }; | |
| 324 | ||
| 325 | uart2: serial@11030000 { | |
| 326 | compatible = "snps,dw-apb-uart"; | |
| 327 | reg = <0x11030000 0x100>; | |
| 328 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 329 | clock-frequency = <24000000>; | |
| 330 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
| 331 | clock-names = "baudclk", "apb_pclk"; | |
| 332 | pinctrl-names = "default"; | |
| 333 | pinctrl-0 = <&uart2_xfer>; | |
| 334 | reg-shift = <2>; | |
| 335 | reg-io-width = <4>; | |
| 336 | status = "disabled"; | |
| 337 | }; | |
| 338 | ||
| d549df4b YY |
339 | i2c0: i2c@11050000 { |
| 340 | compatible = "rockchip,rk3228-i2c"; | |
| 341 | reg = <0x11050000 0x1000>; | |
| 342 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 343 | #address-cells = <1>; | |
| 344 | #size-cells = <0>; | |
| 345 | clock-names = "i2c"; | |
| 346 | clocks = <&cru PCLK_I2C0>; | |
| 347 | pinctrl-names = "default"; | |
| 348 | pinctrl-0 = <&i2c0_xfer>; | |
| 349 | status = "disabled"; | |
| 350 | }; | |
| 351 | ||
| 352 | i2c1: i2c@11060000 { | |
| 353 | compatible = "rockchip,rk3228-i2c"; | |
| 354 | reg = <0x11060000 0x1000>; | |
| 355 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 356 | #address-cells = <1>; | |
| 357 | #size-cells = <0>; | |
| 358 | clock-names = "i2c"; | |
| 359 | clocks = <&cru PCLK_I2C1>; | |
| 360 | pinctrl-names = "default"; | |
| 361 | pinctrl-0 = <&i2c1_xfer>; | |
| 362 | status = "disabled"; | |
| 363 | }; | |
| 364 | ||
| 365 | i2c2: i2c@11070000 { | |
| 366 | compatible = "rockchip,rk3228-i2c"; | |
| 367 | reg = <0x11070000 0x1000>; | |
| 368 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 369 | #address-cells = <1>; | |
| 370 | #size-cells = <0>; | |
| 371 | clock-names = "i2c"; | |
| 372 | clocks = <&cru PCLK_I2C2>; | |
| 373 | pinctrl-names = "default"; | |
| 374 | pinctrl-0 = <&i2c2_xfer>; | |
| 375 | status = "disabled"; | |
| 376 | }; | |
| 377 | ||
| 378 | i2c3: i2c@11080000 { | |
| 379 | compatible = "rockchip,rk3228-i2c"; | |
| 380 | reg = <0x11080000 0x1000>; | |
| 381 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 382 | #address-cells = <1>; | |
| 383 | #size-cells = <0>; | |
| 384 | clock-names = "i2c"; | |
| 385 | clocks = <&cru PCLK_I2C3>; | |
| 386 | pinctrl-names = "default"; | |
| 387 | pinctrl-0 = <&i2c3_xfer>; | |
| 388 | status = "disabled"; | |
| 389 | }; | |
| 390 | ||
| fa206984 FW |
391 | wdt: watchdog@110a0000 { |
| 392 | compatible = "snps,dw-wdt"; | |
| 393 | reg = <0x110a0000 0x100>; | |
| 394 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 395 | clocks = <&cru PCLK_CPU>; | |
| 396 | status = "disabled"; | |
| 397 | }; | |
| 398 | ||
| 9848ebeb JC |
399 | pwm0: pwm@110b0000 { |
| 400 | compatible = "rockchip,rk3288-pwm"; | |
| 401 | reg = <0x110b0000 0x10>; | |
| 402 | #pwm-cells = <3>; | |
| 403 | clocks = <&cru PCLK_PWM>; | |
| 404 | clock-names = "pwm"; | |
| 405 | pinctrl-names = "default"; | |
| 406 | pinctrl-0 = <&pwm0_pin>; | |
| 407 | status = "disabled"; | |
| 408 | }; | |
| 409 | ||
| 410 | pwm1: pwm@110b0010 { | |
| 411 | compatible = "rockchip,rk3288-pwm"; | |
| 412 | reg = <0x110b0010 0x10>; | |
| 413 | #pwm-cells = <3>; | |
| 414 | clocks = <&cru PCLK_PWM>; | |
| 415 | clock-names = "pwm"; | |
| 416 | pinctrl-names = "default"; | |
| 417 | pinctrl-0 = <&pwm1_pin>; | |
| 418 | status = "disabled"; | |
| 419 | }; | |
| 420 | ||
| 421 | pwm2: pwm@110b0020 { | |
| 422 | compatible = "rockchip,rk3288-pwm"; | |
| 423 | reg = <0x110b0020 0x10>; | |
| 424 | #pwm-cells = <3>; | |
| 425 | clocks = <&cru PCLK_PWM>; | |
| 426 | clock-names = "pwm"; | |
| 427 | pinctrl-names = "default"; | |
| 428 | pinctrl-0 = <&pwm2_pin>; | |
| 429 | status = "disabled"; | |
| 430 | }; | |
| 431 | ||
| 432 | pwm3: pwm@110b0030 { | |
| 433 | compatible = "rockchip,rk3288-pwm"; | |
| 434 | reg = <0x110b0030 0x10>; | |
| 435 | #pwm-cells = <2>; | |
| 436 | clocks = <&cru PCLK_PWM>; | |
| 437 | clock-names = "pwm"; | |
| 438 | pinctrl-names = "default"; | |
| 439 | pinctrl-0 = <&pwm3_pin>; | |
| 440 | status = "disabled"; | |
| 441 | }; | |
| 442 | ||
| 443 | timer: timer@110c0000 { | |
| b72af346 | 444 | compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; |
| 9848ebeb JC |
445 | reg = <0x110c0000 0x20>; |
| 446 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| 447 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
| 448 | clock-names = "timer", "pclk"; | |
| 449 | }; | |
| 450 | ||
| 451 | cru: clock-controller@110e0000 { | |
| 452 | compatible = "rockchip,rk3228-cru"; | |
| 453 | reg = <0x110e0000 0x1000>; | |
| 454 | rockchip,grf = <&grf>; | |
| 455 | #clock-cells = <1>; | |
| 456 | #reset-cells = <1>; | |
| 30ee5814 EZ |
457 | assigned-clocks = |
| 458 | <&cru PLL_GPLL>, <&cru ARMCLK>, | |
| 459 | <&cru PLL_CPLL>, <&cru ACLK_PERI>, | |
| 460 | <&cru HCLK_PERI>, <&cru PCLK_PERI>, | |
| 461 | <&cru ACLK_CPU>, <&cru HCLK_CPU>, | |
| 462 | <&cru PCLK_CPU>; | |
| 463 | assigned-clock-rates = | |
| 464 | <594000000>, <816000000>, | |
| 465 | <500000000>, <150000000>, | |
| 466 | <150000000>, <75000000>, | |
| 467 | <150000000>, <150000000>, | |
| 468 | <75000000>; | |
| 9848ebeb JC |
469 | }; |
| 470 | ||
| 7796031e CW |
471 | thermal-zones { |
| 472 | cpu_thermal: cpu-thermal { | |
| 473 | polling-delay-passive = <100>; /* milliseconds */ | |
| 474 | polling-delay = <5000>; /* milliseconds */ | |
| 475 | ||
| 476 | thermal-sensors = <&tsadc 0>; | |
| 477 | ||
| 478 | trips { | |
| 479 | cpu_alert0: cpu_alert0 { | |
| 480 | temperature = <70000>; /* millicelsius */ | |
| 481 | hysteresis = <2000>; /* millicelsius */ | |
| 482 | type = "passive"; | |
| 483 | }; | |
| 484 | cpu_alert1: cpu_alert1 { | |
| 485 | temperature = <75000>; /* millicelsius */ | |
| 486 | hysteresis = <2000>; /* millicelsius */ | |
| 487 | type = "passive"; | |
| 488 | }; | |
| 489 | cpu_crit: cpu_crit { | |
| 490 | temperature = <90000>; /* millicelsius */ | |
| 491 | hysteresis = <2000>; /* millicelsius */ | |
| 492 | type = "critical"; | |
| 493 | }; | |
| 494 | }; | |
| 495 | ||
| 496 | cooling-maps { | |
| 497 | map0 { | |
| 498 | trip = <&cpu_alert0>; | |
| 499 | cooling-device = | |
| 500 | <&cpu0 THERMAL_NO_LIMIT 6>; | |
| 501 | }; | |
| 502 | map1 { | |
| 503 | trip = <&cpu_alert1>; | |
| 504 | cooling-device = | |
| 505 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 506 | }; | |
| 507 | }; | |
| 508 | }; | |
| 509 | }; | |
| 510 | ||
| 511 | tsadc: tsadc@11150000 { | |
| 512 | compatible = "rockchip,rk3228-tsadc"; | |
| 513 | reg = <0x11150000 0x100>; | |
| 514 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
| 515 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
| 516 | clock-names = "tsadc", "apb_pclk"; | |
| 2b3f2f37 RH |
517 | assigned-clocks = <&cru SCLK_TSADC>; |
| 518 | assigned-clock-rates = <32768>; | |
| 7796031e CW |
519 | resets = <&cru SRST_TSADC>; |
| 520 | reset-names = "tsadc-apb"; | |
| 521 | pinctrl-names = "init", "default", "sleep"; | |
| 522 | pinctrl-0 = <&otp_gpio>; | |
| 523 | pinctrl-1 = <&otp_out>; | |
| 524 | pinctrl-2 = <&otp_gpio>; | |
| 525 | #thermal-sensor-cells = <0>; | |
| 526 | rockchip,hw-tshut-temp = <95000>; | |
| 527 | status = "disabled"; | |
| 528 | }; | |
| 529 | ||
| 9848ebeb | 530 | emmc: dwmmc@30020000 { |
| 0d6a01f8 | 531 | compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| 9848ebeb JC |
532 | reg = <0x30020000 0x4000>; |
| 533 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 534 | clock-frequency = <37500000>; | |
| 6a8883d6 | 535 | max-frequency = <37500000>; |
| 9848ebeb JC |
536 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
| 537 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
| 538 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
| 539 | bus-width = <8>; | |
| 540 | default-sample-phase = <158>; | |
| 9848ebeb JC |
541 | fifo-depth = <0x100>; |
| 542 | pinctrl-names = "default"; | |
| 543 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
| 2d1f1d4c HS |
544 | resets = <&cru SRST_EMMC>; |
| 545 | reset-names = "reset"; | |
| 9848ebeb JC |
546 | status = "disabled"; |
| 547 | }; | |
| 548 | ||
| 3880af45 WW |
549 | usb_otg: usb@30040000 { |
| 550 | compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", | |
| 551 | "snps,dwc2"; | |
| 552 | reg = <0x30040000 0x40000>; | |
| 553 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 554 | clocks = <&cru HCLK_OTG>; | |
| 555 | clock-names = "otg"; | |
| 556 | dr_mode = "otg"; | |
| 557 | g-np-tx-fifo-size = <16>; | |
| 558 | g-rx-fifo-size = <280>; | |
| 559 | g-tx-fifo-size = <256 128 128 64 32 16>; | |
| 560 | g-use-dma; | |
| 561 | phys = <&u2phy0_otg>; | |
| 562 | phy-names = "usb2-phy"; | |
| 563 | status = "disabled"; | |
| 564 | }; | |
| 565 | ||
| 566 | usb_host0_ehci: usb@30080000 { | |
| 567 | compatible = "generic-ehci"; | |
| 568 | reg = <0x30080000 0x20000>; | |
| 569 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 570 | clocks = <&cru HCLK_HOST0>, <&u2phy0>; | |
| 571 | clock-names = "usbhost", "utmi"; | |
| 572 | phys = <&u2phy0_host>; | |
| 573 | phy-names = "usb"; | |
| 574 | status = "disabled"; | |
| 575 | }; | |
| 576 | ||
| 577 | usb_host0_ohci: usb@300a0000 { | |
| 578 | compatible = "generic-ohci"; | |
| 579 | reg = <0x300a0000 0x20000>; | |
| 580 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 581 | clocks = <&cru HCLK_HOST0>, <&u2phy0>; | |
| 582 | clock-names = "usbhost", "utmi"; | |
| 583 | phys = <&u2phy0_host>; | |
| 584 | phy-names = "usb"; | |
| 585 | status = "disabled"; | |
| 586 | }; | |
| 587 | ||
| 588 | usb_host1_ehci: usb@300c0000 { | |
| 589 | compatible = "generic-ehci"; | |
| 590 | reg = <0x300c0000 0x20000>; | |
| 591 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 592 | clocks = <&cru HCLK_HOST1>, <&u2phy1>; | |
| 593 | clock-names = "usbhost", "utmi"; | |
| 594 | phys = <&u2phy1_otg>; | |
| 595 | phy-names = "usb"; | |
| 596 | status = "disabled"; | |
| 597 | }; | |
| 598 | ||
| 599 | usb_host1_ohci: usb@300e0000 { | |
| 600 | compatible = "generic-ohci"; | |
| 601 | reg = <0x300e0000 0x20000>; | |
| 602 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 603 | clocks = <&cru HCLK_HOST1>, <&u2phy1>; | |
| 604 | clock-names = "usbhost", "utmi"; | |
| 605 | phys = <&u2phy1_otg>; | |
| 606 | phy-names = "usb"; | |
| 607 | status = "disabled"; | |
| 608 | }; | |
| 609 | ||
| 610 | usb_host2_ehci: usb@30100000 { | |
| 611 | compatible = "generic-ehci"; | |
| 612 | reg = <0x30100000 0x20000>; | |
| 613 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
| 614 | clocks = <&cru HCLK_HOST2>, <&u2phy1>; | |
| 615 | phys = <&u2phy1_host>; | |
| 616 | phy-names = "usb"; | |
| 617 | clock-names = "usbhost", "utmi"; | |
| 618 | status = "disabled"; | |
| 619 | }; | |
| 620 | ||
| 621 | usb_host2_ohci: usb@30120000 { | |
| 622 | compatible = "generic-ohci"; | |
| 623 | reg = <0x30120000 0x20000>; | |
| 624 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 625 | clocks = <&cru HCLK_HOST2>, <&u2phy1>; | |
| 626 | clock-names = "usbhost", "utmi"; | |
| 627 | phys = <&u2phy1_host>; | |
| 628 | phy-names = "usb"; | |
| 629 | status = "disabled"; | |
| 630 | }; | |
| 631 | ||
| 5d3d7c72 XZ |
632 | gmac: ethernet@30200000 { |
| 633 | compatible = "rockchip,rk3228-gmac"; | |
| 634 | reg = <0x30200000 0x10000>; | |
| 635 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 636 | interrupt-names = "macirq"; | |
| 637 | clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, | |
| 638 | <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, | |
| 639 | <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, | |
| 640 | <&cru PCLK_GMAC>; | |
| 641 | clock-names = "stmmaceth", "mac_clk_rx", | |
| 642 | "mac_clk_tx", "clk_mac_ref", | |
| 643 | "clk_mac_refout", "aclk_mac", | |
| 644 | "pclk_mac"; | |
| 645 | resets = <&cru SRST_GMAC>; | |
| 646 | reset-names = "stmmaceth"; | |
| 647 | rockchip,grf = <&grf>; | |
| 648 | status = "disabled"; | |
| 649 | }; | |
| 650 | ||
| 9848ebeb JC |
651 | gic: interrupt-controller@32010000 { |
| 652 | compatible = "arm,gic-400"; | |
| 653 | interrupt-controller; | |
| 654 | #interrupt-cells = <3>; | |
| 655 | #address-cells = <0>; | |
| 656 | ||
| 657 | reg = <0x32011000 0x1000>, | |
| 387720c9 | 658 | <0x32012000 0x2000>, |
| 9848ebeb JC |
659 | <0x32014000 0x2000>, |
| 660 | <0x32016000 0x2000>; | |
| 661 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 662 | }; | |
| 663 | ||
| 664 | pinctrl: pinctrl { | |
| 665 | compatible = "rockchip,rk3228-pinctrl"; | |
| 666 | rockchip,grf = <&grf>; | |
| 667 | #address-cells = <1>; | |
| 668 | #size-cells = <1>; | |
| 669 | ranges; | |
| 670 | ||
| 671 | gpio0: gpio0@11110000 { | |
| 672 | compatible = "rockchip,gpio-bank"; | |
| 673 | reg = <0x11110000 0x100>; | |
| 674 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
| 675 | clocks = <&cru PCLK_GPIO0>; | |
| 676 | ||
| 677 | gpio-controller; | |
| 678 | #gpio-cells = <2>; | |
| 679 | ||
| 680 | interrupt-controller; | |
| 681 | #interrupt-cells = <2>; | |
| 682 | }; | |
| 683 | ||
| 684 | gpio1: gpio1@11120000 { | |
| 685 | compatible = "rockchip,gpio-bank"; | |
| 686 | reg = <0x11120000 0x100>; | |
| 687 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 688 | clocks = <&cru PCLK_GPIO1>; | |
| 689 | ||
| 690 | gpio-controller; | |
| 691 | #gpio-cells = <2>; | |
| 692 | ||
| 693 | interrupt-controller; | |
| 694 | #interrupt-cells = <2>; | |
| 695 | }; | |
| 696 | ||
| 697 | gpio2: gpio2@11130000 { | |
| 698 | compatible = "rockchip,gpio-bank"; | |
| 699 | reg = <0x11130000 0x100>; | |
| 700 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
| 701 | clocks = <&cru PCLK_GPIO2>; | |
| 702 | ||
| 703 | gpio-controller; | |
| 704 | #gpio-cells = <2>; | |
| 705 | ||
| 706 | interrupt-controller; | |
| 707 | #interrupt-cells = <2>; | |
| 708 | }; | |
| 709 | ||
| 710 | gpio3: gpio3@11140000 { | |
| 711 | compatible = "rockchip,gpio-bank"; | |
| 712 | reg = <0x11140000 0x100>; | |
| 713 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
| 714 | clocks = <&cru PCLK_GPIO3>; | |
| 715 | ||
| 716 | gpio-controller; | |
| 717 | #gpio-cells = <2>; | |
| 718 | ||
| 719 | interrupt-controller; | |
| 720 | #interrupt-cells = <2>; | |
| 721 | }; | |
| 722 | ||
| 723 | pcfg_pull_up: pcfg-pull-up { | |
| 724 | bias-pull-up; | |
| 725 | }; | |
| 726 | ||
| 727 | pcfg_pull_down: pcfg-pull-down { | |
| 728 | bias-pull-down; | |
| 729 | }; | |
| 730 | ||
| 731 | pcfg_pull_none: pcfg-pull-none { | |
| 732 | bias-disable; | |
| 733 | }; | |
| 734 | ||
| 5d3d7c72 XZ |
735 | pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { |
| 736 | drive-strength = <12>; | |
| 737 | }; | |
| 738 | ||
| 9848ebeb JC |
739 | emmc { |
| 740 | emmc_clk: emmc-clk { | |
| 741 | rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; | |
| 742 | }; | |
| 743 | ||
| 744 | emmc_cmd: emmc-cmd { | |
| 745 | rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; | |
| 746 | }; | |
| 747 | ||
| 748 | emmc_bus8: emmc-bus8 { | |
| 749 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, | |
| 750 | <1 25 RK_FUNC_2 &pcfg_pull_none>, | |
| 751 | <1 26 RK_FUNC_2 &pcfg_pull_none>, | |
| 752 | <1 27 RK_FUNC_2 &pcfg_pull_none>, | |
| 753 | <1 28 RK_FUNC_2 &pcfg_pull_none>, | |
| 754 | <1 29 RK_FUNC_2 &pcfg_pull_none>, | |
| 755 | <1 30 RK_FUNC_2 &pcfg_pull_none>, | |
| 756 | <1 31 RK_FUNC_2 &pcfg_pull_none>; | |
| 757 | }; | |
| 758 | }; | |
| 759 | ||
| 5d3d7c72 XZ |
760 | gmac { |
| 761 | rgmii_pins: rgmii-pins { | |
| 762 | rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, | |
| 763 | <2 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 764 | <2 25 RK_FUNC_1 &pcfg_pull_none>, | |
| 765 | <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 766 | <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 767 | <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 768 | <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 769 | <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 770 | <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 771 | <2 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 772 | <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
| 773 | <2 21 RK_FUNC_2 &pcfg_pull_none>, | |
| 774 | <2 20 RK_FUNC_2 &pcfg_pull_none>, | |
| 775 | <2 11 RK_FUNC_1 &pcfg_pull_none>, | |
| 776 | <2 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 777 | }; | |
| 778 | ||
| 779 | rmii_pins: rmii-pins { | |
| 780 | rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, | |
| 781 | <2 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 782 | <2 25 RK_FUNC_1 &pcfg_pull_none>, | |
| 783 | <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 784 | <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 785 | <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 786 | <2 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 787 | <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
| 788 | <2 8 RK_FUNC_1 &pcfg_pull_none>, | |
| 789 | <2 15 RK_FUNC_1 &pcfg_pull_none>; | |
| 790 | }; | |
| 791 | ||
| 792 | phy_pins: phy-pins { | |
| 793 | rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, | |
| 794 | <2 8 RK_FUNC_2 &pcfg_pull_none>; | |
| 795 | }; | |
| 796 | }; | |
| 797 | ||
| d549df4b YY |
798 | i2c0 { |
| 799 | i2c0_xfer: i2c0-xfer { | |
| 800 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, | |
| 801 | <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 802 | }; | |
| 803 | }; | |
| 804 | ||
| 805 | i2c1 { | |
| 806 | i2c1_xfer: i2c1-xfer { | |
| 807 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, | |
| 808 | <0 3 RK_FUNC_1 &pcfg_pull_none>; | |
| 809 | }; | |
| 810 | }; | |
| 811 | ||
| 812 | i2c2 { | |
| 813 | i2c2_xfer: i2c2-xfer { | |
| 814 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, | |
| 815 | <2 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 816 | }; | |
| 817 | }; | |
| 818 | ||
| 819 | i2c3 { | |
| 820 | i2c3_xfer: i2c3-xfer { | |
| 821 | rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, | |
| 822 | <0 7 RK_FUNC_1 &pcfg_pull_none>; | |
| 823 | }; | |
| 824 | }; | |
| 825 | ||
| ccada248 XZ |
826 | i2s1 { |
| 827 | i2s1_bus: i2s1-bus { | |
| 828 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, | |
| 829 | <0 9 RK_FUNC_1 &pcfg_pull_none>, | |
| 830 | <0 11 RK_FUNC_1 &pcfg_pull_none>, | |
| 831 | <0 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 832 | <0 13 RK_FUNC_1 &pcfg_pull_none>, | |
| 833 | <0 14 RK_FUNC_1 &pcfg_pull_none>, | |
| 9d420e9b SZ |
834 | <1 2 RK_FUNC_2 &pcfg_pull_none>, |
| 835 | <1 4 RK_FUNC_2 &pcfg_pull_none>, | |
| 836 | <1 5 RK_FUNC_2 &pcfg_pull_none>; | |
| ccada248 XZ |
837 | }; |
| 838 | }; | |
| 839 | ||
| 9848ebeb JC |
840 | pwm0 { |
| 841 | pwm0_pin: pwm0-pin { | |
| 842 | rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 843 | }; | |
| 844 | }; | |
| 845 | ||
| 846 | pwm1 { | |
| 847 | pwm1_pin: pwm1-pin { | |
| 848 | rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; | |
| 849 | }; | |
| 850 | }; | |
| 851 | ||
| 852 | pwm2 { | |
| 853 | pwm2_pin: pwm2-pin { | |
| 854 | rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; | |
| 855 | }; | |
| 856 | }; | |
| 857 | ||
| 858 | pwm3 { | |
| 859 | pwm3_pin: pwm3-pin { | |
| 860 | rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; | |
| 861 | }; | |
| 862 | }; | |
| 863 | ||
| 4b456d20 SZ |
864 | spdif { |
| 865 | spdif_tx: spdif-tx { | |
| 866 | rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; | |
| 867 | }; | |
| 868 | }; | |
| 869 | ||
| 7796031e CW |
870 | tsadc { |
| 871 | otp_gpio: otp-gpio { | |
| 872 | rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; | |
| 873 | }; | |
| 874 | ||
| 875 | otp_out: otp-out { | |
| 876 | rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; | |
| 877 | }; | |
| 878 | }; | |
| 879 | ||
| 9848ebeb JC |
880 | uart0 { |
| 881 | uart0_xfer: uart0-xfer { | |
| 882 | rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, | |
| 883 | <2 27 RK_FUNC_1 &pcfg_pull_none>; | |
| 884 | }; | |
| 885 | ||
| 886 | uart0_cts: uart0-cts { | |
| 887 | rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; | |
| 888 | }; | |
| 889 | ||
| 890 | uart0_rts: uart0-rts { | |
| 891 | rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; | |
| 892 | }; | |
| 893 | }; | |
| 894 | ||
| 895 | uart1 { | |
| 896 | uart1_xfer: uart1-xfer { | |
| 897 | rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, | |
| 898 | <1 10 RK_FUNC_1 &pcfg_pull_none>; | |
| 899 | }; | |
| 900 | ||
| 901 | uart1_cts: uart1-cts { | |
| 902 | rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 903 | }; | |
| 904 | ||
| 905 | uart1_rts: uart1-rts { | |
| 906 | rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
| 907 | }; | |
| 908 | }; | |
| 909 | ||
| 910 | uart2 { | |
| 911 | uart2_xfer: uart2-xfer { | |
| 02131477 | 912 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, |
| 9848ebeb JC |
913 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
| 914 | }; | |
| 915 | ||
| 738e4511 FW |
916 | uart21_xfer: uart21-xfer { |
| 917 | rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, | |
| 918 | <1 9 RK_FUNC_2 &pcfg_pull_none>; | |
| 919 | }; | |
| 920 | ||
| 9848ebeb JC |
921 | uart2_cts: uart2-cts { |
| 922 | rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; | |
| 923 | }; | |
| 924 | ||
| 925 | uart2_rts: uart2-rts { | |
| 926 | rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; | |
| 927 | }; | |
| 928 | }; | |
| 929 | }; | |
| 930 | }; |