[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / rk322x.dtsi

/*
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			resets = <&cru SRST_CORE0>;
			operating-points-v2 = <&cpu0_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};

		cpu1: cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			resets = <&cru SRST_CORE1>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu2: cpu@f02 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
			resets = <&cru SRST_CORE2>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu3: cpu@f03 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
			resets = <&cru SRST_CORE3>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
	};

	cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <950000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <975000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1000000>;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1175000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1275000>;
		};
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pdma: pdma@110f0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x110f0000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMAC>;
			clock-names = "apb_pclk";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	i2s1: i2s1@100b0000 {
		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
		reg = <0x100b0000 0x4000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
		dmas = <&pdma 14>, <&pdma 15>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		status = "disabled";
	};

	i2s0: i2s0@100c0000 {
		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
		reg = <0x100c0000 0x4000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
		dmas = <&pdma 11>, <&pdma 12>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	i2s2: i2s2@100e0000 {
		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
		reg = <0x100e0000 0x4000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
		dmas = <&pdma 0>, <&pdma 1>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	grf: syscon@11000000 {
		compatible = "syscon";
		reg = <0x11000000 0x1000>;
	};

	uart0: serial@11010000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x11010000 0x100>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart1: serial@11020000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x11020000 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart2: serial@11030000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x11030000 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	i2c0: i2c@11050000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11050000 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		status = "disabled";
	};

	i2c1: i2c@11060000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11060000 0x1000>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C1>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		status = "disabled";
	};

	i2c2: i2c@11070000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11070000 0x1000>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C2>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		status = "disabled";
	};

	i2c3: i2c@11080000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11080000 0x1000>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C3>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		status = "disabled";
	};

	wdt: watchdog@110a0000 {
		compatible = "snps,dw-wdt";
		reg = <0x110a0000 0x100>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_CPU>;
		status = "disabled";
	};

	pwm0: pwm@110b0000 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0000 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pin>;
		status = "disabled";
	};

	pwm1: pwm@110b0010 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0010 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_pin>;
		status = "disabled";
	};

	pwm2: pwm@110b0020 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0020 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_pin>;
		status = "disabled";
	};

	pwm3: pwm@110b0030 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0030 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3_pin>;
		status = "disabled";
	};

	timer: timer@110c0000 {
		compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
		reg = <0x110c0000 0x20>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&xin24m>, <&cru PCLK_TIMER>;
		clock-names = "timer", "pclk";
	};

	cru: clock-controller@110e0000 {
		compatible = "rockchip,rk3228-cru";
		reg = <0x110e0000 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks =
			<&cru PLL_GPLL>, <&cru ARMCLK>,
			<&cru PLL_CPLL>, <&cru ACLK_PERI>,
			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
			<&cru ACLK_CPU>, <&cru HCLK_CPU>,
			<&cru PCLK_CPU>;
		assigned-clock-rates =
			<594000000>, <816000000>,
			<500000000>, <150000000>,
			<150000000>, <75000000>,
			<150000000>, <150000000>,
			<75000000>;
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <100>; /* milliseconds */
			polling-delay = <5000>; /* milliseconds */

			thermal-sensors = <&tsadc 0>;

			trips {
				cpu_alert0: cpu_alert0 {
					temperature = <70000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				cpu_alert1: cpu_alert1 {
					temperature = <75000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				cpu_crit: cpu_crit {
					temperature = <90000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT 6>;
				};
				map1 {
					trip = <&cpu_alert1>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	tsadc: tsadc@11150000 {
		compatible = "rockchip,rk3228-tsadc";
		reg = <0x11150000 0x100>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <&cru SCLK_TSADC>;
		assigned-clock-rates = <32768>;
		resets = <&cru SRST_TSADC>;
		reset-names = "tsadc-apb";
		pinctrl-names = "init", "default", "sleep";
		pinctrl-0 = <&otp_gpio>;
		pinctrl-1 = <&otp_out>;
		pinctrl-2 = <&otp_gpio>;
		#thermal-sensor-cells = <0>;
		rockchip,hw-tshut-temp = <95000>;
		status = "disabled";
	};

	emmc: dwmmc@30020000 {
		compatible = "rockchip,rk3288-dw-mshc";
		reg = <0x30020000 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <37500000>;
		max-frequency = <37500000>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
		bus-width = <8>;
		default-sample-phase = <158>;
		num-slots = <1>;
		fifo-depth = <0x100>;
		pinctrl-names = "default";
		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
		resets = <&cru SRST_EMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	gmac: ethernet@30200000 {
		compatible = "rockchip,rk3228-gmac";
		reg = <0x30200000 0x10000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
			<&cru PCLK_GMAC>;
		clock-names = "stmmaceth", "mac_clk_rx",
			"mac_clk_tx", "clk_mac_ref",
			"clk_mac_refout", "aclk_mac",
			"pclk_mac";
		resets = <&cru SRST_GMAC>;
		reset-names = "stmmaceth";
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	gic: interrupt-controller@32010000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0x32011000 0x1000>,
		      <0x32012000 0x2000>,
		      <0x32014000 0x2000>,
		      <0x32016000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3228-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@11110000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11110000 0x100>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@11120000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11120000 0x100>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@11130000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11130000 0x100>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@11140000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11140000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg-pull-up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
			drive-strength = <12>;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_bus8: emmc-bus8 {
				rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
						<1 25 RK_FUNC_2 &pcfg_pull_none>,
						<1 26 RK_FUNC_2 &pcfg_pull_none>,
						<1 27 RK_FUNC_2 &pcfg_pull_none>,
						<1 28 RK_FUNC_2 &pcfg_pull_none>,
						<1 29 RK_FUNC_2 &pcfg_pull_none>,
						<1 30 RK_FUNC_2 &pcfg_pull_none>,
						<1 31 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		gmac {
			rgmii_pins: rgmii-pins {
				rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
						<2 12 RK_FUNC_1 &pcfg_pull_none>,
						<2 25 RK_FUNC_1 &pcfg_pull_none>,
						<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 17 RK_FUNC_1 &pcfg_pull_none>,
						<2 16 RK_FUNC_1 &pcfg_pull_none>,
						<2 21 RK_FUNC_2 &pcfg_pull_none>,
						<2 20 RK_FUNC_2 &pcfg_pull_none>,
						<2 11 RK_FUNC_1 &pcfg_pull_none>,
						<2 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			rmii_pins: rmii-pins {
				rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
						<2 12 RK_FUNC_1 &pcfg_pull_none>,
						<2 25 RK_FUNC_1 &pcfg_pull_none>,
						<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 17 RK_FUNC_1 &pcfg_pull_none>,
						<2 16 RK_FUNC_1 &pcfg_pull_none>,
						<2 8 RK_FUNC_1 &pcfg_pull_none>,
						<2 15 RK_FUNC_1 &pcfg_pull_none>;
			};

			phy_pins: phy-pins {
				rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
						<2 8 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
						<0 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
						<0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
						<2 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
						<0 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s1 {
			i2s1_bus: i2s1-bus {
				rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
						<0 9 RK_FUNC_1 &pcfg_pull_none>,
						<0 11 RK_FUNC_1 &pcfg_pull_none>,
						<0 12 RK_FUNC_1 &pcfg_pull_none>,
						<0 13 RK_FUNC_1 &pcfg_pull_none>,
						<0 14 RK_FUNC_1 &pcfg_pull_none>,
						<1 2 RK_FUNC_2 &pcfg_pull_none>,
						<1 4 RK_FUNC_2 &pcfg_pull_none>,
						<1 5 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_pin: pwm3-pin {
				rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		tsadc {
			otp_gpio: otp-gpio {
				rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
			};

			otp_out: otp-out {
				rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
						<2 27 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
						<1 10 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
						<1 19 RK_FUNC_2 &pcfg_pull_none>;
			};

			uart21_xfer: uart21-xfer {
				rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
						<1 9 RK_FUNC_2 &pcfg_pull_none>;
			};

			uart2_cts: uart2-cts {
				rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart2_rts: uart2-rts {
				rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
			};
		};
	};
};
Commit	Line	Data
9848ebeb JC	1	/*
	2	* This file is dual-licensed: you can use it either under the terms
	3	* of the GPL or the X11 license, at your option. Note that this dual
	4	* licensing only applies to this file, and not this project as a
	5	* whole.
	6	*
	7	* a) This file is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of the
	10	* License, or (at your option) any later version.
	11	*
	12	* This file is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* Or, alternatively,
	18	*
	19	* b) Permission is hereby granted, free of charge, to any person
	20	* obtaining a copy of this software and associated documentation
	21	* files (the "Software"), to deal in the Software without
	22	* restriction, including without limitation the rights to use,
	23	* copy, modify, merge, publish, distribute, sublicense, and/or
	24	* sell copies of the Software, and to permit persons to whom the
	25	* Software is furnished to do so, subject to the following
	26	* conditions:
	27	*
	28	* The above copyright notice and this permission notice shall be
	29	* included in all copies or substantial portions of the Software.
	30	*
	31	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	32	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	33	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	34	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	35	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	36	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	37	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	38	* OTHER DEALINGS IN THE SOFTWARE.
	39	*/
	40
	41	#include <dt-bindings/gpio/gpio.h>
	42	#include <dt-bindings/interrupt-controller/irq.h>
	43	#include <dt-bindings/interrupt-controller/arm-gic.h>
	44	#include <dt-bindings/pinctrl/rockchip.h>
	45	#include <dt-bindings/clock/rk3228-cru.h>
7796031e	46	#include <dt-bindings/thermal/thermal.h>
9848ebeb JC	47
9848ebeb JC	48	/ {
0193273d JMC	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51
9848ebeb JC	52	interrupt-parent = <&gic>;
	53
	54	aliases {
	55	serial0 = &uart0;
	56	serial1 = &uart1;
	57	serial2 = &uart2;
	58	};
	59
	60	cpus {
	61	#address-cells = <1>;
	62	#size-cells = <0>;
	63
	64	cpu0: cpu@f00 {
	65	device_type = "cpu";
	66	compatible = "arm,cortex-a7";
	67	reg = <0xf00>;
	68	resets = <&cru SRST_CORE0>;
9f12da43	69	operating-points-v2 = <&cpu0_opp_table>;
7796031e	70	#cooling-cells = <2>; /* min followed by max */
9848ebeb JC	71	clock-latency = <40000>;
	72	clocks = <&cru ARMCLK>;
	73	};
	74
	75	cpu1: cpu@f01 {
	76	device_type = "cpu";
	77	compatible = "arm,cortex-a7";
	78	reg = <0xf01>;
	79	resets = <&cru SRST_CORE1>;
9f12da43	80	operating-points-v2 = <&cpu0_opp_table>;
9848ebeb JC	81	};
	82
	83	cpu2: cpu@f02 {
	84	device_type = "cpu";
	85	compatible = "arm,cortex-a7";
	86	reg = <0xf02>;
	87	resets = <&cru SRST_CORE2>;
9f12da43	88	operating-points-v2 = <&cpu0_opp_table>;
9848ebeb JC	89	};
	90
	91	cpu3: cpu@f03 {
	92	device_type = "cpu";
	93	compatible = "arm,cortex-a7";
	94	reg = <0xf03>;
	95	resets = <&cru SRST_CORE3>;
9f12da43 FX	96	operating-points-v2 = <&cpu0_opp_table>;
	97	};
	98	};
	99
	100	cpu0_opp_table: opp_table0 {
	101	compatible = "operating-points-v2";
	102	opp-shared;
	103
	104	opp-408000000 {
	105	opp-hz = /bits/ 64 <408000000>;
	106	opp-microvolt = <950000>;
	107	clock-latency-ns = <40000>;
	108	opp-suspend;
	109	};
	110	opp-600000000 {
	111	opp-hz = /bits/ 64 <600000000>;
	112	opp-microvolt = <975000>;
	113	};
	114	opp-816000000 {
	115	opp-hz = /bits/ 64 <816000000>;
	116	opp-microvolt = <1000000>;
	117	};
	118	opp-1008000000 {
	119	opp-hz = /bits/ 64 <1008000000>;
	120	opp-microvolt = <1175000>;
	121	};
	122	opp-1200000000 {
	123	opp-hz = /bits/ 64 <1200000000>;
	124	opp-microvolt = <1275000>;
9848ebeb JC	125	};
	126	};
	127
	128	amba {
2ef7d5f3	129	compatible = "simple-bus";
9848ebeb JC	130	#address-cells = <1>;
	131	#size-cells = <1>;
	132	ranges;
	133
	134	pdma: pdma@110f0000 {
	135	compatible = "arm,pl330", "arm,primecell";
	136	reg = <0x110f0000 0x4000>;
	137	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	138	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	139	#dma-cells = <1>;
	140	clocks = <&cru ACLK_DMAC>;
	141	clock-names = "apb_pclk";
	142	};
	143	};
	144
	145	arm-pmu {
	146	compatible = "arm,cortex-a7-pmu";
	147	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	148	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
	149	<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
	150	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	151	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	152	};
	153
	154	timer {
	155	compatible = "arm,armv7-timer";
	156	arm,cpu-registers-not-fw-configured;
	157	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	158	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	159	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	160	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	161	clock-frequency = <24000000>;
	162	};
	163
	164	xin24m: oscillator {
	165	compatible = "fixed-clock";
	166	clock-frequency = <24000000>;
	167	clock-output-names = "xin24m";
	168	#clock-cells = <0>;
	169	};
	170
ccada248 XZ	171	i2s1: i2s1@100b0000 {
	172	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	173	reg = <0x100b0000 0x4000>;
	174	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177	clock-names = "i2s_clk", "i2s_hclk";
	178	clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
	179	dmas = <&pdma 14>, <&pdma 15>;
	180	dma-names = "tx", "rx";
	181	pinctrl-names = "default";
	182	pinctrl-0 = <&i2s1_bus>;
	183	status = "disabled";
	184	};
	185
	186	i2s0: i2s0@100c0000 {
	187	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	188	reg = <0x100c0000 0x4000>;
	189	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	190	#address-cells = <1>;
	191	#size-cells = <0>;
	192	clock-names = "i2s_clk", "i2s_hclk";
	193	clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
	194	dmas = <&pdma 11>, <&pdma 12>;
	195	dma-names = "tx", "rx";
	196	status = "disabled";
	197	};
	198
	199	i2s2: i2s2@100e0000 {
	200	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	201	reg = <0x100e0000 0x4000>;
	202	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	clock-names = "i2s_clk", "i2s_hclk";
	206	clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
	207	dmas = <&pdma 0>, <&pdma 1>;
	208	dma-names = "tx", "rx";
	209	status = "disabled";
	210	};
	211
9848ebeb JC	212	grf: syscon@11000000 {
	213	compatible = "syscon";
	214	reg = <0x11000000 0x1000>;
	215	};
	216
	217	uart0: serial@11010000 {
	218	compatible = "snps,dw-apb-uart";
	219	reg = <0x11010000 0x100>;
	220	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	221	clock-frequency = <24000000>;
	222	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	223	clock-names = "baudclk", "apb_pclk";
	224	pinctrl-names = "default";
	225	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	226	reg-shift = <2>;
	227	reg-io-width = <4>;
	228	status = "disabled";
	229	};
	230
	231	uart1: serial@11020000 {
	232	compatible = "snps,dw-apb-uart";
	233	reg = <0x11020000 0x100>;
	234	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	235	clock-frequency = <24000000>;
	236	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	237	clock-names = "baudclk", "apb_pclk";
	238	pinctrl-names = "default";
	239	pinctrl-0 = <&uart1_xfer>;
	240	reg-shift = <2>;
	241	reg-io-width = <4>;
	242	status = "disabled";
	243	};
	244
	245	uart2: serial@11030000 {
	246	compatible = "snps,dw-apb-uart";
	247	reg = <0x11030000 0x100>;
	248	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	249	clock-frequency = <24000000>;
	250	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	251	clock-names = "baudclk", "apb_pclk";
	252	pinctrl-names = "default";
	253	pinctrl-0 = <&uart2_xfer>;
	254	reg-shift = <2>;
	255	reg-io-width = <4>;
	256	status = "disabled";
	257	};
	258
d549df4b YY	259	i2c0: i2c@11050000 {
	260	compatible = "rockchip,rk3228-i2c";
	261	reg = <0x11050000 0x1000>;
	262	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	263	#address-cells = <1>;
	264	#size-cells = <0>;
	265	clock-names = "i2c";
	266	clocks = <&cru PCLK_I2C0>;
	267	pinctrl-names = "default";
	268	pinctrl-0 = <&i2c0_xfer>;
	269	status = "disabled";
	270	};
	271
	272	i2c1: i2c@11060000 {
	273	compatible = "rockchip,rk3228-i2c";
	274	reg = <0x11060000 0x1000>;
	275	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	276	#address-cells = <1>;
	277	#size-cells = <0>;
	278	clock-names = "i2c";
	279	clocks = <&cru PCLK_I2C1>;
	280	pinctrl-names = "default";
	281	pinctrl-0 = <&i2c1_xfer>;
	282	status = "disabled";
	283	};
	284
	285	i2c2: i2c@11070000 {
	286	compatible = "rockchip,rk3228-i2c";
	287	reg = <0x11070000 0x1000>;
	288	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	289	#address-cells = <1>;
	290	#size-cells = <0>;
	291	clock-names = "i2c";
	292	clocks = <&cru PCLK_I2C2>;
	293	pinctrl-names = "default";
	294	pinctrl-0 = <&i2c2_xfer>;
	295	status = "disabled";
	296	};
	297
	298	i2c3: i2c@11080000 {
	299	compatible = "rockchip,rk3228-i2c";
	300	reg = <0x11080000 0x1000>;
	301	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	302	#address-cells = <1>;
	303	#size-cells = <0>;
	304	clock-names = "i2c";
	305	clocks = <&cru PCLK_I2C3>;
	306	pinctrl-names = "default";
	307	pinctrl-0 = <&i2c3_xfer>;
	308	status = "disabled";
	309	};
	310
fa206984 FW	311	wdt: watchdog@110a0000 {
	312	compatible = "snps,dw-wdt";
	313	reg = <0x110a0000 0x100>;
	314	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	315	clocks = <&cru PCLK_CPU>;
	316	status = "disabled";
	317	};
	318
9848ebeb JC	319	pwm0: pwm@110b0000 {
	320	compatible = "rockchip,rk3288-pwm";
	321	reg = <0x110b0000 0x10>;
	322	#pwm-cells = <3>;
	323	clocks = <&cru PCLK_PWM>;
	324	clock-names = "pwm";
	325	pinctrl-names = "default";
	326	pinctrl-0 = <&pwm0_pin>;
	327	status = "disabled";
	328	};
	329
	330	pwm1: pwm@110b0010 {
	331	compatible = "rockchip,rk3288-pwm";
	332	reg = <0x110b0010 0x10>;
	333	#pwm-cells = <3>;
	334	clocks = <&cru PCLK_PWM>;
	335	clock-names = "pwm";
	336	pinctrl-names = "default";
	337	pinctrl-0 = <&pwm1_pin>;
	338	status = "disabled";
	339	};
	340
	341	pwm2: pwm@110b0020 {
	342	compatible = "rockchip,rk3288-pwm";
	343	reg = <0x110b0020 0x10>;
	344	#pwm-cells = <3>;
	345	clocks = <&cru PCLK_PWM>;
	346	clock-names = "pwm";
	347	pinctrl-names = "default";
	348	pinctrl-0 = <&pwm2_pin>;
	349	status = "disabled";
	350	};
	351
	352	pwm3: pwm@110b0030 {
	353	compatible = "rockchip,rk3288-pwm";
	354	reg = <0x110b0030 0x10>;
	355	#pwm-cells = <2>;
	356	clocks = <&cru PCLK_PWM>;
	357	clock-names = "pwm";
	358	pinctrl-names = "default";
	359	pinctrl-0 = <&pwm3_pin>;
	360	status = "disabled";
	361	};
	362
	363	timer: timer@110c0000 {
b72af346	364	compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
9848ebeb JC	365	reg = <0x110c0000 0x20>;
	366	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	367	clocks = <&xin24m>, <&cru PCLK_TIMER>;
	368	clock-names = "timer", "pclk";
	369	};
	370
	371	cru: clock-controller@110e0000 {
	372	compatible = "rockchip,rk3228-cru";
	373	reg = <0x110e0000 0x1000>;
	374	rockchip,grf = <&grf>;
	375	#clock-cells = <1>;
	376	#reset-cells = <1>;
30ee5814 EZ	377	assigned-clocks =
	378	<&cru PLL_GPLL>, <&cru ARMCLK>,
	379	<&cru PLL_CPLL>, <&cru ACLK_PERI>,
	380	<&cru HCLK_PERI>, <&cru PCLK_PERI>,
	381	<&cru ACLK_CPU>, <&cru HCLK_CPU>,
	382	<&cru PCLK_CPU>;
	383	assigned-clock-rates =
	384	<594000000>, <816000000>,
	385	<500000000>, <150000000>,
	386	<150000000>, <75000000>,
	387	<150000000>, <150000000>,
	388	<75000000>;
9848ebeb JC	389	};
9848ebeb JC	390
7796031e CW	391	thermal-zones {
	392	cpu_thermal: cpu-thermal {
	393	polling-delay-passive = <100>; /* milliseconds */
	394	polling-delay = <5000>; /* milliseconds */
	395
	396	thermal-sensors = <&tsadc 0>;
	397
	398	trips {
	399	cpu_alert0: cpu_alert0 {
	400	temperature = <70000>; /* millicelsius */
	401	hysteresis = <2000>; /* millicelsius */
	402	type = "passive";
	403	};
	404	cpu_alert1: cpu_alert1 {
	405	temperature = <75000>; /* millicelsius */
	406	hysteresis = <2000>; /* millicelsius */
	407	type = "passive";
	408	};
	409	cpu_crit: cpu_crit {
	410	temperature = <90000>; /* millicelsius */
	411	hysteresis = <2000>; /* millicelsius */
	412	type = "critical";
	413	};
	414	};
	415
	416	cooling-maps {
	417	map0 {
	418	trip = <&cpu_alert0>;
	419	cooling-device =
	420	<&cpu0 THERMAL_NO_LIMIT 6>;
	421	};
	422	map1 {
	423	trip = <&cpu_alert1>;
	424	cooling-device =
	425	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	426	};
	427	};
	428	};
	429	};
	430
	431	tsadc: tsadc@11150000 {
	432	compatible = "rockchip,rk3228-tsadc";
	433	reg = <0x11150000 0x100>;
	434	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	435	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	436	clock-names = "tsadc", "apb_pclk";
2b3f2f37 RH	437	assigned-clocks = <&cru SCLK_TSADC>;
2b3f2f37 RH	438	assigned-clock-rates = <32768>;
7796031e CW	439	resets = <&cru SRST_TSADC>;
	440	reset-names = "tsadc-apb";
	441	pinctrl-names = "init", "default", "sleep";
	442	pinctrl-0 = <&otp_gpio>;
	443	pinctrl-1 = <&otp_out>;
	444	pinctrl-2 = <&otp_gpio>;
	445	#thermal-sensor-cells = <0>;
	446	rockchip,hw-tshut-temp = <95000>;
	447	status = "disabled";
	448	};
	449
9848ebeb JC	450	emmc: dwmmc@30020000 {
	451	compatible = "rockchip,rk3288-dw-mshc";
	452	reg = <0x30020000 0x4000>;
	453	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	454	clock-frequency = <37500000>;
6a8883d6	455	max-frequency = <37500000>;
9848ebeb JC	456	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	457	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	458	clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
	459	bus-width = <8>;
	460	default-sample-phase = <158>;
	461	num-slots = <1>;
	462	fifo-depth = <0x100>;
	463	pinctrl-names = "default";
	464	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
2d1f1d4c HS	465	resets = <&cru SRST_EMMC>;
2d1f1d4c HS	466	reset-names = "reset";
9848ebeb JC	467	status = "disabled";
	468	};
	469
5d3d7c72 XZ	470	gmac: ethernet@30200000 {
	471	compatible = "rockchip,rk3228-gmac";
	472	reg = <0x30200000 0x10000>;
	473	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	474	interrupt-names = "macirq";
	475	clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
	476	<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
	477	<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
	478	<&cru PCLK_GMAC>;
	479	clock-names = "stmmaceth", "mac_clk_rx",
	480	"mac_clk_tx", "clk_mac_ref",
	481	"clk_mac_refout", "aclk_mac",
	482	"pclk_mac";
	483	resets = <&cru SRST_GMAC>;
	484	reset-names = "stmmaceth";
	485	rockchip,grf = <&grf>;
	486	status = "disabled";
	487	};
	488
9848ebeb JC	489	gic: interrupt-controller@32010000 {
	490	compatible = "arm,gic-400";
	491	interrupt-controller;
	492	#interrupt-cells = <3>;
	493	#address-cells = <0>;
	494
	495	reg = <0x32011000 0x1000>,
387720c9	496	<0x32012000 0x2000>,
9848ebeb JC	497	<0x32014000 0x2000>,
	498	<0x32016000 0x2000>;
	499	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	500	};
	501
	502	pinctrl: pinctrl {
	503	compatible = "rockchip,rk3228-pinctrl";
	504	rockchip,grf = <&grf>;
	505	#address-cells = <1>;
	506	#size-cells = <1>;
	507	ranges;
	508
	509	gpio0: gpio0@11110000 {
	510	compatible = "rockchip,gpio-bank";
	511	reg = <0x11110000 0x100>;
	512	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	513	clocks = <&cru PCLK_GPIO0>;
	514
	515	gpio-controller;
	516	#gpio-cells = <2>;
	517
	518	interrupt-controller;
	519	#interrupt-cells = <2>;
	520	};
	521
	522	gpio1: gpio1@11120000 {
	523	compatible = "rockchip,gpio-bank";
	524	reg = <0x11120000 0x100>;
	525	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	526	clocks = <&cru PCLK_GPIO1>;
	527
	528	gpio-controller;
	529	#gpio-cells = <2>;
	530
	531	interrupt-controller;
	532	#interrupt-cells = <2>;
	533	};
	534
	535	gpio2: gpio2@11130000 {
	536	compatible = "rockchip,gpio-bank";
	537	reg = <0x11130000 0x100>;
	538	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	539	clocks = <&cru PCLK_GPIO2>;
	540
	541	gpio-controller;
	542	#gpio-cells = <2>;
	543
	544	interrupt-controller;
	545	#interrupt-cells = <2>;
	546	};
	547
	548	gpio3: gpio3@11140000 {
	549	compatible = "rockchip,gpio-bank";
	550	reg = <0x11140000 0x100>;
	551	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	552	clocks = <&cru PCLK_GPIO3>;
	553
	554	gpio-controller;
	555	#gpio-cells = <2>;
	556
	557	interrupt-controller;
	558	#interrupt-cells = <2>;
	559	};
	560
561	pcfg_pull_up: pcfg-pull-up {
562	bias-pull-up;
563	};
564
565	pcfg_pull_down: pcfg-pull-down {
566	bias-pull-down;
567	};
568
569	pcfg_pull_none: pcfg-pull-none {
570	bias-disable;
571	};
572
5d3d7c72 XZ	573	pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
	574	drive-strength = <12>;
	575	};
	576
9848ebeb JC	577	emmc {
	578	emmc_clk: emmc-clk {
	579	rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
	580	};
	581
	582	emmc_cmd: emmc-cmd {
	583	rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
	584	};
	585
	586	emmc_bus8: emmc-bus8 {
	587	rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
	588	<1 25 RK_FUNC_2 &pcfg_pull_none>,
	589	<1 26 RK_FUNC_2 &pcfg_pull_none>,
	590	<1 27 RK_FUNC_2 &pcfg_pull_none>,
	591	<1 28 RK_FUNC_2 &pcfg_pull_none>,
	592	<1 29 RK_FUNC_2 &pcfg_pull_none>,
	593	<1 30 RK_FUNC_2 &pcfg_pull_none>,
	594	<1 31 RK_FUNC_2 &pcfg_pull_none>;
	595	};
	596	};
	597
5d3d7c72 XZ	598	gmac {
	599	rgmii_pins: rgmii-pins {
	600	rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
	601	<2 12 RK_FUNC_1 &pcfg_pull_none>,
	602	<2 25 RK_FUNC_1 &pcfg_pull_none>,
	603	<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	604	<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	605	<2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	606	<2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	607	<2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	608	<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	609	<2 17 RK_FUNC_1 &pcfg_pull_none>,
	610	<2 16 RK_FUNC_1 &pcfg_pull_none>,
	611	<2 21 RK_FUNC_2 &pcfg_pull_none>,
	612	<2 20 RK_FUNC_2 &pcfg_pull_none>,
	613	<2 11 RK_FUNC_1 &pcfg_pull_none>,
	614	<2 8 RK_FUNC_1 &pcfg_pull_none>;
	615	};
	616
	617	rmii_pins: rmii-pins {
	618	rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
	619	<2 12 RK_FUNC_1 &pcfg_pull_none>,
	620	<2 25 RK_FUNC_1 &pcfg_pull_none>,
	621	<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	622	<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	623	<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	624	<2 17 RK_FUNC_1 &pcfg_pull_none>,
	625	<2 16 RK_FUNC_1 &pcfg_pull_none>,
	626	<2 8 RK_FUNC_1 &pcfg_pull_none>,
	627	<2 15 RK_FUNC_1 &pcfg_pull_none>;
	628	};
	629
	630	phy_pins: phy-pins {
	631	rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
	632	<2 8 RK_FUNC_2 &pcfg_pull_none>;
	633	};
	634	};
	635
d549df4b YY	636	i2c0 {
	637	i2c0_xfer: i2c0-xfer {
	638	rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
	639	<0 1 RK_FUNC_1 &pcfg_pull_none>;
	640	};
	641	};
	642
	643	i2c1 {
	644	i2c1_xfer: i2c1-xfer {
	645	rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
	646	<0 3 RK_FUNC_1 &pcfg_pull_none>;
	647	};
	648	};
	649
	650	i2c2 {
	651	i2c2_xfer: i2c2-xfer {
	652	rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
	653	<2 21 RK_FUNC_1 &pcfg_pull_none>;
	654	};
	655	};
	656
	657	i2c3 {
	658	i2c3_xfer: i2c3-xfer {
	659	rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
	660	<0 7 RK_FUNC_1 &pcfg_pull_none>;
	661	};
	662	};
	663
ccada248 XZ	664	i2s1 {
	665	i2s1_bus: i2s1-bus {
	666	rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
	667	<0 9 RK_FUNC_1 &pcfg_pull_none>,
	668	<0 11 RK_FUNC_1 &pcfg_pull_none>,
	669	<0 12 RK_FUNC_1 &pcfg_pull_none>,
	670	<0 13 RK_FUNC_1 &pcfg_pull_none>,
	671	<0 14 RK_FUNC_1 &pcfg_pull_none>,
9d420e9b SZ	672	<1 2 RK_FUNC_2 &pcfg_pull_none>,
	673	<1 4 RK_FUNC_2 &pcfg_pull_none>,
	674	<1 5 RK_FUNC_2 &pcfg_pull_none>;
ccada248 XZ	675	};
	676	};
	677
9848ebeb JC	678	pwm0 {
	679	pwm0_pin: pwm0-pin {
	680	rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
	681	};
	682	};
	683
	684	pwm1 {
	685	pwm1_pin: pwm1-pin {
	686	rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
	687	};
	688	};
	689
	690	pwm2 {
	691	pwm2_pin: pwm2-pin {
	692	rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
	693	};
	694	};
	695
	696	pwm3 {
	697	pwm3_pin: pwm3-pin {
	698	rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
	699	};
	700	};
	701
7796031e CW	702	tsadc {
	703	otp_gpio: otp-gpio {
	704	rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
	705	};
	706
	707	otp_out: otp-out {
	708	rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
	709	};
	710	};
	711
9848ebeb JC	712	uart0 {
	713	uart0_xfer: uart0-xfer {
	714	rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
	715	<2 27 RK_FUNC_1 &pcfg_pull_none>;
	716	};
	717
	718	uart0_cts: uart0-cts {
	719	rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
	720	};
	721
	722	uart0_rts: uart0-rts {
	723	rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
	724	};
	725	};
	726
	727	uart1 {
	728	uart1_xfer: uart1-xfer {
	729	rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
	730	<1 10 RK_FUNC_1 &pcfg_pull_none>;
	731	};
	732
	733	uart1_cts: uart1-cts {
	734	rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
	735	};
	736
	737	uart1_rts: uart1-rts {
	738	rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
	739	};
	740	};
	741
	742	uart2 {
	743	uart2_xfer: uart2-xfer {
02131477	744	rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
9848ebeb JC	745	<1 19 RK_FUNC_2 &pcfg_pull_none>;
	746	};
	747
738e4511 FW	748	uart21_xfer: uart21-xfer {
	749	rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
	750	<1 9 RK_FUNC_2 &pcfg_pull_none>;
	751	};
	752
9848ebeb JC	753	uart2_cts: uart2-cts {
	754	rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
	755	};
	756
	757	uart2_rts: uart2-rts {
	758	rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
	759	};
	760	};
	761	};
	762	};