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e28ea9db AS |
1 | /* |
2 | * Google Veyron (and derivatives) board device tree source | |
3 | * | |
4 | * Copyright 2015 Google, Inc | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
11 | * a) This file is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * Or, alternatively, | |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
45 | #include <dt-bindings/clock/rockchip,rk808.h> | |
46 | #include <dt-bindings/input/input.h> | |
47 | #include "rk3288.dtsi" | |
48 | ||
49 | / { | |
50 | memory { | |
51 | device_type = "memory"; | |
52 | reg = <0x0 0x80000000>; | |
53 | }; | |
54 | ||
55 | gpio_keys: gpio-keys { | |
56 | compatible = "gpio-keys"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | ||
60 | pinctrl-names = "default"; | |
61 | pinctrl-0 = <&pwr_key_l>; | |
62 | power { | |
63 | label = "Power"; | |
64 | gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; | |
65 | linux,code = <KEY_POWER>; | |
66 | debounce-interval = <100>; | |
67 | gpio-key,wakeup; | |
68 | }; | |
69 | }; | |
70 | ||
71 | gpio-restart { | |
72 | compatible = "gpio-restart"; | |
73 | gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; | |
74 | pinctrl-names = "default"; | |
75 | pinctrl-0 = <&ap_warm_reset_h>; | |
76 | priority = <200>; | |
77 | }; | |
78 | ||
79 | emmc_pwrseq: emmc-pwrseq { | |
80 | compatible = "mmc-pwrseq-emmc"; | |
81 | pinctrl-0 = <&emmc_reset>; | |
82 | pinctrl-names = "default"; | |
83 | reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; | |
84 | }; | |
85 | ||
86 | io_domains: io-domains { | |
87 | compatible = "rockchip,rk3288-io-voltage-domain"; | |
88 | rockchip,grf = <&grf>; | |
89 | ||
90 | bb-supply = <&vcc33_io>; | |
91 | dvp-supply = <&vcc_18>; | |
92 | flash0-supply = <&vcc18_flashio>; | |
93 | gpio1830-supply = <&vcc33_io>; | |
94 | gpio30-supply = <&vcc33_io>; | |
95 | lcdc-supply = <&vcc33_lcd>; | |
96 | wifi-supply = <&vcc18_wl>; | |
97 | }; | |
98 | ||
99 | sdio_pwrseq: sdio-pwrseq { | |
100 | compatible = "mmc-pwrseq-simple"; | |
101 | clocks = <&rk808 RK808_CLKOUT1>; | |
102 | clock-names = "ext_clock"; | |
103 | pinctrl-names = "default"; | |
104 | pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; | |
105 | ||
106 | /* | |
107 | * On the module itself this is one of these (depending | |
108 | * on the actual card populated): | |
109 | * - SDIO_RESET_L_WL_REG_ON | |
110 | * - PDN (power down when low) | |
111 | */ | |
112 | reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; | |
113 | }; | |
114 | ||
115 | vcc_5v: vcc-5v { | |
116 | compatible = "regulator-fixed"; | |
117 | regulator-name = "vcc_5v"; | |
118 | regulator-always-on; | |
119 | regulator-boot-on; | |
120 | regulator-min-microvolt = <5000000>; | |
121 | regulator-max-microvolt = <5000000>; | |
122 | }; | |
123 | ||
124 | vcc33_sys: vcc33-sys { | |
125 | compatible = "regulator-fixed"; | |
126 | regulator-name = "vcc33_sys"; | |
127 | regulator-always-on; | |
128 | regulator-boot-on; | |
129 | regulator-min-microvolt = <3300000>; | |
130 | regulator-max-microvolt = <3300000>; | |
131 | }; | |
132 | ||
133 | vcc50_hdmi: vcc50-hdmi { | |
134 | compatible = "regulator-fixed"; | |
135 | regulator-name = "vcc50_hdmi"; | |
136 | regulator-always-on; | |
137 | regulator-boot-on; | |
138 | vin-supply = <&vcc_5v>; | |
139 | }; | |
140 | }; | |
141 | ||
142 | &cpu0 { | |
143 | cpu0-supply = <&vdd_cpu>; | |
144 | }; | |
145 | ||
146 | &emmc { | |
147 | status = "okay"; | |
148 | ||
149 | broken-cd; | |
150 | bus-width = <8>; | |
151 | cap-mmc-highspeed; | |
c41d31f7 | 152 | rockchip,default-sample-phase = <158>; |
e28ea9db | 153 | disable-wp; |
c41d31f7 | 154 | mmc-hs200-1_8v; |
e28ea9db AS |
155 | mmc-pwrseq = <&emmc_pwrseq>; |
156 | non-removable; | |
157 | num-slots = <1>; | |
158 | pinctrl-names = "default"; | |
159 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
160 | }; | |
161 | ||
162 | &hdmi { | |
a797451b | 163 | ddc-i2c-bus = <&i2c5>; |
e28ea9db AS |
164 | status = "okay"; |
165 | }; | |
166 | ||
167 | &i2c0 { | |
168 | status = "okay"; | |
169 | ||
170 | clock-frequency = <400000>; | |
171 | i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ | |
172 | i2c-scl-rising-time-ns = <100>; /* 45ns measured */ | |
173 | ||
174 | rk808: pmic@1b { | |
175 | compatible = "rockchip,rk808"; | |
176 | reg = <0x1b>; | |
177 | clock-output-names = "xin32k", "wifibt_32kin"; | |
178 | interrupt-parent = <&gpio0>; | |
179 | interrupts = <4 IRQ_TYPE_LEVEL_LOW>; | |
180 | pinctrl-names = "default"; | |
181 | pinctrl-0 = <&pmic_int_l>; | |
182 | rockchip,system-power-controller; | |
183 | wakeup-source; | |
184 | #clock-cells = <1>; | |
185 | ||
186 | vcc1-supply = <&vcc33_sys>; | |
187 | vcc2-supply = <&vcc33_sys>; | |
188 | vcc3-supply = <&vcc33_sys>; | |
189 | vcc4-supply = <&vcc33_sys>; | |
190 | vcc6-supply = <&vcc_5v>; | |
191 | vcc7-supply = <&vcc33_sys>; | |
192 | vcc8-supply = <&vcc33_sys>; | |
193 | vcc12-supply = <&vcc_18>; | |
194 | vddio-supply = <&vcc33_io>; | |
195 | ||
196 | regulators { | |
197 | vdd_cpu: DCDC_REG1 { | |
198 | regulator-name = "vdd_arm"; | |
199 | regulator-always-on; | |
200 | regulator-boot-on; | |
201 | regulator-min-microvolt = <750000>; | |
202 | regulator-max-microvolt = <1450000>; | |
203 | regulator-ramp-delay = <6001>; | |
204 | regulator-state-mem { | |
205 | regulator-off-in-suspend; | |
206 | }; | |
207 | }; | |
208 | ||
209 | vdd_gpu: DCDC_REG2 { | |
210 | regulator-name = "vdd_gpu"; | |
211 | regulator-always-on; | |
212 | regulator-boot-on; | |
213 | regulator-min-microvolt = <800000>; | |
214 | regulator-max-microvolt = <1250000>; | |
215 | regulator-ramp-delay = <6001>; | |
216 | regulator-state-mem { | |
217 | regulator-on-in-suspend; | |
218 | regulator-suspend-microvolt = <1000000>; | |
219 | }; | |
220 | }; | |
221 | ||
222 | vcc135_ddr: DCDC_REG3 { | |
223 | regulator-name = "vcc135_ddr"; | |
224 | regulator-always-on; | |
225 | regulator-boot-on; | |
226 | regulator-state-mem { | |
227 | regulator-on-in-suspend; | |
228 | }; | |
229 | }; | |
230 | ||
231 | /* | |
232 | * vcc_18 has several aliases. (vcc18_flashio and | |
233 | * vcc18_wl). We'll add those aliases here just to | |
234 | * make it easier to follow the schematic. The signals | |
235 | * are actually hooked together and only separated for | |
236 | * power measurement purposes). | |
237 | */ | |
238 | vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { | |
239 | regulator-name = "vcc_18"; | |
240 | regulator-always-on; | |
241 | regulator-boot-on; | |
242 | regulator-min-microvolt = <1800000>; | |
243 | regulator-max-microvolt = <1800000>; | |
244 | regulator-state-mem { | |
245 | regulator-on-in-suspend; | |
246 | regulator-suspend-microvolt = <1800000>; | |
247 | }; | |
248 | }; | |
249 | ||
250 | /* | |
251 | * Note that both vcc33_io and vcc33_pmuio are always | |
252 | * powered together. To simplify the logic in the dts | |
253 | * we just refer to vcc33_io every time something is | |
254 | * powered from vcc33_pmuio. In fact, on later boards | |
255 | * (such as danger) they're the same net. | |
256 | */ | |
257 | vcc33_io: LDO_REG1 { | |
258 | regulator-name = "vcc33_io"; | |
259 | regulator-always-on; | |
260 | regulator-boot-on; | |
261 | regulator-min-microvolt = <3300000>; | |
262 | regulator-max-microvolt = <3300000>; | |
263 | regulator-state-mem { | |
264 | regulator-on-in-suspend; | |
265 | regulator-suspend-microvolt = <3300000>; | |
266 | }; | |
267 | }; | |
268 | ||
269 | vdd_10: LDO_REG3 { | |
270 | regulator-name = "vdd_10"; | |
271 | regulator-always-on; | |
272 | regulator-boot-on; | |
273 | regulator-min-microvolt = <1000000>; | |
274 | regulator-max-microvolt = <1000000>; | |
275 | regulator-state-mem { | |
276 | regulator-on-in-suspend; | |
277 | regulator-suspend-microvolt = <1000000>; | |
278 | }; | |
279 | }; | |
280 | ||
281 | vdd10_lcd_pwren_h: LDO_REG7 { | |
282 | regulator-name = "vdd10_lcd_pwren_h"; | |
283 | regulator-always-on; | |
284 | regulator-boot-on; | |
285 | regulator-min-microvolt = <2500000>; | |
286 | regulator-max-microvolt = <2500000>; | |
287 | regulator-state-mem { | |
288 | regulator-off-in-suspend; | |
289 | }; | |
290 | }; | |
291 | ||
292 | vcc33_lcd: SWITCH_REG1 { | |
293 | regulator-name = "vcc33_lcd"; | |
294 | regulator-always-on; | |
295 | regulator-boot-on; | |
296 | regulator-state-mem { | |
297 | regulator-off-in-suspend; | |
298 | }; | |
299 | }; | |
300 | }; | |
301 | }; | |
302 | }; | |
303 | ||
304 | &i2c1 { | |
305 | status = "okay"; | |
306 | ||
307 | clock-frequency = <400000>; | |
308 | i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ | |
309 | i2c-scl-rising-time-ns = <100>; /* 40ns measured */ | |
310 | ||
311 | tpm: tpm@20 { | |
312 | compatible = "infineon,slb9645tt"; | |
313 | reg = <0x20>; | |
314 | powered-while-suspended; | |
315 | }; | |
316 | }; | |
317 | ||
318 | &i2c2 { | |
319 | status = "okay"; | |
320 | ||
321 | /* 100kHz since 4.7k resistors don't rise fast enough */ | |
322 | clock-frequency = <100000>; | |
323 | i2c-scl-falling-time-ns = <50>; /* 10ns measured */ | |
324 | i2c-scl-rising-time-ns = <800>; /* 600ns measured */ | |
325 | }; | |
326 | ||
327 | &i2c4 { | |
328 | status = "okay"; | |
329 | ||
330 | clock-frequency = <400000>; | |
331 | i2c-scl-falling-time-ns = <50>; /* 11ns measured */ | |
332 | i2c-scl-rising-time-ns = <300>; /* 225ns measured */ | |
333 | }; | |
334 | ||
335 | &i2c5 { | |
336 | status = "okay"; | |
337 | ||
338 | clock-frequency = <100000>; | |
339 | i2c-scl-falling-time-ns = <300>; | |
340 | i2c-scl-rising-time-ns = <1000>; | |
341 | }; | |
342 | ||
ba5810ab HS |
343 | &power { |
344 | assigned-clocks = <&cru SCLK_EDP_24M>; | |
345 | assigned-clock-parents = <&xin24m>; | |
346 | }; | |
347 | ||
e28ea9db AS |
348 | &pwm1 { |
349 | status = "okay"; | |
350 | }; | |
351 | ||
352 | &sdio0 { | |
353 | status = "okay"; | |
354 | ||
355 | broken-cd; | |
356 | bus-width = <4>; | |
357 | cap-sd-highspeed; | |
358 | cap-sdio-irq; | |
359 | keep-power-in-suspend; | |
360 | mmc-pwrseq = <&sdio_pwrseq>; | |
361 | non-removable; | |
362 | num-slots = <1>; | |
363 | pinctrl-names = "default"; | |
364 | pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; | |
c41d31f7 HS |
365 | sd-uhs-sdr12; |
366 | sd-uhs-sdr25; | |
367 | sd-uhs-sdr50; | |
368 | sd-uhs-sdr104; | |
e28ea9db AS |
369 | vmmc-supply = <&vcc33_sys>; |
370 | vqmmc-supply = <&vcc18_wl>; | |
371 | }; | |
372 | ||
373 | &spi2 { | |
374 | status = "okay"; | |
375 | ||
376 | rx-sample-delay-ns = <12>; | |
377 | }; | |
378 | ||
379 | &tsadc { | |
380 | status = "okay"; | |
381 | ||
117ccc11 RP |
382 | rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ |
383 | rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ | |
e28ea9db AS |
384 | }; |
385 | ||
386 | &uart0 { | |
387 | status = "okay"; | |
388 | ||
389 | /* We need to go faster than 24MHz, so adjust clock parents / rates */ | |
390 | assigned-clocks = <&cru SCLK_UART0>; | |
391 | assigned-clock-rates = <48000000>; | |
392 | ||
393 | /* Pins don't include flow control by default; add that in */ | |
394 | pinctrl-names = "default"; | |
395 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
396 | }; | |
397 | ||
398 | &uart1 { | |
399 | status = "okay"; | |
400 | }; | |
401 | ||
402 | &uart2 { | |
403 | status = "okay"; | |
404 | }; | |
405 | ||
406 | &usbphy { | |
407 | status = "okay"; | |
408 | }; | |
409 | ||
410 | &usb_host0_ehci { | |
411 | status = "okay"; | |
412 | ||
413 | needs-reset-on-resume; | |
414 | }; | |
415 | ||
416 | &usb_host1 { | |
417 | status = "okay"; | |
418 | }; | |
419 | ||
420 | &usb_otg { | |
421 | status = "okay"; | |
422 | ||
423 | assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; | |
424 | assigned-clock-parents = <&cru SCLK_OTGPHY0>; | |
425 | dr_mode = "host"; | |
426 | }; | |
427 | ||
428 | &vopb { | |
429 | status = "okay"; | |
430 | }; | |
431 | ||
432 | &vopb_mmu { | |
433 | status = "okay"; | |
434 | }; | |
435 | ||
436 | &wdt { | |
437 | status = "okay"; | |
438 | }; | |
439 | ||
440 | &pinctrl { | |
441 | pinctrl-names = "default", "sleep"; | |
442 | pinctrl-0 = < | |
443 | /* Common for sleep and wake, but no owners */ | |
444 | &global_pwroff | |
445 | >; | |
446 | pinctrl-1 = < | |
447 | /* Common for sleep and wake, but no owners */ | |
448 | &global_pwroff | |
449 | >; | |
450 | ||
451 | pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { | |
452 | bias-disable; | |
453 | drive-strength = <8>; | |
454 | }; | |
455 | ||
456 | pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { | |
457 | bias-pull-up; | |
458 | drive-strength = <8>; | |
459 | }; | |
460 | ||
461 | pcfg_output_high: pcfg-output-high { | |
462 | output-high; | |
463 | }; | |
464 | ||
465 | pcfg_output_low: pcfg-output-low { | |
466 | output-low; | |
467 | }; | |
468 | ||
469 | buttons { | |
470 | pwr_key_l: pwr-key-l { | |
471 | rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; | |
472 | }; | |
473 | }; | |
474 | ||
475 | emmc { | |
476 | emmc_reset: emmc-reset { | |
477 | rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; | |
478 | }; | |
479 | ||
480 | /* | |
481 | * We run eMMC at max speed; bump up drive strength. | |
482 | * We also have external pulls, so disable the internal ones. | |
483 | */ | |
484 | emmc_clk: emmc-clk { | |
485 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; | |
486 | }; | |
487 | ||
488 | emmc_cmd: emmc-cmd { | |
489 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; | |
490 | }; | |
491 | ||
492 | emmc_bus8: emmc-bus8 { | |
493 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
494 | <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
495 | <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
496 | <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
497 | <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
498 | <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
499 | <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
500 | <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; | |
501 | }; | |
502 | }; | |
503 | ||
504 | pmic { | |
505 | pmic_int_l: pmic-int-l { | |
506 | rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; | |
507 | }; | |
508 | }; | |
509 | ||
510 | reboot { | |
511 | ap_warm_reset_h: ap-warm-reset-h { | |
512 | rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; | |
513 | }; | |
514 | }; | |
515 | ||
516 | recovery-switch { | |
517 | rec_mode_l: rec-mode-l { | |
518 | rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; | |
519 | }; | |
520 | }; | |
521 | ||
522 | sdio0 { | |
523 | wifi_enable_h: wifienable-h { | |
524 | rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; | |
525 | }; | |
526 | ||
527 | /* NOTE: mislabelled on schematic; should be bt_enable_h */ | |
528 | bt_enable_l: bt-enable-l { | |
529 | rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; | |
530 | }; | |
531 | ||
532 | /* | |
533 | * We run sdio0 at max speed; bump up drive strength. | |
534 | * We also have external pulls, so disable the internal ones. | |
535 | */ | |
536 | sdio0_bus4: sdio0-bus4 { | |
537 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, | |
538 | <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, | |
539 | <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, | |
540 | <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; | |
541 | }; | |
542 | ||
543 | sdio0_cmd: sdio0-cmd { | |
544 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; | |
545 | }; | |
546 | ||
547 | sdio0_clk: sdio0-clk { | |
548 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; | |
549 | }; | |
550 | }; | |
551 | ||
552 | tpm { | |
553 | tpm_int_h: tpm-int-h { | |
554 | rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; | |
555 | }; | |
556 | }; | |
557 | ||
e28ea9db AS |
558 | write-protect { |
559 | fw_wp_ap: fw-wp-ap { | |
560 | rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; | |
561 | }; | |
562 | }; | |
563 | }; |