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ARM: dts: rockchip: add core rk3288 dtsi
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
18#include "skeleton.dtsi"
19
20/ {
21 compatible = "rockchip,rk3288";
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@500 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a12";
46 reg = <0x500>;
47 };
48 cpu@501 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a12";
51 reg = <0x501>;
52 };
53 cpu@502 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x502>;
57 };
58 cpu@503 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x503>;
62 };
63 };
64
65 xin24m: oscillator {
66 compatible = "fixed-clock";
67 clock-frequency = <24000000>;
68 clock-output-names = "xin24m";
69 #clock-cells = <0>;
70 };
71
72 timer {
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
78 clock-frequency = <24000000>;
79 };
80
81 i2c1: i2c@ff140000 {
82 compatible = "rockchip,rk3288-i2c";
83 reg = <0xff140000 0x1000>;
84 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 clock-names = "i2c";
88 clocks = <&cru PCLK_I2C1>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&i2c1_xfer>;
91 status = "disabled";
92 };
93
94 i2c3: i2c@ff150000 {
95 compatible = "rockchip,rk3288-i2c";
96 reg = <0xff150000 0x1000>;
97 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 clock-names = "i2c";
101 clocks = <&cru PCLK_I2C3>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2c3_xfer>;
104 status = "disabled";
105 };
106
107 i2c4: i2c@ff160000 {
108 compatible = "rockchip,rk3288-i2c";
109 reg = <0xff160000 0x1000>;
110 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 clock-names = "i2c";
114 clocks = <&cru PCLK_I2C4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c4_xfer>;
117 status = "disabled";
118 };
119
120 i2c5: i2c@ff170000 {
121 compatible = "rockchip,rk3288-i2c";
122 reg = <0xff170000 0x1000>;
123 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 clock-names = "i2c";
127 clocks = <&cru PCLK_I2C5>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&i2c5_xfer>;
130 status = "disabled";
131 };
132
133 uart0: serial@ff180000 {
134 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
135 reg = <0xff180000 0x100>;
136 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
139 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
140 clock-names = "baudclk", "apb_pclk";
141 pinctrl-names = "default";
142 pinctrl-0 = <&uart0_xfer>;
143 status = "disabled";
144 };
145
146 uart1: serial@ff190000 {
147 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
148 reg = <0xff190000 0x100>;
149 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
150 reg-shift = <2>;
151 reg-io-width = <4>;
152 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
153 clock-names = "baudclk", "apb_pclk";
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart1_xfer>;
156 status = "disabled";
157 };
158
159 uart2: serial@ff690000 {
160 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
161 reg = <0xff690000 0x100>;
162 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
163 reg-shift = <2>;
164 reg-io-width = <4>;
165 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
166 clock-names = "baudclk", "apb_pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&uart2_xfer>;
169 status = "disabled";
170 };
171
172 uart3: serial@ff1b0000 {
173 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
174 reg = <0xff1b0000 0x100>;
175 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
176 reg-shift = <2>;
177 reg-io-width = <4>;
178 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
179 clock-names = "baudclk", "apb_pclk";
180 pinctrl-names = "default";
181 pinctrl-0 = <&uart3_xfer>;
182 status = "disabled";
183 };
184
185 uart4: serial@ff1c0000 {
186 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
187 reg = <0xff1c0000 0x100>;
188 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
189 reg-shift = <2>;
190 reg-io-width = <4>;
191 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
192 clock-names = "baudclk", "apb_pclk";
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart4_xfer>;
195 status = "disabled";
196 };
197
198 i2c0: i2c@ff650000 {
199 compatible = "rockchip,rk3288-i2c";
200 reg = <0xff650000 0x1000>;
201 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 clock-names = "i2c";
205 clocks = <&cru PCLK_I2C0>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&i2c0_xfer>;
208 status = "disabled";
209 };
210
211 i2c2: i2c@ff660000 {
212 compatible = "rockchip,rk3288-i2c";
213 reg = <0xff660000 0x1000>;
214 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 clock-names = "i2c";
218 clocks = <&cru PCLK_I2C2>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c2_xfer>;
221 status = "disabled";
222 };
223
224 pmu: power-management@ff730000 {
225 compatible = "rockchip,rk3288-pmu", "syscon";
226 reg = <0xff730000 0x100>;
227 };
228
229 sgrf: syscon@ff740000 {
230 compatible = "rockchip,rk3288-sgrf", "syscon";
231 reg = <0xff740000 0x1000>;
232 };
233
234 cru: clock-controller@ff760000 {
235 compatible = "rockchip,rk3288-cru";
236 reg = <0xff760000 0x1000>;
237 rockchip,grf = <&grf>;
238 #clock-cells = <1>;
239 #reset-cells = <1>;
240 };
241
242 grf: syscon@ff770000 {
243 compatible = "rockchip,rk3288-grf", "syscon";
244 reg = <0xff770000 0x1000>;
245 };
246
247 wdt: watchdog@ff800000 {
248 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
249 reg = <0xff800000 0x100>;
250 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
253
254 gic: interrupt-controller@ffc01000 {
255 compatible = "arm,gic-400";
256 interrupt-controller;
257 #interrupt-cells = <3>;
258 #address-cells = <0>;
259
260 reg = <0xffc01000 0x1000>,
261 <0xffc02000 0x1000>,
262 <0xffc04000 0x2000>,
263 <0xffc06000 0x2000>;
264 interrupts = <GIC_PPI 9 0xf04>;
265 };
266
267 pinctrl: pinctrl {
268 compatible = "rockchip,rk3288-pinctrl";
269 rockchip,grf = <&grf>;
270 rockchip,pmu = <&pmu>;
271 #address-cells = <1>;
272 #size-cells = <1>;
273 ranges;
274
275 gpio0: gpio0@ff750000 {
276 compatible = "rockchip,gpio-bank";
277 reg = <0xff750000 0x100>;
278 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cru PCLK_GPIO0>;
280
281 gpio-controller;
282 #gpio-cells = <2>;
283
284 interrupt-controller;
285 #interrupt-cells = <2>;
286 };
287
288 gpio1: gpio1@ff780000 {
289 compatible = "rockchip,gpio-bank";
290 reg = <0xff780000 0x100>;
291 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_GPIO1>;
293
294 gpio-controller;
295 #gpio-cells = <2>;
296
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 gpio2: gpio2@ff790000 {
302 compatible = "rockchip,gpio-bank";
303 reg = <0xff790000 0x100>;
304 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru PCLK_GPIO2>;
306
307 gpio-controller;
308 #gpio-cells = <2>;
309
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 gpio3: gpio3@ff7a0000 {
315 compatible = "rockchip,gpio-bank";
316 reg = <0xff7a0000 0x100>;
317 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru PCLK_GPIO3>;
319
320 gpio-controller;
321 #gpio-cells = <2>;
322
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 };
326
327 gpio4: gpio4@ff7b0000 {
328 compatible = "rockchip,gpio-bank";
329 reg = <0xff7b0000 0x100>;
330 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cru PCLK_GPIO4>;
332
333 gpio-controller;
334 #gpio-cells = <2>;
335
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 gpio5: gpio5@ff7c0000 {
341 compatible = "rockchip,gpio-bank";
342 reg = <0xff7c0000 0x100>;
343 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&cru PCLK_GPIO5>;
345
346 gpio-controller;
347 #gpio-cells = <2>;
348
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 };
352
353 gpio6: gpio6@ff7d0000 {
354 compatible = "rockchip,gpio-bank";
355 reg = <0xff7d0000 0x100>;
356 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&cru PCLK_GPIO6>;
358
359 gpio-controller;
360 #gpio-cells = <2>;
361
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio7: gpio7@ff7e0000 {
367 compatible = "rockchip,gpio-bank";
368 reg = <0xff7e0000 0x100>;
369 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cru PCLK_GPIO7>;
371
372 gpio-controller;
373 #gpio-cells = <2>;
374
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 };
378
379 gpio8: gpio8@ff7f0000 {
380 compatible = "rockchip,gpio-bank";
381 reg = <0xff7f0000 0x100>;
382 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cru PCLK_GPIO8>;
384
385 gpio-controller;
386 #gpio-cells = <2>;
387
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 };
391
392 pcfg_pull_up: pcfg-pull-up {
393 bias-pull-up;
394 };
395
396 pcfg_pull_down: pcfg-pull-down {
397 bias-pull-down;
398 };
399
400 pcfg_pull_none: pcfg-pull-none {
401 bias-disable;
402 };
403
404 i2c0 {
405 i2c0_xfer: i2c0-xfer {
406 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
407 <0 16 RK_FUNC_1 &pcfg_pull_none>;
408 };
409 };
410
411 i2c1 {
412 i2c1_xfer: i2c1-xfer {
413 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
414 <8 5 RK_FUNC_1 &pcfg_pull_none>;
415 };
416 };
417
418 i2c2 {
419 i2c2_xfer: i2c2-xfer {
420 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
421 <6 10 RK_FUNC_1 &pcfg_pull_none>;
422 };
423 };
424
425 i2c3 {
426 i2c3_xfer: i2c3-xfer {
427 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
428 <2 17 RK_FUNC_1 &pcfg_pull_none>;
429 };
430 };
431
432 i2c4 {
433 i2c4_xfer: i2c4-xfer {
434 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
435 <7 18 RK_FUNC_1 &pcfg_pull_none>;
436 };
437 };
438
439 i2c5 {
440 i2c5_xfer: i2c5-xfer {
441 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
442 <7 20 RK_FUNC_1 &pcfg_pull_none>;
443 };
444 };
445
446 sdmmc {
447 sdmmc_clk: sdmmc-clk {
448 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
449 };
450
451 sdmmc_cmd: sdmmc-cmd {
452 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
453 };
454
455 sdmmc_cd: sdmcc-cd {
456 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
457 };
458
459 sdmmc_bus1: sdmmc-bus1 {
460 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
461 };
462
463 sdmmc_bus4: sdmmc-bus4 {
464 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
465 <6 17 RK_FUNC_1 &pcfg_pull_up>,
466 <6 18 RK_FUNC_1 &pcfg_pull_up>,
467 <6 19 RK_FUNC_1 &pcfg_pull_up>;
468 };
469 };
470
471 emmc {
472 emmc_clk: emmc-clk {
473 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
474 };
475
476 emmc_cmd: emmc-cmd {
477 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
478 };
479
480 emmc_pwr: emmc-pwr {
481 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
482 };
483
484 emmc_bus1: emmc-bus1 {
485 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
486 };
487
488 emmc_bus4: emmc-bus4 {
489 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
490 <3 1 RK_FUNC_2 &pcfg_pull_up>,
491 <3 2 RK_FUNC_2 &pcfg_pull_up>,
492 <3 3 RK_FUNC_2 &pcfg_pull_up>;
493 };
494
495 emmc_bus8: emmc-bus8 {
496 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
497 <3 1 RK_FUNC_2 &pcfg_pull_up>,
498 <3 2 RK_FUNC_2 &pcfg_pull_up>,
499 <3 3 RK_FUNC_2 &pcfg_pull_up>,
500 <3 4 RK_FUNC_2 &pcfg_pull_up>,
501 <3 5 RK_FUNC_2 &pcfg_pull_up>,
502 <3 6 RK_FUNC_2 &pcfg_pull_up>,
503 <3 7 RK_FUNC_2 &pcfg_pull_up>;
504 };
505 };
506
507 uart0 {
508 uart0_xfer: uart0-xfer {
509 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
510 <4 17 RK_FUNC_1 &pcfg_pull_none>;
511 };
512
513 uart0_cts: uart0-cts {
514 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
515 };
516
517 uart0_rts: uart0-rts {
518 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
519 };
520 };
521
522 uart1 {
523 uart1_xfer: uart1-xfer {
524 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
525 <5 9 RK_FUNC_1 &pcfg_pull_none>;
526 };
527
528 uart1_cts: uart1-cts {
529 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
530 };
531
532 uart1_rts: uart1-rts {
533 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
534 };
535 };
536
537 uart2 {
538 uart2_xfer: uart2-xfer {
539 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
540 <7 23 RK_FUNC_1 &pcfg_pull_none>;
541 };
542 /* no rts / cts for uart2 */
543 };
544
545 uart3 {
546 uart3_xfer: uart3-xfer {
547 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
548 <7 8 RK_FUNC_1 &pcfg_pull_none>;
549 };
550
551 uart3_cts: uart3-cts {
552 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
553 };
554
555 uart3_rts: uart3-rts {
556 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
557 };
558 };
559
560 uart4 {
561 uart4_xfer: uart4-xfer {
562 rockchip,pins = <5 12 3 &pcfg_pull_up>,
563 <5 13 3 &pcfg_pull_none>;
564 };
565
566 uart4_cts: uart4-cts {
567 rockchip,pins = <5 14 3 &pcfg_pull_none>;
568 };
569
570 uart4_rts: uart4-rts {
571 rockchip,pins = <5 15 3 &pcfg_pull_none>;
572 };
573 };
574 };
575};
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