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2ab557b7 | 1 | /* |
b1772506 HS |
2 | * This file is dual-licensed: you can use it either under the terms |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
2ab557b7 | 6 | * |
b1772506 HS |
7 | * a) This file is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
2ab557b7 HS |
39 | */ |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3288-cru.h> | |
b67d6bc3 | 46 | #include <dt-bindings/thermal/thermal.h> |
b63af764 | 47 | #include <dt-bindings/power/rk3288-power.h> |
2ab557b7 HS |
48 | #include "skeleton.dtsi" |
49 | ||
50 | / { | |
51 | compatible = "rockchip,rk3288"; | |
52 | ||
53 | interrupt-parent = <&gic>; | |
54 | ||
55 | aliases { | |
85ef8d61 | 56 | ethernet0 = &gmac; |
2ab557b7 HS |
57 | i2c0 = &i2c0; |
58 | i2c1 = &i2c1; | |
59 | i2c2 = &i2c2; | |
60 | i2c3 = &i2c3; | |
61 | i2c4 = &i2c4; | |
62 | i2c5 = &i2c5; | |
d7f9a388 DA |
63 | mshc0 = &emmc; |
64 | mshc1 = &sdmmc; | |
65 | mshc2 = &sdio0; | |
66 | mshc3 = &sdio1; | |
2ab557b7 HS |
67 | serial0 = &uart0; |
68 | serial1 = &uart1; | |
69 | serial2 = &uart2; | |
70 | serial3 = &uart3; | |
71 | serial4 = &uart4; | |
1f53170b | 72 | spi0 = &spi0; |
73 | spi1 = &spi1; | |
74 | spi2 = &spi2; | |
2ab557b7 HS |
75 | }; |
76 | ||
f1840780 SR |
77 | arm-pmu { |
78 | compatible = "arm,cortex-a12-pmu"; | |
79 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, | |
80 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, | |
81 | <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
82 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
4863dcd3 | 83 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
f1840780 SR |
84 | }; |
85 | ||
2ab557b7 HS |
86 | cpus { |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
08bcc754 | 89 | enable-method = "rockchip,rk3066-smp"; |
fbdbc732 | 90 | rockchip,pmu = <&pmu>; |
2ab557b7 | 91 | |
be8a77c5 | 92 | cpu0: cpu@500 { |
2ab557b7 HS |
93 | device_type = "cpu"; |
94 | compatible = "arm,cortex-a12"; | |
95 | reg = <0x500>; | |
044542af | 96 | resets = <&cru SRST_CORE0>; |
be8a77c5 HS |
97 | operating-points = < |
98 | /* KHz uV */ | |
99 | 1608000 1350000 | |
100 | 1512000 1300000 | |
101 | 1416000 1200000 | |
102 | 1200000 1100000 | |
103 | 1008000 1050000 | |
104 | 816000 1000000 | |
105 | 696000 950000 | |
106 | 600000 900000 | |
107 | 408000 900000 | |
108 | 312000 900000 | |
109 | 216000 900000 | |
110 | 126000 900000 | |
111 | >; | |
b67d6bc3 | 112 | #cooling-cells = <2>; /* min followed by max */ |
be8a77c5 HS |
113 | clock-latency = <40000>; |
114 | clocks = <&cru ARMCLK>; | |
2ab557b7 | 115 | }; |
4863dcd3 | 116 | cpu1: cpu@501 { |
2ab557b7 HS |
117 | device_type = "cpu"; |
118 | compatible = "arm,cortex-a12"; | |
119 | reg = <0x501>; | |
044542af | 120 | resets = <&cru SRST_CORE1>; |
2ab557b7 | 121 | }; |
4863dcd3 | 122 | cpu2: cpu@502 { |
2ab557b7 HS |
123 | device_type = "cpu"; |
124 | compatible = "arm,cortex-a12"; | |
125 | reg = <0x502>; | |
044542af | 126 | resets = <&cru SRST_CORE2>; |
2ab557b7 | 127 | }; |
4863dcd3 | 128 | cpu3: cpu@503 { |
2ab557b7 HS |
129 | device_type = "cpu"; |
130 | compatible = "arm,cortex-a12"; | |
131 | reg = <0x503>; | |
044542af | 132 | resets = <&cru SRST_CORE3>; |
2ab557b7 HS |
133 | }; |
134 | }; | |
135 | ||
982891c3 | 136 | amba { |
2ef7d5f3 | 137 | compatible = "simple-bus"; |
982891c3 HS |
138 | #address-cells = <1>; |
139 | #size-cells = <1>; | |
140 | ranges; | |
141 | ||
142 | dmac_peri: dma-controller@ff250000 { | |
143 | compatible = "arm,pl330", "arm,primecell"; | |
144 | reg = <0xff250000 0x4000>; | |
145 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
146 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
147 | #dma-cells = <1>; | |
e7d6c9b1 | 148 | arm,pl330-broken-no-flushp; |
982891c3 HS |
149 | clocks = <&cru ACLK_DMAC2>; |
150 | clock-names = "apb_pclk"; | |
151 | }; | |
152 | ||
153 | dmac_bus_ns: dma-controller@ff600000 { | |
154 | compatible = "arm,pl330", "arm,primecell"; | |
155 | reg = <0xff600000 0x4000>; | |
156 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
157 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
158 | #dma-cells = <1>; | |
e7d6c9b1 | 159 | arm,pl330-broken-no-flushp; |
982891c3 HS |
160 | clocks = <&cru ACLK_DMAC1>; |
161 | clock-names = "apb_pclk"; | |
162 | status = "disabled"; | |
163 | }; | |
164 | ||
165 | dmac_bus_s: dma-controller@ffb20000 { | |
166 | compatible = "arm,pl330", "arm,primecell"; | |
167 | reg = <0xffb20000 0x4000>; | |
168 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
169 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
170 | #dma-cells = <1>; | |
e7d6c9b1 | 171 | arm,pl330-broken-no-flushp; |
982891c3 HS |
172 | clocks = <&cru ACLK_DMAC1>; |
173 | clock-names = "apb_pclk"; | |
174 | }; | |
175 | }; | |
176 | ||
b21bcfc9 HS |
177 | reserved-memory { |
178 | #address-cells = <1>; | |
179 | #size-cells = <1>; | |
180 | ranges; | |
181 | ||
182 | /* | |
183 | * The rk3288 cannot use the memory area above 0xfe000000 | |
184 | * for dma operations for some reason. While there is | |
185 | * probably a better solution available somewhere, we | |
186 | * haven't found it yet and while devices with 2GB of ram | |
187 | * are not affected, this issue prevents 4GB from booting. | |
188 | * So to make these devices at least bootable, block | |
189 | * this area for the time being until the real solution | |
190 | * is found. | |
191 | */ | |
192 | dma-unusable@fe000000 { | |
193 | reg = <0xfe000000 0x1000000>; | |
194 | }; | |
195 | }; | |
196 | ||
2ab557b7 HS |
197 | xin24m: oscillator { |
198 | compatible = "fixed-clock"; | |
199 | clock-frequency = <24000000>; | |
200 | clock-output-names = "xin24m"; | |
201 | #clock-cells = <0>; | |
202 | }; | |
203 | ||
f5663969 HS |
204 | edp_phy: edp-phy { |
205 | compatible = "rockchip,rk3288-dp-phy"; | |
206 | clocks = <&cru SCLK_EDP_24M>; | |
207 | clock-names = "24m"; | |
208 | rockchip,grf = <&grf>; | |
209 | #phy-cells = <0>; | |
210 | status = "disabled"; | |
211 | }; | |
212 | ||
2ab557b7 HS |
213 | timer { |
214 | compatible = "arm,armv7-timer"; | |
e2405a59 | 215 | arm,cpu-registers-not-fw-configured; |
2ab557b7 HS |
216 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
217 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
218 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
219 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
220 | clock-frequency = <24000000>; | |
221 | }; | |
222 | ||
e48cc181 DL |
223 | timer: timer@ff810000 { |
224 | compatible = "rockchip,rk3288-timer"; | |
225 | reg = <0xff810000 0x20>; | |
226 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
227 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
228 | clock-names = "timer", "pclk"; | |
229 | }; | |
230 | ||
a29cb8c4 DK |
231 | display-subsystem { |
232 | compatible = "rockchip,display-subsystem"; | |
233 | ports = <&vopl_out>, <&vopb_out>; | |
234 | }; | |
235 | ||
85095bf3 DA |
236 | sdmmc: dwmmc@ff0c0000 { |
237 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 238 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
239 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, |
240 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
241 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
242 | fifo-depth = <0x100>; |
243 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
244 | reg = <0xff0c0000 0x4000>; | |
245 | status = "disabled"; | |
246 | }; | |
247 | ||
f1a07231 AK |
248 | sdio0: dwmmc@ff0d0000 { |
249 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 250 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
251 | clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, |
252 | <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; | |
253 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
254 | fifo-depth = <0x100>; |
255 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
256 | reg = <0xff0d0000 0x4000>; | |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
260 | sdio1: dwmmc@ff0e0000 { | |
261 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 262 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
263 | clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, |
264 | <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; | |
265 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
266 | fifo-depth = <0x100>; |
267 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
268 | reg = <0xff0e0000 0x4000>; | |
269 | status = "disabled"; | |
270 | }; | |
271 | ||
85095bf3 DA |
272 | emmc: dwmmc@ff0f0000 { |
273 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 274 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
275 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
276 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
277 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
278 | fifo-depth = <0x100>; |
279 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
280 | reg = <0xff0f0000 0x4000>; | |
281 | status = "disabled"; | |
282 | }; | |
283 | ||
f23a6179 HS |
284 | saradc: saradc@ff100000 { |
285 | compatible = "rockchip,saradc"; | |
286 | reg = <0xff100000 0x100>; | |
287 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
288 | #io-channel-cells = <1>; | |
289 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
290 | clock-names = "saradc", "apb_pclk"; | |
291 | status = "disabled"; | |
292 | }; | |
293 | ||
1f53170b | 294 | spi0: spi@ff110000 { |
295 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
296 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
297 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
298 | dmas = <&dmac_peri 11>, <&dmac_peri 12>; |
299 | dma-names = "tx", "rx"; | |
1f53170b | 300 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
301 | pinctrl-names = "default"; | |
302 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
303 | reg = <0xff110000 0x1000>; | |
304 | #address-cells = <1>; | |
305 | #size-cells = <0>; | |
306 | status = "disabled"; | |
307 | }; | |
308 | ||
309 | spi1: spi@ff120000 { | |
310 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
311 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
312 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
313 | dmas = <&dmac_peri 13>, <&dmac_peri 14>; |
314 | dma-names = "tx", "rx"; | |
1f53170b | 315 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
316 | pinctrl-names = "default"; | |
317 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
318 | reg = <0xff120000 0x1000>; | |
319 | #address-cells = <1>; | |
320 | #size-cells = <0>; | |
321 | status = "disabled"; | |
322 | }; | |
323 | ||
324 | spi2: spi@ff130000 { | |
325 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
326 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
327 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
328 | dmas = <&dmac_peri 15>, <&dmac_peri 16>; |
329 | dma-names = "tx", "rx"; | |
1f53170b | 330 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
331 | pinctrl-names = "default"; | |
332 | pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; | |
333 | reg = <0xff130000 0x1000>; | |
334 | #address-cells = <1>; | |
335 | #size-cells = <0>; | |
336 | status = "disabled"; | |
337 | }; | |
338 | ||
2ab557b7 HS |
339 | i2c1: i2c@ff140000 { |
340 | compatible = "rockchip,rk3288-i2c"; | |
341 | reg = <0xff140000 0x1000>; | |
342 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
343 | #address-cells = <1>; | |
344 | #size-cells = <0>; | |
345 | clock-names = "i2c"; | |
346 | clocks = <&cru PCLK_I2C1>; | |
347 | pinctrl-names = "default"; | |
348 | pinctrl-0 = <&i2c1_xfer>; | |
349 | status = "disabled"; | |
350 | }; | |
351 | ||
352 | i2c3: i2c@ff150000 { | |
353 | compatible = "rockchip,rk3288-i2c"; | |
354 | reg = <0xff150000 0x1000>; | |
355 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
356 | #address-cells = <1>; | |
357 | #size-cells = <0>; | |
358 | clock-names = "i2c"; | |
359 | clocks = <&cru PCLK_I2C3>; | |
360 | pinctrl-names = "default"; | |
361 | pinctrl-0 = <&i2c3_xfer>; | |
362 | status = "disabled"; | |
363 | }; | |
364 | ||
365 | i2c4: i2c@ff160000 { | |
366 | compatible = "rockchip,rk3288-i2c"; | |
367 | reg = <0xff160000 0x1000>; | |
368 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | clock-names = "i2c"; | |
372 | clocks = <&cru PCLK_I2C4>; | |
373 | pinctrl-names = "default"; | |
374 | pinctrl-0 = <&i2c4_xfer>; | |
375 | status = "disabled"; | |
376 | }; | |
377 | ||
378 | i2c5: i2c@ff170000 { | |
379 | compatible = "rockchip,rk3288-i2c"; | |
380 | reg = <0xff170000 0x1000>; | |
381 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
382 | #address-cells = <1>; | |
383 | #size-cells = <0>; | |
384 | clock-names = "i2c"; | |
385 | clocks = <&cru PCLK_I2C5>; | |
386 | pinctrl-names = "default"; | |
387 | pinctrl-0 = <&i2c5_xfer>; | |
388 | status = "disabled"; | |
389 | }; | |
390 | ||
391 | uart0: serial@ff180000 { | |
392 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
393 | reg = <0xff180000 0x100>; | |
394 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
395 | reg-shift = <2>; | |
396 | reg-io-width = <4>; | |
397 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
398 | clock-names = "baudclk", "apb_pclk"; | |
399 | pinctrl-names = "default"; | |
400 | pinctrl-0 = <&uart0_xfer>; | |
401 | status = "disabled"; | |
402 | }; | |
403 | ||
404 | uart1: serial@ff190000 { | |
405 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
406 | reg = <0xff190000 0x100>; | |
407 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
408 | reg-shift = <2>; | |
409 | reg-io-width = <4>; | |
410 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
411 | clock-names = "baudclk", "apb_pclk"; | |
412 | pinctrl-names = "default"; | |
413 | pinctrl-0 = <&uart1_xfer>; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | uart2: serial@ff690000 { | |
418 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
419 | reg = <0xff690000 0x100>; | |
420 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
421 | reg-shift = <2>; | |
422 | reg-io-width = <4>; | |
423 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
424 | clock-names = "baudclk", "apb_pclk"; | |
425 | pinctrl-names = "default"; | |
426 | pinctrl-0 = <&uart2_xfer>; | |
427 | status = "disabled"; | |
428 | }; | |
429 | ||
430 | uart3: serial@ff1b0000 { | |
431 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
432 | reg = <0xff1b0000 0x100>; | |
433 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
434 | reg-shift = <2>; | |
435 | reg-io-width = <4>; | |
436 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
437 | clock-names = "baudclk", "apb_pclk"; | |
438 | pinctrl-names = "default"; | |
439 | pinctrl-0 = <&uart3_xfer>; | |
440 | status = "disabled"; | |
441 | }; | |
442 | ||
443 | uart4: serial@ff1c0000 { | |
444 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
445 | reg = <0xff1c0000 0x100>; | |
446 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
447 | reg-shift = <2>; | |
448 | reg-io-width = <4>; | |
449 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; | |
450 | clock-names = "baudclk", "apb_pclk"; | |
451 | pinctrl-names = "default"; | |
452 | pinctrl-0 = <&uart4_xfer>; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
b67d6bc3 CW |
456 | thermal-zones { |
457 | #include "rk3288-thermal.dtsi" | |
458 | }; | |
459 | ||
460 | tsadc: tsadc@ff280000 { | |
461 | compatible = "rockchip,rk3288-tsadc"; | |
462 | reg = <0xff280000 0x100>; | |
463 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
464 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
465 | clock-names = "tsadc", "apb_pclk"; | |
466 | resets = <&cru SRST_TSADC>; | |
467 | reset-names = "tsadc-apb"; | |
784359b8 CW |
468 | pinctrl-names = "init", "default", "sleep"; |
469 | pinctrl-0 = <&otp_gpio>; | |
470 | pinctrl-1 = <&otp_out>; | |
471 | pinctrl-2 = <&otp_gpio>; | |
b67d6bc3 CW |
472 | #thermal-sensor-cells = <1>; |
473 | rockchip,hw-tshut-temp = <95000>; | |
474 | status = "disabled"; | |
475 | }; | |
476 | ||
3d3fb74a RC |
477 | gmac: ethernet@ff290000 { |
478 | compatible = "rockchip,rk3288-gmac"; | |
479 | reg = <0xff290000 0x10000>; | |
480 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
481 | interrupt-names = "macirq"; | |
482 | rockchip,grf = <&grf>; | |
483 | clocks = <&cru SCLK_MAC>, | |
484 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, | |
485 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, | |
486 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; | |
487 | clock-names = "stmmaceth", | |
488 | "mac_clk_rx", "mac_clk_tx", | |
489 | "clk_mac_ref", "clk_mac_refout", | |
490 | "aclk_mac", "pclk_mac"; | |
e6b54649 RP |
491 | resets = <&cru SRST_MAC>; |
492 | reset-names = "stmmaceth"; | |
54b0bc60 | 493 | status = "disabled"; |
3d3fb74a RC |
494 | }; |
495 | ||
c9c32c50 DA |
496 | usb_host0_ehci: usb@ff500000 { |
497 | compatible = "generic-ehci"; | |
498 | reg = <0xff500000 0x100>; | |
499 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
500 | clocks = <&cru HCLK_USBHOST0>; | |
501 | clock-names = "usbhost"; | |
f6db7029 YL |
502 | phys = <&usbphy1>; |
503 | phy-names = "usb"; | |
c9c32c50 DA |
504 | status = "disabled"; |
505 | }; | |
506 | ||
507 | /* NOTE: ohci@ff520000 doesn't actually work on hardware */ | |
508 | ||
12dd3653 KY |
509 | usb_host1: usb@ff540000 { |
510 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
511 | "snps,dwc2"; | |
512 | reg = <0xff540000 0x40000>; | |
513 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
514 | clocks = <&cru HCLK_USBHOST1>; | |
515 | clock-names = "otg"; | |
cabd2ea2 | 516 | dr_mode = "host"; |
f6db7029 YL |
517 | phys = <&usbphy2>; |
518 | phy-names = "usb2-phy"; | |
12dd3653 KY |
519 | status = "disabled"; |
520 | }; | |
521 | ||
522 | usb_otg: usb@ff580000 { | |
523 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
524 | "snps,dwc2"; | |
525 | reg = <0xff580000 0x40000>; | |
526 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
527 | clocks = <&cru HCLK_OTG0>; | |
528 | clock-names = "otg"; | |
cabd2ea2 YL |
529 | dr_mode = "otg"; |
530 | g-np-tx-fifo-size = <16>; | |
531 | g-rx-fifo-size = <275>; | |
532 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
533 | g-use-dma; | |
f6db7029 YL |
534 | phys = <&usbphy0>; |
535 | phy-names = "usb2-phy"; | |
12dd3653 KY |
536 | status = "disabled"; |
537 | }; | |
538 | ||
c9c32c50 DA |
539 | usb_hsic: usb@ff5c0000 { |
540 | compatible = "generic-ehci"; | |
541 | reg = <0xff5c0000 0x100>; | |
542 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
543 | clocks = <&cru HCLK_HSIC>; | |
544 | clock-names = "usbhost"; | |
545 | status = "disabled"; | |
546 | }; | |
547 | ||
2ab557b7 HS |
548 | i2c0: i2c@ff650000 { |
549 | compatible = "rockchip,rk3288-i2c"; | |
550 | reg = <0xff650000 0x1000>; | |
551 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
552 | #address-cells = <1>; | |
553 | #size-cells = <0>; | |
554 | clock-names = "i2c"; | |
555 | clocks = <&cru PCLK_I2C0>; | |
556 | pinctrl-names = "default"; | |
557 | pinctrl-0 = <&i2c0_xfer>; | |
558 | status = "disabled"; | |
559 | }; | |
560 | ||
561 | i2c2: i2c@ff660000 { | |
562 | compatible = "rockchip,rk3288-i2c"; | |
563 | reg = <0xff660000 0x1000>; | |
564 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
565 | #address-cells = <1>; | |
566 | #size-cells = <0>; | |
567 | clock-names = "i2c"; | |
568 | clocks = <&cru PCLK_I2C2>; | |
569 | pinctrl-names = "default"; | |
570 | pinctrl-0 = <&i2c2_xfer>; | |
571 | status = "disabled"; | |
572 | }; | |
573 | ||
df542df3 DA |
574 | pwm0: pwm@ff680000 { |
575 | compatible = "rockchip,rk3288-pwm"; | |
576 | reg = <0xff680000 0x10>; | |
577 | #pwm-cells = <3>; | |
578 | pinctrl-names = "default"; | |
579 | pinctrl-0 = <&pwm0_pin>; | |
580 | clocks = <&cru PCLK_PWM>; | |
581 | clock-names = "pwm"; | |
582 | status = "disabled"; | |
583 | }; | |
584 | ||
585 | pwm1: pwm@ff680010 { | |
586 | compatible = "rockchip,rk3288-pwm"; | |
587 | reg = <0xff680010 0x10>; | |
588 | #pwm-cells = <3>; | |
589 | pinctrl-names = "default"; | |
590 | pinctrl-0 = <&pwm1_pin>; | |
591 | clocks = <&cru PCLK_PWM>; | |
592 | clock-names = "pwm"; | |
593 | status = "disabled"; | |
594 | }; | |
595 | ||
596 | pwm2: pwm@ff680020 { | |
597 | compatible = "rockchip,rk3288-pwm"; | |
598 | reg = <0xff680020 0x10>; | |
599 | #pwm-cells = <3>; | |
600 | pinctrl-names = "default"; | |
601 | pinctrl-0 = <&pwm2_pin>; | |
602 | clocks = <&cru PCLK_PWM>; | |
603 | clock-names = "pwm"; | |
604 | status = "disabled"; | |
605 | }; | |
606 | ||
607 | pwm3: pwm@ff680030 { | |
608 | compatible = "rockchip,rk3288-pwm"; | |
609 | reg = <0xff680030 0x10>; | |
610 | #pwm-cells = <2>; | |
611 | pinctrl-names = "default"; | |
612 | pinctrl-0 = <&pwm3_pin>; | |
613 | clocks = <&cru PCLK_PWM>; | |
614 | clock-names = "pwm"; | |
615 | status = "disabled"; | |
616 | }; | |
617 | ||
1123d412 KY |
618 | bus_intmem@ff700000 { |
619 | compatible = "mmio-sram"; | |
620 | reg = <0xff700000 0x18000>; | |
621 | #address-cells = <1>; | |
622 | #size-cells = <1>; | |
623 | ranges = <0 0xff700000 0x18000>; | |
624 | smp-sram@0 { | |
625 | compatible = "rockchip,rk3066-smp-sram"; | |
626 | reg = <0x00 0x10>; | |
627 | }; | |
628 | }; | |
629 | ||
eecfe981 CZ |
630 | sram@ff720000 { |
631 | compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; | |
632 | reg = <0xff720000 0x1000>; | |
633 | }; | |
634 | ||
2ab557b7 | 635 | pmu: power-management@ff730000 { |
b63af764 | 636 | compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; |
2ab557b7 | 637 | reg = <0xff730000 0x100>; |
b63af764 CW |
638 | |
639 | power: power-controller { | |
640 | compatible = "rockchip,rk3288-power-controller"; | |
641 | #power-domain-cells = <1>; | |
642 | #address-cells = <1>; | |
643 | #size-cells = <0>; | |
644 | ||
df5ea015 SS |
645 | assigned-clocks = <&cru SCLK_EDP_24M>; |
646 | assigned-clock-parents = <&xin24m>; | |
647 | ||
b63af764 CW |
648 | /* |
649 | * Note: Although SCLK_* are the working clocks | |
650 | * of device without including on the NOC, needed for | |
651 | * synchronous reset. | |
652 | * | |
653 | * The clocks on the which NOC: | |
654 | * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. | |
655 | * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. | |
656 | * ACLK_RGA is on ACLK_RGA_NIU. | |
657 | * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. | |
658 | * | |
659 | * Which clock are device clocks: | |
660 | * clocks devices | |
661 | * *_IEP IEP:Image Enhancement Processor | |
662 | * *_ISP ISP:Image Signal Processing | |
663 | * *_VIP VIP:Video Input Processor | |
664 | * *_VOP* VOP:Visual Output Processor | |
665 | * *_RGA RGA | |
666 | * *_EDP* EDP | |
667 | * *_LVDS_* LVDS | |
668 | * *_HDMI HDMI | |
669 | * *_MIPI_* MIPI | |
670 | */ | |
95cface9 | 671 | pd_vio@RK3288_PD_VIO { |
b63af764 CW |
672 | reg = <RK3288_PD_VIO>; |
673 | clocks = <&cru ACLK_IEP>, | |
674 | <&cru ACLK_ISP>, | |
675 | <&cru ACLK_RGA>, | |
676 | <&cru ACLK_VIP>, | |
677 | <&cru ACLK_VOP0>, | |
678 | <&cru ACLK_VOP1>, | |
679 | <&cru DCLK_VOP0>, | |
680 | <&cru DCLK_VOP1>, | |
681 | <&cru HCLK_IEP>, | |
682 | <&cru HCLK_ISP>, | |
683 | <&cru HCLK_RGA>, | |
684 | <&cru HCLK_VIP>, | |
685 | <&cru HCLK_VOP0>, | |
686 | <&cru HCLK_VOP1>, | |
687 | <&cru PCLK_EDP_CTRL>, | |
688 | <&cru PCLK_HDMI_CTRL>, | |
689 | <&cru PCLK_LVDS_PHY>, | |
690 | <&cru PCLK_MIPI_CSI>, | |
691 | <&cru PCLK_MIPI_DSI0>, | |
692 | <&cru PCLK_MIPI_DSI1>, | |
693 | <&cru SCLK_EDP_24M>, | |
694 | <&cru SCLK_EDP>, | |
695 | <&cru SCLK_ISP_JPE>, | |
696 | <&cru SCLK_ISP>, | |
697 | <&cru SCLK_RGA>; | |
698 | }; | |
699 | ||
700 | /* | |
701 | * Note: The following 3 are HEVC(H.265) clocks, | |
702 | * and on the ACLK_HEVC_NIU (NOC). | |
703 | */ | |
95cface9 | 704 | pd_hevc@RK3288_PD_HEVC { |
b63af764 CW |
705 | reg = <RK3288_PD_HEVC>; |
706 | clocks = <&cru ACLK_HEVC>, | |
707 | <&cru SCLK_HEVC_CABAC>, | |
708 | <&cru SCLK_HEVC_CORE>; | |
709 | }; | |
710 | ||
711 | /* | |
712 | * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC | |
713 | * (video endecoder & decoder) clocks that on the | |
714 | * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). | |
715 | */ | |
95cface9 | 716 | pd_video@RK3288_PD_VIDEO { |
b63af764 CW |
717 | reg = <RK3288_PD_VIDEO>; |
718 | clocks = <&cru ACLK_VCODEC>, | |
719 | <&cru HCLK_VCODEC>; | |
720 | }; | |
721 | ||
722 | /* | |
723 | * Note: ACLK_GPU is the GPU clock, | |
724 | * and on the ACLK_GPU_NIU (NOC). | |
725 | */ | |
95cface9 | 726 | pd_gpu@RK3288_PD_GPU { |
b63af764 CW |
727 | reg = <RK3288_PD_GPU>; |
728 | clocks = <&cru ACLK_GPU>; | |
729 | }; | |
730 | }; | |
2ab557b7 HS |
731 | }; |
732 | ||
733 | sgrf: syscon@ff740000 { | |
734 | compatible = "rockchip,rk3288-sgrf", "syscon"; | |
735 | reg = <0xff740000 0x1000>; | |
736 | }; | |
737 | ||
738 | cru: clock-controller@ff760000 { | |
739 | compatible = "rockchip,rk3288-cru"; | |
740 | reg = <0xff760000 0x1000>; | |
741 | rockchip,grf = <&grf>; | |
742 | #clock-cells = <1>; | |
743 | #reset-cells = <1>; | |
cd78d0cd KY |
744 | assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, |
745 | <&cru PLL_NPLL>, <&cru ACLK_CPU>, | |
746 | <&cru HCLK_CPU>, <&cru PCLK_CPU>, | |
747 | <&cru ACLK_PERI>, <&cru HCLK_PERI>, | |
748 | <&cru PCLK_PERI>; | |
749 | assigned-clock-rates = <594000000>, <400000000>, | |
750 | <500000000>, <300000000>, | |
751 | <150000000>, <75000000>, | |
752 | <300000000>, <150000000>, | |
753 | <75000000>; | |
2ab557b7 HS |
754 | }; |
755 | ||
756 | grf: syscon@ff770000 { | |
757 | compatible = "rockchip,rk3288-grf", "syscon"; | |
758 | reg = <0xff770000 0x1000>; | |
759 | }; | |
760 | ||
761 | wdt: watchdog@ff800000 { | |
762 | compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; | |
763 | reg = <0xff800000 0x100>; | |
39d05162 | 764 | clocks = <&cru PCLK_WDT>; |
1a1b698b | 765 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
2ab557b7 HS |
766 | status = "disabled"; |
767 | }; | |
768 | ||
874e568e SS |
769 | spdif: sound@ff88b0000 { |
770 | compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; | |
771 | reg = <0xff8b0000 0x10000>; | |
772 | #sound-dai-cells = <0>; | |
773 | clock-names = "hclk", "mclk"; | |
774 | clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; | |
775 | dmas = <&dmac_bus_s 3>; | |
776 | dma-names = "tx"; | |
57dcfa56 | 777 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
874e568e SS |
778 | pinctrl-names = "default"; |
779 | pinctrl-0 = <&spdif_tx>; | |
780 | rockchip,grf = <&grf>; | |
781 | status = "disabled"; | |
782 | }; | |
783 | ||
a0f95e35 J |
784 | i2s: i2s@ff890000 { |
785 | compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; | |
786 | reg = <0xff890000 0x10000>; | |
57dcfa56 | 787 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
a0f95e35 J |
788 | #address-cells = <1>; |
789 | #size-cells = <0>; | |
790 | dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; | |
791 | dma-names = "tx", "rx"; | |
792 | clock-names = "i2s_hclk", "i2s_clk"; | |
793 | clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; | |
794 | pinctrl-names = "default"; | |
795 | pinctrl-0 = <&i2s0_bus>; | |
e241657d SZ |
796 | rockchip,playback-channels = <8>; |
797 | rockchip,capture-channels = <2>; | |
a0f95e35 J |
798 | status = "disabled"; |
799 | }; | |
800 | ||
c2cb6161 ZW |
801 | crypto: cypto-controller@ff8a0000 { |
802 | compatible = "rockchip,rk3288-crypto"; | |
803 | reg = <0xff8a0000 0x4000>; | |
804 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
805 | clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, | |
806 | <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; | |
807 | clock-names = "aclk", "hclk", "sclk", "apb_pclk"; | |
808 | resets = <&cru SRST_CRYPTO>; | |
809 | reset-names = "crypto-rst"; | |
810 | status = "okay"; | |
811 | }; | |
812 | ||
a29cb8c4 DK |
813 | vopb: vop@ff930000 { |
814 | compatible = "rockchip,rk3288-vop"; | |
815 | reg = <0xff930000 0x19c>; | |
816 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
817 | clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; | |
818 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 819 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
820 | resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; |
821 | reset-names = "axi", "ahb", "dclk"; | |
822 | iommus = <&vopb_mmu>; | |
823 | status = "disabled"; | |
824 | ||
825 | vopb_out: port { | |
826 | #address-cells = <1>; | |
827 | #size-cells = <0>; | |
d5a1df48 AY |
828 | |
829 | vopb_out_hdmi: endpoint@0 { | |
830 | reg = <0>; | |
831 | remote-endpoint = <&hdmi_in_vopb>; | |
832 | }; | |
6df7ec61 HS |
833 | |
834 | vopb_out_edp: endpoint@1 { | |
835 | reg = <1>; | |
836 | remote-endpoint = <&edp_in_vopb>; | |
837 | }; | |
838 | ||
cab6f070 CZ |
839 | vopb_out_mipi: endpoint@2 { |
840 | reg = <2>; | |
841 | remote-endpoint = <&mipi_in_vopb>; | |
842 | }; | |
a29cb8c4 DK |
843 | }; |
844 | }; | |
845 | ||
7cae068b DK |
846 | vopb_mmu: iommu@ff930300 { |
847 | compatible = "rockchip,iommu"; | |
848 | reg = <0xff930300 0x100>; | |
849 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
850 | interrupt-names = "vopb_mmu"; | |
b63af764 | 851 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
852 | #iommu-cells = <0>; |
853 | status = "disabled"; | |
854 | }; | |
855 | ||
a29cb8c4 DK |
856 | vopl: vop@ff940000 { |
857 | compatible = "rockchip,rk3288-vop"; | |
858 | reg = <0xff940000 0x19c>; | |
859 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
860 | clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; | |
861 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 862 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
863 | resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; |
864 | reset-names = "axi", "ahb", "dclk"; | |
865 | iommus = <&vopl_mmu>; | |
866 | status = "disabled"; | |
867 | ||
868 | vopl_out: port { | |
869 | #address-cells = <1>; | |
870 | #size-cells = <0>; | |
d5a1df48 AY |
871 | |
872 | vopl_out_hdmi: endpoint@0 { | |
873 | reg = <0>; | |
874 | remote-endpoint = <&hdmi_in_vopl>; | |
875 | }; | |
6df7ec61 HS |
876 | |
877 | vopl_out_edp: endpoint@1 { | |
878 | reg = <1>; | |
879 | remote-endpoint = <&edp_in_vopl>; | |
880 | }; | |
881 | ||
cab6f070 CZ |
882 | vopl_out_mipi: endpoint@2 { |
883 | reg = <2>; | |
884 | remote-endpoint = <&mipi_in_vopl>; | |
885 | }; | |
a29cb8c4 DK |
886 | }; |
887 | }; | |
888 | ||
7cae068b DK |
889 | vopl_mmu: iommu@ff940300 { |
890 | compatible = "rockchip,iommu"; | |
891 | reg = <0xff940300 0x100>; | |
892 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
893 | interrupt-names = "vopl_mmu"; | |
b63af764 | 894 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
895 | #iommu-cells = <0>; |
896 | status = "disabled"; | |
897 | }; | |
898 | ||
cab6f070 CZ |
899 | mipi_dsi: mipi@ff960000 { |
900 | compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; | |
901 | reg = <0xff960000 0x4000>; | |
5415ba40 | 902 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
cab6f070 CZ |
903 | clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; |
904 | clock-names = "ref", "pclk"; | |
1946a201 | 905 | power-domains = <&power RK3288_PD_VIO>; |
cab6f070 CZ |
906 | rockchip,grf = <&grf>; |
907 | #address-cells = <1>; | |
908 | #size-cells = <0>; | |
909 | status = "disabled"; | |
910 | ||
911 | ports { | |
cab6f070 CZ |
912 | mipi_in: port { |
913 | #address-cells = <1>; | |
914 | #size-cells = <0>; | |
915 | mipi_in_vopb: endpoint@0 { | |
916 | reg = <0>; | |
917 | remote-endpoint = <&vopb_out_mipi>; | |
918 | }; | |
919 | mipi_in_vopl: endpoint@1 { | |
920 | reg = <1>; | |
921 | remote-endpoint = <&vopl_out_mipi>; | |
922 | }; | |
923 | }; | |
924 | }; | |
925 | }; | |
926 | ||
6df7ec61 HS |
927 | edp: dp@ff970000 { |
928 | compatible = "rockchip,rk3288-dp"; | |
929 | reg = <0xff970000 0x4000>; | |
930 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
931 | clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; | |
932 | clock-names = "dp", "pclk"; | |
933 | phys = <&edp_phy>; | |
934 | phy-names = "dp"; | |
935 | resets = <&cru SRST_EDP>; | |
936 | reset-names = "dp"; | |
937 | rockchip,grf = <&grf>; | |
938 | status = "disabled"; | |
939 | ||
940 | ports { | |
941 | #address-cells = <1>; | |
942 | #size-cells = <0>; | |
943 | edp_in: port@0 { | |
944 | reg = <0>; | |
945 | #address-cells = <1>; | |
946 | #size-cells = <0>; | |
947 | edp_in_vopb: endpoint@0 { | |
948 | reg = <0>; | |
949 | remote-endpoint = <&vopb_out_edp>; | |
950 | }; | |
951 | edp_in_vopl: endpoint@1 { | |
952 | reg = <1>; | |
953 | remote-endpoint = <&vopl_out_edp>; | |
954 | }; | |
955 | }; | |
956 | }; | |
957 | }; | |
958 | ||
d5a1df48 AY |
959 | hdmi: hdmi@ff980000 { |
960 | compatible = "rockchip,rk3288-dw-hdmi"; | |
961 | reg = <0xff980000 0x20000>; | |
962 | reg-io-width = <4>; | |
d5a1df48 AY |
963 | rockchip,grf = <&grf>; |
964 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
965 | clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; | |
966 | clock-names = "iahb", "isfr"; | |
b63af764 | 967 | power-domains = <&power RK3288_PD_VIO>; |
d5a1df48 AY |
968 | status = "disabled"; |
969 | ||
970 | ports { | |
971 | hdmi_in: port { | |
972 | #address-cells = <1>; | |
973 | #size-cells = <0>; | |
974 | hdmi_in_vopb: endpoint@0 { | |
975 | reg = <0>; | |
976 | remote-endpoint = <&vopb_out_hdmi>; | |
977 | }; | |
978 | hdmi_in_vopl: endpoint@1 { | |
979 | reg = <1>; | |
980 | remote-endpoint = <&vopl_out_hdmi>; | |
981 | }; | |
982 | }; | |
983 | }; | |
984 | }; | |
985 | ||
2ab557b7 HS |
986 | gic: interrupt-controller@ffc01000 { |
987 | compatible = "arm,gic-400"; | |
988 | interrupt-controller; | |
989 | #interrupt-cells = <3>; | |
990 | #address-cells = <0>; | |
991 | ||
992 | reg = <0xffc01000 0x1000>, | |
993 | <0xffc02000 0x1000>, | |
994 | <0xffc04000 0x2000>, | |
995 | <0xffc06000 0x2000>; | |
996 | interrupts = <GIC_PPI 9 0xf04>; | |
997 | }; | |
998 | ||
88185559 Z |
999 | efuse: efuse@ffb40000 { |
1000 | compatible = "rockchip,rockchip-efuse"; | |
1001 | reg = <0xffb40000 0x20>; | |
1002 | #address-cells = <1>; | |
1003 | #size-cells = <1>; | |
1004 | clocks = <&cru PCLK_EFUSE256>; | |
1005 | clock-names = "pclk_efuse"; | |
1006 | ||
1007 | cpu_leakage: cpu_leakage@17 { | |
1008 | reg = <0x17 0x1>; | |
1009 | }; | |
1010 | }; | |
1011 | ||
f6db7029 YL |
1012 | usbphy: phy { |
1013 | compatible = "rockchip,rk3288-usb-phy"; | |
1014 | rockchip,grf = <&grf>; | |
1015 | #address-cells = <1>; | |
1016 | #size-cells = <0>; | |
1017 | status = "disabled"; | |
1018 | ||
a8f0fa27 | 1019 | usbphy0: usb-phy@320 { |
f6db7029 YL |
1020 | #phy-cells = <0>; |
1021 | reg = <0x320>; | |
1022 | clocks = <&cru SCLK_OTGPHY0>; | |
1023 | clock-names = "phyclk"; | |
0ace8217 | 1024 | #clock-cells = <0>; |
f6db7029 YL |
1025 | }; |
1026 | ||
a8f0fa27 | 1027 | usbphy1: usb-phy@334 { |
f6db7029 YL |
1028 | #phy-cells = <0>; |
1029 | reg = <0x334>; | |
1030 | clocks = <&cru SCLK_OTGPHY1>; | |
1031 | clock-names = "phyclk"; | |
0ace8217 | 1032 | #clock-cells = <0>; |
f6db7029 YL |
1033 | }; |
1034 | ||
a8f0fa27 | 1035 | usbphy2: usb-phy@348 { |
f6db7029 YL |
1036 | #phy-cells = <0>; |
1037 | reg = <0x348>; | |
1038 | clocks = <&cru SCLK_OTGPHY2>; | |
1039 | clock-names = "phyclk"; | |
0ace8217 | 1040 | #clock-cells = <0>; |
f6db7029 YL |
1041 | }; |
1042 | }; | |
1043 | ||
2ab557b7 HS |
1044 | pinctrl: pinctrl { |
1045 | compatible = "rockchip,rk3288-pinctrl"; | |
1046 | rockchip,grf = <&grf>; | |
1047 | rockchip,pmu = <&pmu>; | |
1048 | #address-cells = <1>; | |
1049 | #size-cells = <1>; | |
1050 | ranges; | |
1051 | ||
1052 | gpio0: gpio0@ff750000 { | |
1053 | compatible = "rockchip,gpio-bank"; | |
1054 | reg = <0xff750000 0x100>; | |
1055 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
1056 | clocks = <&cru PCLK_GPIO0>; | |
1057 | ||
1058 | gpio-controller; | |
1059 | #gpio-cells = <2>; | |
1060 | ||
1061 | interrupt-controller; | |
1062 | #interrupt-cells = <2>; | |
1063 | }; | |
1064 | ||
1065 | gpio1: gpio1@ff780000 { | |
1066 | compatible = "rockchip,gpio-bank"; | |
1067 | reg = <0xff780000 0x100>; | |
1068 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
1069 | clocks = <&cru PCLK_GPIO1>; | |
1070 | ||
1071 | gpio-controller; | |
1072 | #gpio-cells = <2>; | |
1073 | ||
1074 | interrupt-controller; | |
1075 | #interrupt-cells = <2>; | |
1076 | }; | |
1077 | ||
1078 | gpio2: gpio2@ff790000 { | |
1079 | compatible = "rockchip,gpio-bank"; | |
1080 | reg = <0xff790000 0x100>; | |
1081 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
1082 | clocks = <&cru PCLK_GPIO2>; | |
1083 | ||
1084 | gpio-controller; | |
1085 | #gpio-cells = <2>; | |
1086 | ||
1087 | interrupt-controller; | |
1088 | #interrupt-cells = <2>; | |
1089 | }; | |
1090 | ||
1091 | gpio3: gpio3@ff7a0000 { | |
1092 | compatible = "rockchip,gpio-bank"; | |
1093 | reg = <0xff7a0000 0x100>; | |
1094 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
1095 | clocks = <&cru PCLK_GPIO3>; | |
1096 | ||
1097 | gpio-controller; | |
1098 | #gpio-cells = <2>; | |
1099 | ||
1100 | interrupt-controller; | |
1101 | #interrupt-cells = <2>; | |
1102 | }; | |
1103 | ||
1104 | gpio4: gpio4@ff7b0000 { | |
1105 | compatible = "rockchip,gpio-bank"; | |
1106 | reg = <0xff7b0000 0x100>; | |
1107 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
1108 | clocks = <&cru PCLK_GPIO4>; | |
1109 | ||
1110 | gpio-controller; | |
1111 | #gpio-cells = <2>; | |
1112 | ||
1113 | interrupt-controller; | |
1114 | #interrupt-cells = <2>; | |
1115 | }; | |
1116 | ||
1117 | gpio5: gpio5@ff7c0000 { | |
1118 | compatible = "rockchip,gpio-bank"; | |
1119 | reg = <0xff7c0000 0x100>; | |
1120 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
1121 | clocks = <&cru PCLK_GPIO5>; | |
1122 | ||
1123 | gpio-controller; | |
1124 | #gpio-cells = <2>; | |
1125 | ||
1126 | interrupt-controller; | |
1127 | #interrupt-cells = <2>; | |
1128 | }; | |
1129 | ||
1130 | gpio6: gpio6@ff7d0000 { | |
1131 | compatible = "rockchip,gpio-bank"; | |
1132 | reg = <0xff7d0000 0x100>; | |
1133 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
1134 | clocks = <&cru PCLK_GPIO6>; | |
1135 | ||
1136 | gpio-controller; | |
1137 | #gpio-cells = <2>; | |
1138 | ||
1139 | interrupt-controller; | |
1140 | #interrupt-cells = <2>; | |
1141 | }; | |
1142 | ||
1143 | gpio7: gpio7@ff7e0000 { | |
1144 | compatible = "rockchip,gpio-bank"; | |
1145 | reg = <0xff7e0000 0x100>; | |
1146 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
1147 | clocks = <&cru PCLK_GPIO7>; | |
1148 | ||
1149 | gpio-controller; | |
1150 | #gpio-cells = <2>; | |
1151 | ||
1152 | interrupt-controller; | |
1153 | #interrupt-cells = <2>; | |
1154 | }; | |
1155 | ||
1156 | gpio8: gpio8@ff7f0000 { | |
1157 | compatible = "rockchip,gpio-bank"; | |
1158 | reg = <0xff7f0000 0x100>; | |
1159 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
1160 | clocks = <&cru PCLK_GPIO8>; | |
1161 | ||
1162 | gpio-controller; | |
1163 | #gpio-cells = <2>; | |
1164 | ||
1165 | interrupt-controller; | |
1166 | #interrupt-cells = <2>; | |
1167 | }; | |
1168 | ||
e61ccb12 DA |
1169 | hdmi { |
1170 | hdmi_ddc: hdmi-ddc { | |
1171 | rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, | |
1172 | <7 20 RK_FUNC_2 &pcfg_pull_none>; | |
1173 | }; | |
1174 | }; | |
1175 | ||
2ab557b7 HS |
1176 | pcfg_pull_up: pcfg-pull-up { |
1177 | bias-pull-up; | |
1178 | }; | |
1179 | ||
1180 | pcfg_pull_down: pcfg-pull-down { | |
1181 | bias-pull-down; | |
1182 | }; | |
1183 | ||
1184 | pcfg_pull_none: pcfg-pull-none { | |
1185 | bias-disable; | |
1186 | }; | |
1187 | ||
3d3fb74a RC |
1188 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { |
1189 | bias-disable; | |
1190 | drive-strength = <12>; | |
1191 | }; | |
1192 | ||
eecfe981 CZ |
1193 | sleep { |
1194 | global_pwroff: global-pwroff { | |
1195 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; | |
1196 | }; | |
1197 | ||
1198 | ddrio_pwroff: ddrio-pwroff { | |
1199 | rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
1200 | }; | |
1201 | ||
1202 | ddr0_retention: ddr0-retention { | |
1203 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; | |
1204 | }; | |
1205 | ||
1206 | ddr1_retention: ddr1-retention { | |
1207 | rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; | |
1208 | }; | |
1209 | }; | |
1210 | ||
2ab557b7 HS |
1211 | i2c0 { |
1212 | i2c0_xfer: i2c0-xfer { | |
1213 | rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, | |
1214 | <0 16 RK_FUNC_1 &pcfg_pull_none>; | |
1215 | }; | |
1216 | }; | |
1217 | ||
1218 | i2c1 { | |
1219 | i2c1_xfer: i2c1-xfer { | |
1220 | rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, | |
1221 | <8 5 RK_FUNC_1 &pcfg_pull_none>; | |
1222 | }; | |
1223 | }; | |
1224 | ||
1225 | i2c2 { | |
1226 | i2c2_xfer: i2c2-xfer { | |
1227 | rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, | |
1228 | <6 10 RK_FUNC_1 &pcfg_pull_none>; | |
1229 | }; | |
1230 | }; | |
1231 | ||
1232 | i2c3 { | |
1233 | i2c3_xfer: i2c3-xfer { | |
1234 | rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
1235 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
1236 | }; | |
1237 | }; | |
1238 | ||
1239 | i2c4 { | |
1240 | i2c4_xfer: i2c4-xfer { | |
1241 | rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, | |
1242 | <7 18 RK_FUNC_1 &pcfg_pull_none>; | |
1243 | }; | |
1244 | }; | |
1245 | ||
1246 | i2c5 { | |
1247 | i2c5_xfer: i2c5-xfer { | |
1248 | rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, | |
1249 | <7 20 RK_FUNC_1 &pcfg_pull_none>; | |
a0f95e35 J |
1250 | }; |
1251 | }; | |
1252 | ||
1253 | i2s0 { | |
1254 | i2s0_bus: i2s0-bus { | |
1255 | rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, | |
1256 | <6 1 RK_FUNC_1 &pcfg_pull_none>, | |
1257 | <6 2 RK_FUNC_1 &pcfg_pull_none>, | |
1258 | <6 3 RK_FUNC_1 &pcfg_pull_none>, | |
1259 | <6 4 RK_FUNC_1 &pcfg_pull_none>, | |
1260 | <6 8 RK_FUNC_1 &pcfg_pull_none>; | |
2ab557b7 HS |
1261 | }; |
1262 | }; | |
1263 | ||
1264 | sdmmc { | |
1265 | sdmmc_clk: sdmmc-clk { | |
1266 | rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; | |
1267 | }; | |
1268 | ||
1269 | sdmmc_cmd: sdmmc-cmd { | |
1270 | rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; | |
1271 | }; | |
1272 | ||
d59df5d1 | 1273 | sdmmc_cd: sdmmc-cd { |
2ab557b7 HS |
1274 | rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; |
1275 | }; | |
1276 | ||
1277 | sdmmc_bus1: sdmmc-bus1 { | |
1278 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; | |
1279 | }; | |
1280 | ||
1281 | sdmmc_bus4: sdmmc-bus4 { | |
1282 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, | |
1283 | <6 17 RK_FUNC_1 &pcfg_pull_up>, | |
1284 | <6 18 RK_FUNC_1 &pcfg_pull_up>, | |
1285 | <6 19 RK_FUNC_1 &pcfg_pull_up>; | |
1286 | }; | |
1287 | }; | |
1288 | ||
f1a07231 AK |
1289 | sdio0 { |
1290 | sdio0_bus1: sdio0-bus1 { | |
1291 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; | |
1292 | }; | |
1293 | ||
1294 | sdio0_bus4: sdio0-bus4 { | |
1295 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, | |
1296 | <4 21 RK_FUNC_1 &pcfg_pull_up>, | |
1297 | <4 22 RK_FUNC_1 &pcfg_pull_up>, | |
1298 | <4 23 RK_FUNC_1 &pcfg_pull_up>; | |
1299 | }; | |
1300 | ||
1301 | sdio0_cmd: sdio0-cmd { | |
1302 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; | |
1303 | }; | |
1304 | ||
1305 | sdio0_clk: sdio0-clk { | |
1306 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; | |
1307 | }; | |
1308 | ||
1309 | sdio0_cd: sdio0-cd { | |
1310 | rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; | |
1311 | }; | |
1312 | ||
1313 | sdio0_wp: sdio0-wp { | |
1314 | rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; | |
1315 | }; | |
1316 | ||
1317 | sdio0_pwr: sdio0-pwr { | |
1318 | rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; | |
1319 | }; | |
1320 | ||
1321 | sdio0_bkpwr: sdio0-bkpwr { | |
1322 | rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; | |
1323 | }; | |
1324 | ||
1325 | sdio0_int: sdio0-int { | |
1326 | rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; | |
1327 | }; | |
1328 | }; | |
1329 | ||
1330 | sdio1 { | |
1331 | sdio1_bus1: sdio1-bus1 { | |
1332 | rockchip,pins = <3 24 4 &pcfg_pull_up>; | |
1333 | }; | |
1334 | ||
1335 | sdio1_bus4: sdio1-bus4 { | |
1336 | rockchip,pins = <3 24 4 &pcfg_pull_up>, | |
1337 | <3 25 4 &pcfg_pull_up>, | |
1338 | <3 26 4 &pcfg_pull_up>, | |
1339 | <3 27 4 &pcfg_pull_up>; | |
1340 | }; | |
1341 | ||
1342 | sdio1_cd: sdio1-cd { | |
1343 | rockchip,pins = <3 28 4 &pcfg_pull_up>; | |
1344 | }; | |
1345 | ||
1346 | sdio1_wp: sdio1-wp { | |
1347 | rockchip,pins = <3 29 4 &pcfg_pull_up>; | |
1348 | }; | |
1349 | ||
1350 | sdio1_bkpwr: sdio1-bkpwr { | |
1351 | rockchip,pins = <3 30 4 &pcfg_pull_up>; | |
1352 | }; | |
1353 | ||
1354 | sdio1_int: sdio1-int { | |
1355 | rockchip,pins = <3 31 4 &pcfg_pull_up>; | |
1356 | }; | |
1357 | ||
1358 | sdio1_cmd: sdio1-cmd { | |
1359 | rockchip,pins = <4 6 4 &pcfg_pull_up>; | |
1360 | }; | |
1361 | ||
1362 | sdio1_clk: sdio1-clk { | |
1363 | rockchip,pins = <4 7 4 &pcfg_pull_none>; | |
1364 | }; | |
1365 | ||
1366 | sdio1_pwr: sdio1-pwr { | |
1367 | rockchip,pins = <4 9 4 &pcfg_pull_up>; | |
1368 | }; | |
1369 | }; | |
1370 | ||
2ab557b7 HS |
1371 | emmc { |
1372 | emmc_clk: emmc-clk { | |
1373 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
1374 | }; | |
1375 | ||
1376 | emmc_cmd: emmc-cmd { | |
1377 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; | |
1378 | }; | |
1379 | ||
1380 | emmc_pwr: emmc-pwr { | |
1381 | rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; | |
1382 | }; | |
1383 | ||
1384 | emmc_bus1: emmc-bus1 { | |
1385 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
1386 | }; | |
1387 | ||
1388 | emmc_bus4: emmc-bus4 { | |
1389 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1390 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1391 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1392 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
1393 | }; | |
1394 | ||
1395 | emmc_bus8: emmc-bus8 { | |
1396 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1397 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1398 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1399 | <3 3 RK_FUNC_2 &pcfg_pull_up>, | |
1400 | <3 4 RK_FUNC_2 &pcfg_pull_up>, | |
1401 | <3 5 RK_FUNC_2 &pcfg_pull_up>, | |
1402 | <3 6 RK_FUNC_2 &pcfg_pull_up>, | |
1403 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
1404 | }; | |
1405 | }; | |
1406 | ||
1f53170b | 1407 | spi0 { |
1408 | spi0_clk: spi0-clk { | |
1409 | rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; | |
1410 | }; | |
1411 | spi0_cs0: spi0-cs0 { | |
1412 | rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; | |
1413 | }; | |
1414 | spi0_tx: spi0-tx { | |
1415 | rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; | |
1416 | }; | |
1417 | spi0_rx: spi0-rx { | |
1418 | rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; | |
1419 | }; | |
1420 | spi0_cs1: spi0-cs1 { | |
1421 | rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; | |
1422 | }; | |
1423 | }; | |
1424 | spi1 { | |
1425 | spi1_clk: spi1-clk { | |
1426 | rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; | |
1427 | }; | |
1428 | spi1_cs0: spi1-cs0 { | |
1429 | rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; | |
1430 | }; | |
1431 | spi1_rx: spi1-rx { | |
1432 | rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; | |
1433 | }; | |
1434 | spi1_tx: spi1-tx { | |
1435 | rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; | |
1436 | }; | |
1437 | }; | |
1438 | ||
1439 | spi2 { | |
1440 | spi2_cs1: spi2-cs1 { | |
1441 | rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; | |
1442 | }; | |
1443 | spi2_clk: spi2-clk { | |
1444 | rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; | |
1445 | }; | |
1446 | spi2_cs0: spi2-cs0 { | |
1447 | rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; | |
1448 | }; | |
1449 | spi2_rx: spi2-rx { | |
1450 | rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; | |
1451 | }; | |
1452 | spi2_tx: spi2-tx { | |
1453 | rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; | |
1454 | }; | |
1455 | }; | |
1456 | ||
2ab557b7 HS |
1457 | uart0 { |
1458 | uart0_xfer: uart0-xfer { | |
1459 | rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, | |
1460 | <4 17 RK_FUNC_1 &pcfg_pull_none>; | |
1461 | }; | |
1462 | ||
1463 | uart0_cts: uart0-cts { | |
8915f364 | 1464 | rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1465 | }; |
1466 | ||
1467 | uart0_rts: uart0-rts { | |
1468 | rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; | |
1469 | }; | |
1470 | }; | |
1471 | ||
1472 | uart1 { | |
1473 | uart1_xfer: uart1-xfer { | |
1474 | rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, | |
1475 | <5 9 RK_FUNC_1 &pcfg_pull_none>; | |
1476 | }; | |
1477 | ||
1478 | uart1_cts: uart1-cts { | |
8915f364 | 1479 | rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1480 | }; |
1481 | ||
1482 | uart1_rts: uart1-rts { | |
1483 | rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; | |
1484 | }; | |
1485 | }; | |
1486 | ||
1487 | uart2 { | |
1488 | uart2_xfer: uart2-xfer { | |
1489 | rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, | |
1490 | <7 23 RK_FUNC_1 &pcfg_pull_none>; | |
1491 | }; | |
1492 | /* no rts / cts for uart2 */ | |
1493 | }; | |
1494 | ||
1495 | uart3 { | |
1496 | uart3_xfer: uart3-xfer { | |
1497 | rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, | |
1498 | <7 8 RK_FUNC_1 &pcfg_pull_none>; | |
1499 | }; | |
1500 | ||
1501 | uart3_cts: uart3-cts { | |
8915f364 | 1502 | rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1503 | }; |
1504 | ||
1505 | uart3_rts: uart3-rts { | |
1506 | rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; | |
1507 | }; | |
1508 | }; | |
1509 | ||
1510 | uart4 { | |
1511 | uart4_xfer: uart4-xfer { | |
1512 | rockchip,pins = <5 12 3 &pcfg_pull_up>, | |
1513 | <5 13 3 &pcfg_pull_none>; | |
1514 | }; | |
1515 | ||
1516 | uart4_cts: uart4-cts { | |
8915f364 | 1517 | rockchip,pins = <5 14 3 &pcfg_pull_up>; |
2ab557b7 HS |
1518 | }; |
1519 | ||
1520 | uart4_rts: uart4-rts { | |
1521 | rockchip,pins = <5 15 3 &pcfg_pull_none>; | |
1522 | }; | |
1523 | }; | |
df542df3 | 1524 | |
b67d6bc3 | 1525 | tsadc { |
784359b8 CW |
1526 | otp_gpio: otp-gpio { |
1527 | rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; | |
1528 | }; | |
1529 | ||
b67d6bc3 CW |
1530 | otp_out: otp-out { |
1531 | rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; | |
1532 | }; | |
1533 | }; | |
1534 | ||
df542df3 DA |
1535 | pwm0 { |
1536 | pwm0_pin: pwm0-pin { | |
1537 | rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; | |
1538 | }; | |
1539 | }; | |
1540 | ||
1541 | pwm1 { | |
1542 | pwm1_pin: pwm1-pin { | |
1543 | rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; | |
1544 | }; | |
1545 | }; | |
1546 | ||
1547 | pwm2 { | |
1548 | pwm2_pin: pwm2-pin { | |
1549 | rockchip,pins = <7 22 3 &pcfg_pull_none>; | |
1550 | }; | |
1551 | }; | |
1552 | ||
1553 | pwm3 { | |
1554 | pwm3_pin: pwm3-pin { | |
1555 | rockchip,pins = <7 23 3 &pcfg_pull_none>; | |
1556 | }; | |
1557 | }; | |
3d3fb74a RC |
1558 | |
1559 | gmac { | |
1560 | rgmii_pins: rgmii-pins { | |
1561 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1562 | <3 31 3 &pcfg_pull_none>, | |
1563 | <3 26 3 &pcfg_pull_none>, | |
1564 | <3 27 3 &pcfg_pull_none>, | |
1565 | <3 28 3 &pcfg_pull_none_12ma>, | |
1566 | <3 29 3 &pcfg_pull_none_12ma>, | |
1567 | <3 24 3 &pcfg_pull_none_12ma>, | |
1568 | <3 25 3 &pcfg_pull_none_12ma>, | |
1569 | <4 0 3 &pcfg_pull_none>, | |
1570 | <4 5 3 &pcfg_pull_none>, | |
1571 | <4 6 3 &pcfg_pull_none>, | |
1572 | <4 9 3 &pcfg_pull_none_12ma>, | |
1573 | <4 4 3 &pcfg_pull_none_12ma>, | |
1574 | <4 1 3 &pcfg_pull_none>, | |
1575 | <4 3 3 &pcfg_pull_none>; | |
1576 | }; | |
1577 | ||
1578 | rmii_pins: rmii-pins { | |
1579 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1580 | <3 31 3 &pcfg_pull_none>, | |
1581 | <3 28 3 &pcfg_pull_none>, | |
1582 | <3 29 3 &pcfg_pull_none>, | |
1583 | <4 0 3 &pcfg_pull_none>, | |
1584 | <4 5 3 &pcfg_pull_none>, | |
1585 | <4 4 3 &pcfg_pull_none>, | |
1586 | <4 1 3 &pcfg_pull_none>, | |
1587 | <4 2 3 &pcfg_pull_none>, | |
1588 | <4 3 3 &pcfg_pull_none>; | |
1589 | }; | |
1590 | }; | |
874e568e SS |
1591 | |
1592 | spdif { | |
1593 | spdif_tx: spdif-tx { | |
1594 | rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; | |
1595 | }; | |
1596 | }; | |
2ab557b7 HS |
1597 | }; |
1598 | }; |