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ARM: dts: rockchip: enable tsadc on rk3288 boards
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
b67d6bc3 18#include <dt-bindings/thermal/thermal.h>
2ab557b7
HS		 19#include "skeleton.dtsi"
20
21/ {
22 compatible = "rockchip,rk3288";
23
24 interrupt-parent = <&gic>;
25
26 aliases {
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
d7f9a388
DA		 33 mshc0 = &emmc;
34 mshc1 = &sdmmc;
35 mshc2 = &sdio0;
36 mshc3 = &sdio1;
2ab557b7
HS		 37 serial0 = &uart0;
38 serial1 = &uart1;
39 serial2 = &uart2;
40 serial3 = &uart3;
41 serial4 = &uart4;
1f53170b 42 spi0 = &spi0;
43 spi1 = &spi1;
44 spi2 = &spi2;
2ab557b7
HS		 45 };
46
f1840780
SR		 47 arm-pmu {
48 compatible = "arm,cortex-a12-pmu";
49 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
53 };
54
2ab557b7
HS		 55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
08bcc754 58 enable-method = "rockchip,rk3066-smp";
fbdbc732 59 rockchip,pmu = <&pmu>;
2ab557b7 60
be8a77c5 61 cpu0: cpu@500 {
2ab557b7
HS		 62 device_type = "cpu";
63 compatible = "arm,cortex-a12";
64 reg = <0x500>;
044542af 65 resets = <&cru SRST_CORE0>;
be8a77c5
HS		 66 operating-points = <
67 /* KHz uV */
68 1608000 1350000
69 1512000 1300000
70 1416000 1200000
71 1200000 1100000
72 1008000 1050000
73 816000 1000000
74 696000 950000
75 600000 900000
76 408000 900000
77 312000 900000
78 216000 900000
79 126000 900000
80 >;
b67d6bc3 81 #cooling-cells = <2>; /* min followed by max */
be8a77c5
HS		 82 clock-latency = <40000>;
83 clocks = <&cru ARMCLK>;
2ab557b7
HS		 84 };
85 cpu@501 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a12";
88 reg = <0x501>;
044542af 89 resets = <&cru SRST_CORE1>;
2ab557b7
HS		 90 };
91 cpu@502 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a12";
94 reg = <0x502>;
044542af 95 resets = <&cru SRST_CORE2>;
2ab557b7
HS		 96 };
97 cpu@503 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a12";
100 reg = <0x503>;
044542af 101 resets = <&cru SRST_CORE3>;
2ab557b7
HS		 102 };
103 };
104
982891c3
HS		 105 amba {
106 compatible = "arm,amba-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 dmac_peri: dma-controller@ff250000 {
112 compatible = "arm,pl330", "arm,primecell";
113 reg = <0xff250000 0x4000>;
114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
116 #dma-cells = <1>;
117 clocks = <&cru ACLK_DMAC2>;
118 clock-names = "apb_pclk";
119 };
120
121 dmac_bus_ns: dma-controller@ff600000 {
122 compatible = "arm,pl330", "arm,primecell";
123 reg = <0xff600000 0x4000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
126 #dma-cells = <1>;
127 clocks = <&cru ACLK_DMAC1>;
128 clock-names = "apb_pclk";
129 status = "disabled";
130 };
131
132 dmac_bus_s: dma-controller@ffb20000 {
133 compatible = "arm,pl330", "arm,primecell";
134 reg = <0xffb20000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
137 #dma-cells = <1>;
138 clocks = <&cru ACLK_DMAC1>;
139 clock-names = "apb_pclk";
140 };
141 };
142
2ab557b7
HS		 143 xin24m: oscillator {
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "xin24m";
147 #clock-cells = <0>;
148 };
149
150 timer {
151 compatible = "arm,armv7-timer";
e2405a59 152 arm,cpu-registers-not-fw-configured;
2ab557b7
HS		 153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
157 clock-frequency = <24000000>;
158 };
159
e48cc181
DL		 160 timer: timer@ff810000 {
161 compatible = "rockchip,rk3288-timer";
162 reg = <0xff810000 0x20>;
163 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&xin24m>, <&cru PCLK_TIMER>;
165 clock-names = "timer", "pclk";
166 };
167
a29cb8c4
DK		 168 display-subsystem {
169 compatible = "rockchip,display-subsystem";
170 ports = <&vopl_out>, <&vopb_out>;
171 };
172
85095bf3
DA		 173 sdmmc: dwmmc@ff0c0000 {
174 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 175 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 176 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
177 clock-names = "biu", "ciu";
178 fifo-depth = <0x100>;
179 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
180 reg = <0xff0c0000 0x4000>;
181 status = "disabled";
182 };
183
f1a07231
AK		 184 sdio0: dwmmc@ff0d0000 {
185 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 186 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 187 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
188 clock-names = "biu", "ciu";
189 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
191 reg = <0xff0d0000 0x4000>;
192 status = "disabled";
193 };
194
195 sdio1: dwmmc@ff0e0000 {
196 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 197 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 198 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
199 clock-names = "biu", "ciu";
200 fifo-depth = <0x100>;
201 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
202 reg = <0xff0e0000 0x4000>;
203 status = "disabled";
204 };
205
85095bf3
DA		 206 emmc: dwmmc@ff0f0000 {
207 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 208 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 209 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
210 clock-names = "biu", "ciu";
211 fifo-depth = <0x100>;
212 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
213 reg = <0xff0f0000 0x4000>;
214 status = "disabled";
215 };
216
f23a6179
HS		 217 saradc: saradc@ff100000 {
218 compatible = "rockchip,saradc";
219 reg = <0xff100000 0x100>;
220 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
221 #io-channel-cells = <1>;
222 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
223 clock-names = "saradc", "apb_pclk";
224 status = "disabled";
225 };
226
1f53170b 227 spi0: spi@ff110000 {
228 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
229 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
230 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 231 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
232 dma-names = "tx", "rx";
1f53170b 233 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
236 reg = <0xff110000 0x1000>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 status = "disabled";
240 };
241
242 spi1: spi@ff120000 {
243 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
244 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
245 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 246 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
247 dma-names = "tx", "rx";
1f53170b 248 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
251 reg = <0xff120000 0x1000>;
252 #address-cells = <1>;
253 #size-cells = <0>;
254 status = "disabled";
255 };
256
257 spi2: spi@ff130000 {
258 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
259 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
260 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 261 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
262 dma-names = "tx", "rx";
1f53170b 263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
266 reg = <0xff130000 0x1000>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 status = "disabled";
270 };
271
2ab557b7
HS		 272 i2c1: i2c@ff140000 {
273 compatible = "rockchip,rk3288-i2c";
274 reg = <0xff140000 0x1000>;
275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 clock-names = "i2c";
279 clocks = <&cru PCLK_I2C1>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c1_xfer>;
282 status = "disabled";
283 };
284
285 i2c3: i2c@ff150000 {
286 compatible = "rockchip,rk3288-i2c";
287 reg = <0xff150000 0x1000>;
288 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 clock-names = "i2c";
292 clocks = <&cru PCLK_I2C3>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c3_xfer>;
295 status = "disabled";
296 };
297
298 i2c4: i2c@ff160000 {
299 compatible = "rockchip,rk3288-i2c";
300 reg = <0xff160000 0x1000>;
301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 clock-names = "i2c";
305 clocks = <&cru PCLK_I2C4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c4_xfer>;
308 status = "disabled";
309 };
310
311 i2c5: i2c@ff170000 {
312 compatible = "rockchip,rk3288-i2c";
313 reg = <0xff170000 0x1000>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clock-names = "i2c";
318 clocks = <&cru PCLK_I2C5>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c5_xfer>;
321 status = "disabled";
322 };
323
324 uart0: serial@ff180000 {
325 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
326 reg = <0xff180000 0x100>;
327 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
328 reg-shift = <2>;
329 reg-io-width = <4>;
330 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
331 clock-names = "baudclk", "apb_pclk";
332 pinctrl-names = "default";
333 pinctrl-0 = <&uart0_xfer>;
334 status = "disabled";
335 };
336
337 uart1: serial@ff190000 {
338 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
339 reg = <0xff190000 0x100>;
340 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
341 reg-shift = <2>;
342 reg-io-width = <4>;
343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&uart1_xfer>;
347 status = "disabled";
348 };
349
350 uart2: serial@ff690000 {
351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg = <0xff690000 0x100>;
353 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
354 reg-shift = <2>;
355 reg-io-width = <4>;
356 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
357 clock-names = "baudclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart2_xfer>;
360 status = "disabled";
361 };
362
363 uart3: serial@ff1b0000 {
364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
365 reg = <0xff1b0000 0x100>;
366 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
367 reg-shift = <2>;
368 reg-io-width = <4>;
369 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
370 clock-names = "baudclk", "apb_pclk";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart3_xfer>;
373 status = "disabled";
374 };
375
376 uart4: serial@ff1c0000 {
377 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
378 reg = <0xff1c0000 0x100>;
379 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
380 reg-shift = <2>;
381 reg-io-width = <4>;
382 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
383 clock-names = "baudclk", "apb_pclk";
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart4_xfer>;
386 status = "disabled";
387 };
388
b67d6bc3
CW		 389 thermal-zones {
390 #include "rk3288-thermal.dtsi"
391 };
392
393 tsadc: tsadc@ff280000 {
394 compatible = "rockchip,rk3288-tsadc";
395 reg = <0xff280000 0x100>;
396 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
398 clock-names = "tsadc", "apb_pclk";
399 resets = <&cru SRST_TSADC>;
400 reset-names = "tsadc-apb";
401 pinctrl-names = "default";
402 pinctrl-0 = <&otp_out>;
403 #thermal-sensor-cells = <1>;
404 rockchip,hw-tshut-temp = <95000>;
405 status = "disabled";
406 };
407
3d3fb74a
RC		 408 gmac: ethernet@ff290000 {
409 compatible = "rockchip,rk3288-gmac";
410 reg = <0xff290000 0x10000>;
411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
412 interrupt-names = "macirq";
413 rockchip,grf = <&grf>;
414 clocks = <&cru SCLK_MAC>,
415 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
416 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
417 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
418 clock-names = "stmmaceth",
419 "mac_clk_rx", "mac_clk_tx",
420 "clk_mac_ref", "clk_mac_refout",
421 "aclk_mac", "pclk_mac";
54b0bc60 422 status = "disabled";
3d3fb74a
RC		 423 };
424
c9c32c50
DA		 425 usb_host0_ehci: usb@ff500000 {
426 compatible = "generic-ehci";
427 reg = <0xff500000 0x100>;
428 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru HCLK_USBHOST0>;
430 clock-names = "usbhost";
f6db7029
YL		 431 phys = <&usbphy1>;
432 phy-names = "usb";
c9c32c50
DA		 433 status = "disabled";
434 };
435
436 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
437
12dd3653
KY		 438 usb_host1: usb@ff540000 {
439 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
440 "snps,dwc2";
441 reg = <0xff540000 0x40000>;
442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cru HCLK_USBHOST1>;
444 clock-names = "otg";
f6db7029
YL		 445 phys = <&usbphy2>;
446 phy-names = "usb2-phy";
12dd3653
KY		 447 status = "disabled";
448 };
449
450 usb_otg: usb@ff580000 {
451 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
452 "snps,dwc2";
453 reg = <0xff580000 0x40000>;
454 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru HCLK_OTG0>;
456 clock-names = "otg";
f6db7029
YL		 457 phys = <&usbphy0>;
458 phy-names = "usb2-phy";
12dd3653
KY		 459 status = "disabled";
460 };
461
c9c32c50
DA		 462 usb_hsic: usb@ff5c0000 {
463 compatible = "generic-ehci";
464 reg = <0xff5c0000 0x100>;
465 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&cru HCLK_HSIC>;
467 clock-names = "usbhost";
468 status = "disabled";
469 };
470
2ab557b7
HS		 471 i2c0: i2c@ff650000 {
472 compatible = "rockchip,rk3288-i2c";
473 reg = <0xff650000 0x1000>;
474 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 clock-names = "i2c";
478 clocks = <&cru PCLK_I2C0>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&i2c0_xfer>;
481 status = "disabled";
482 };
483
484 i2c2: i2c@ff660000 {
485 compatible = "rockchip,rk3288-i2c";
486 reg = <0xff660000 0x1000>;
487 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 clock-names = "i2c";
491 clocks = <&cru PCLK_I2C2>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&i2c2_xfer>;
494 status = "disabled";
495 };
496
df542df3
DA		 497 pwm0: pwm@ff680000 {
498 compatible = "rockchip,rk3288-pwm";
499 reg = <0xff680000 0x10>;
500 #pwm-cells = <3>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&pwm0_pin>;
503 clocks = <&cru PCLK_PWM>;
504 clock-names = "pwm";
505 status = "disabled";
506 };
507
508 pwm1: pwm@ff680010 {
509 compatible = "rockchip,rk3288-pwm";
510 reg = <0xff680010 0x10>;
511 #pwm-cells = <3>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pwm1_pin>;
514 clocks = <&cru PCLK_PWM>;
515 clock-names = "pwm";
516 status = "disabled";
517 };
518
519 pwm2: pwm@ff680020 {
520 compatible = "rockchip,rk3288-pwm";
521 reg = <0xff680020 0x10>;
522 #pwm-cells = <3>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pwm2_pin>;
525 clocks = <&cru PCLK_PWM>;
526 clock-names = "pwm";
527 status = "disabled";
528 };
529
530 pwm3: pwm@ff680030 {
531 compatible = "rockchip,rk3288-pwm";
532 reg = <0xff680030 0x10>;
533 #pwm-cells = <2>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&pwm3_pin>;
536 clocks = <&cru PCLK_PWM>;
537 clock-names = "pwm";
538 status = "disabled";
539 };
540
1123d412
KY		 541 bus_intmem@ff700000 {
542 compatible = "mmio-sram";
543 reg = <0xff700000 0x18000>;
544 #address-cells = <1>;
545 #size-cells = <1>;
546 ranges = <0 0xff700000 0x18000>;
547 smp-sram@0 {
548 compatible = "rockchip,rk3066-smp-sram";
549 reg = <0x00 0x10>;
550 };
551 };
552
eecfe981
CZ		 553 sram@ff720000 {
554 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
555 reg = <0xff720000 0x1000>;
556 };
557
2ab557b7
HS		 558 pmu: power-management@ff730000 {
559 compatible = "rockchip,rk3288-pmu", "syscon";
560 reg = <0xff730000 0x100>;
561 };
562
563 sgrf: syscon@ff740000 {
564 compatible = "rockchip,rk3288-sgrf", "syscon";
565 reg = <0xff740000 0x1000>;
566 };
567
568 cru: clock-controller@ff760000 {
569 compatible = "rockchip,rk3288-cru";
570 reg = <0xff760000 0x1000>;
571 rockchip,grf = <&grf>;
572 #clock-cells = <1>;
573 #reset-cells = <1>;
cd78d0cd
KY		 574 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
575 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
576 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
577 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
578 <&cru PCLK_PERI>;
579 assigned-clock-rates = <594000000>, <400000000>,
580 <500000000>, <300000000>,
581 <150000000>, <75000000>,
582 <300000000>, <150000000>,
583 <75000000>;
2ab557b7
HS		 584 };
585
586 grf: syscon@ff770000 {
587 compatible = "rockchip,rk3288-grf", "syscon";
588 reg = <0xff770000 0x1000>;
589 };
590
591 wdt: watchdog@ff800000 {
592 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
593 reg = <0xff800000 0x100>;
39d05162 594 clocks = <&cru PCLK_WDT>;
2ab557b7
HS		 595 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
596 status = "disabled";
597 };
598
a0f95e35
J		 599 i2s: i2s@ff890000 {
600 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
601 reg = <0xff890000 0x10000>;
602 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
603 #address-cells = <1>;
604 #size-cells = <0>;
605 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
606 dma-names = "tx", "rx";
607 clock-names = "i2s_hclk", "i2s_clk";
608 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2s0_bus>;
611 status = "disabled";
612 };
613
a29cb8c4
DK		 614 vopb: vop@ff930000 {
615 compatible = "rockchip,rk3288-vop";
616 reg = <0xff930000 0x19c>;
617 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
619 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
620 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
621 reset-names = "axi", "ahb", "dclk";
622 iommus = <&vopb_mmu>;
623 status = "disabled";
624
625 vopb_out: port {
626 #address-cells = <1>;
627 #size-cells = <0>;
d5a1df48
AY		 628
629 vopb_out_hdmi: endpoint@0 {
630 reg = <0>;
631 remote-endpoint = <&hdmi_in_vopb>;
632 };
a29cb8c4
DK		 633 };
634 };
635
7cae068b
DK		 636 vopb_mmu: iommu@ff930300 {
637 compatible = "rockchip,iommu";
638 reg = <0xff930300 0x100>;
639 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
640 interrupt-names = "vopb_mmu";
641 #iommu-cells = <0>;
642 status = "disabled";
643 };
644
a29cb8c4
DK		 645 vopl: vop@ff940000 {
646 compatible = "rockchip,rk3288-vop";
647 reg = <0xff940000 0x19c>;
648 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
650 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
651 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
652 reset-names = "axi", "ahb", "dclk";
653 iommus = <&vopl_mmu>;
654 status = "disabled";
655
656 vopl_out: port {
657 #address-cells = <1>;
658 #size-cells = <0>;
d5a1df48
AY		 659
660 vopl_out_hdmi: endpoint@0 {
661 reg = <0>;
662 remote-endpoint = <&hdmi_in_vopl>;
663 };
a29cb8c4
DK		 664 };
665 };
666
7cae068b
DK		 667 vopl_mmu: iommu@ff940300 {
668 compatible = "rockchip,iommu";
669 reg = <0xff940300 0x100>;
670 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
671 interrupt-names = "vopl_mmu";
672 #iommu-cells = <0>;
673 status = "disabled";
674 };
675
d5a1df48
AY		 676 hdmi: hdmi@ff980000 {
677 compatible = "rockchip,rk3288-dw-hdmi";
678 reg = <0xff980000 0x20000>;
679 reg-io-width = <4>;
d5a1df48
AY		 680 rockchip,grf = <&grf>;
681 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
683 clock-names = "iahb", "isfr";
684 status = "disabled";
685
686 ports {
687 hdmi_in: port {
688 #address-cells = <1>;
689 #size-cells = <0>;
690 hdmi_in_vopb: endpoint@0 {
691 reg = <0>;
692 remote-endpoint = <&vopb_out_hdmi>;
693 };
694 hdmi_in_vopl: endpoint@1 {
695 reg = <1>;
696 remote-endpoint = <&vopl_out_hdmi>;
697 };
698 };
699 };
700 };
701
2ab557b7
HS		 702 gic: interrupt-controller@ffc01000 {
703 compatible = "arm,gic-400";
704 interrupt-controller;
705 #interrupt-cells = <3>;
706 #address-cells = <0>;
707
708 reg = <0xffc01000 0x1000>,
709 <0xffc02000 0x1000>,
710 <0xffc04000 0x2000>,
711 <0xffc06000 0x2000>;
712 interrupts = <GIC_PPI 9 0xf04>;
713 };
714
f6db7029
YL		 715 usbphy: phy {
716 compatible = "rockchip,rk3288-usb-phy";
717 rockchip,grf = <&grf>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 status = "disabled";
721
722 usbphy0: usb-phy0 {
723 #phy-cells = <0>;
724 reg = <0x320>;
725 clocks = <&cru SCLK_OTGPHY0>;
726 clock-names = "phyclk";
727 };
728
729 usbphy1: usb-phy1 {
730 #phy-cells = <0>;
731 reg = <0x334>;
732 clocks = <&cru SCLK_OTGPHY1>;
733 clock-names = "phyclk";
734 };
735
736 usbphy2: usb-phy2 {
737 #phy-cells = <0>;
738 reg = <0x348>;
739 clocks = <&cru SCLK_OTGPHY2>;
740 clock-names = "phyclk";
741 };
742 };
743
2ab557b7
HS		 744 pinctrl: pinctrl {
745 compatible = "rockchip,rk3288-pinctrl";
746 rockchip,grf = <&grf>;
747 rockchip,pmu = <&pmu>;
748 #address-cells = <1>;
749 #size-cells = <1>;
750 ranges;
751
752 gpio0: gpio0@ff750000 {
753 compatible = "rockchip,gpio-bank";
754 reg = <0xff750000 0x100>;
755 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&cru PCLK_GPIO0>;
757
758 gpio-controller;
759 #gpio-cells = <2>;
760
761 interrupt-controller;
762 #interrupt-cells = <2>;
763 };
764
765 gpio1: gpio1@ff780000 {
766 compatible = "rockchip,gpio-bank";
767 reg = <0xff780000 0x100>;
768 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&cru PCLK_GPIO1>;
770
771 gpio-controller;
772 #gpio-cells = <2>;
773
774 interrupt-controller;
775 #interrupt-cells = <2>;
776 };
777
778 gpio2: gpio2@ff790000 {
779 compatible = "rockchip,gpio-bank";
780 reg = <0xff790000 0x100>;
781 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru PCLK_GPIO2>;
783
784 gpio-controller;
785 #gpio-cells = <2>;
786
787 interrupt-controller;
788 #interrupt-cells = <2>;
789 };
790
791 gpio3: gpio3@ff7a0000 {
792 compatible = "rockchip,gpio-bank";
793 reg = <0xff7a0000 0x100>;
794 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&cru PCLK_GPIO3>;
796
797 gpio-controller;
798 #gpio-cells = <2>;
799
800 interrupt-controller;
801 #interrupt-cells = <2>;
802 };
803
804 gpio4: gpio4@ff7b0000 {
805 compatible = "rockchip,gpio-bank";
806 reg = <0xff7b0000 0x100>;
807 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&cru PCLK_GPIO4>;
809
810 gpio-controller;
811 #gpio-cells = <2>;
812
813 interrupt-controller;
814 #interrupt-cells = <2>;
815 };
816
817 gpio5: gpio5@ff7c0000 {
818 compatible = "rockchip,gpio-bank";
819 reg = <0xff7c0000 0x100>;
820 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cru PCLK_GPIO5>;
822
823 gpio-controller;
824 #gpio-cells = <2>;
825
826 interrupt-controller;
827 #interrupt-cells = <2>;
828 };
829
830 gpio6: gpio6@ff7d0000 {
831 compatible = "rockchip,gpio-bank";
832 reg = <0xff7d0000 0x100>;
833 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&cru PCLK_GPIO6>;
835
836 gpio-controller;
837 #gpio-cells = <2>;
838
839 interrupt-controller;
840 #interrupt-cells = <2>;
841 };
842
843 gpio7: gpio7@ff7e0000 {
844 compatible = "rockchip,gpio-bank";
845 reg = <0xff7e0000 0x100>;
846 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&cru PCLK_GPIO7>;
848
849 gpio-controller;
850 #gpio-cells = <2>;
851
852 interrupt-controller;
853 #interrupt-cells = <2>;
854 };
855
856 gpio8: gpio8@ff7f0000 {
857 compatible = "rockchip,gpio-bank";
858 reg = <0xff7f0000 0x100>;
859 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&cru PCLK_GPIO8>;
861
862 gpio-controller;
863 #gpio-cells = <2>;
864
865 interrupt-controller;
866 #interrupt-cells = <2>;
867 };
868
869 pcfg_pull_up: pcfg-pull-up {
870 bias-pull-up;
871 };
872
873 pcfg_pull_down: pcfg-pull-down {
874 bias-pull-down;
875 };
876
877 pcfg_pull_none: pcfg-pull-none {
878 bias-disable;
879 };
880
3d3fb74a
RC		 881 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
882 bias-disable;
883 drive-strength = <12>;
884 };
885
eecfe981
CZ		 886 sleep {
887 global_pwroff: global-pwroff {
888 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
889 };
890
891 ddrio_pwroff: ddrio-pwroff {
892 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
893 };
894
895 ddr0_retention: ddr0-retention {
896 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
897 };
898
899 ddr1_retention: ddr1-retention {
900 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
901 };
902 };
903
2ab557b7
HS		 904 i2c0 {
905 i2c0_xfer: i2c0-xfer {
906 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
907 <0 16 RK_FUNC_1 &pcfg_pull_none>;
908 };
909 };
910
911 i2c1 {
912 i2c1_xfer: i2c1-xfer {
913 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
914 <8 5 RK_FUNC_1 &pcfg_pull_none>;
915 };
916 };
917
918 i2c2 {
919 i2c2_xfer: i2c2-xfer {
920 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
921 <6 10 RK_FUNC_1 &pcfg_pull_none>;
922 };
923 };
924
925 i2c3 {
926 i2c3_xfer: i2c3-xfer {
927 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
928 <2 17 RK_FUNC_1 &pcfg_pull_none>;
929 };
930 };
931
932 i2c4 {
933 i2c4_xfer: i2c4-xfer {
934 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
935 <7 18 RK_FUNC_1 &pcfg_pull_none>;
936 };
937 };
938
939 i2c5 {
940 i2c5_xfer: i2c5-xfer {
941 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
942 <7 20 RK_FUNC_1 &pcfg_pull_none>;
a0f95e35
J		 943 };
944 };
945
946 i2s0 {
947 i2s0_bus: i2s0-bus {
948 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
949 <6 1 RK_FUNC_1 &pcfg_pull_none>,
950 <6 2 RK_FUNC_1 &pcfg_pull_none>,
951 <6 3 RK_FUNC_1 &pcfg_pull_none>,
952 <6 4 RK_FUNC_1 &pcfg_pull_none>,
953 <6 8 RK_FUNC_1 &pcfg_pull_none>;
2ab557b7
HS		 954 };
955 };
956
957 sdmmc {
958 sdmmc_clk: sdmmc-clk {
959 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
960 };
961
962 sdmmc_cmd: sdmmc-cmd {
963 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
964 };
965
966 sdmmc_cd: sdmcc-cd {
967 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
968 };
969
970 sdmmc_bus1: sdmmc-bus1 {
971 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
972 };
973
974 sdmmc_bus4: sdmmc-bus4 {
975 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
976 <6 17 RK_FUNC_1 &pcfg_pull_up>,
977 <6 18 RK_FUNC_1 &pcfg_pull_up>,
978 <6 19 RK_FUNC_1 &pcfg_pull_up>;
979 };
980 };
981
f1a07231
AK		 982 sdio0 {
983 sdio0_bus1: sdio0-bus1 {
984 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
985 };
986
987 sdio0_bus4: sdio0-bus4 {
988 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
989 <4 21 RK_FUNC_1 &pcfg_pull_up>,
990 <4 22 RK_FUNC_1 &pcfg_pull_up>,
991 <4 23 RK_FUNC_1 &pcfg_pull_up>;
992 };
993
994 sdio0_cmd: sdio0-cmd {
995 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
996 };
997
998 sdio0_clk: sdio0-clk {
999 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1000 };
1001
1002 sdio0_cd: sdio0-cd {
1003 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1004 };
1005
1006 sdio0_wp: sdio0-wp {
1007 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1008 };
1009
1010 sdio0_pwr: sdio0-pwr {
1011 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1012 };
1013
1014 sdio0_bkpwr: sdio0-bkpwr {
1015 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1016 };
1017
1018 sdio0_int: sdio0-int {
1019 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1020 };
1021 };
1022
1023 sdio1 {
1024 sdio1_bus1: sdio1-bus1 {
1025 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1026 };
1027
1028 sdio1_bus4: sdio1-bus4 {
1029 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1030 <3 25 4 &pcfg_pull_up>,
1031 <3 26 4 &pcfg_pull_up>,
1032 <3 27 4 &pcfg_pull_up>;
1033 };
1034
1035 sdio1_cd: sdio1-cd {
1036 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1037 };
1038
1039 sdio1_wp: sdio1-wp {
1040 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1041 };
1042
1043 sdio1_bkpwr: sdio1-bkpwr {
1044 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1045 };
1046
1047 sdio1_int: sdio1-int {
1048 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1049 };
1050
1051 sdio1_cmd: sdio1-cmd {
1052 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1053 };
1054
1055 sdio1_clk: sdio1-clk {
1056 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1057 };
1058
1059 sdio1_pwr: sdio1-pwr {
1060 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1061 };
1062 };
1063
2ab557b7
HS		 1064 emmc {
1065 emmc_clk: emmc-clk {
1066 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1067 };
1068
1069 emmc_cmd: emmc-cmd {
1070 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1071 };
1072
1073 emmc_pwr: emmc-pwr {
1074 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1075 };
1076
1077 emmc_bus1: emmc-bus1 {
1078 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1079 };
1080
1081 emmc_bus4: emmc-bus4 {
1082 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1083 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1084 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1085 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1086 };
1087
1088 emmc_bus8: emmc-bus8 {
1089 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1090 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1091 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1092 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1093 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1094 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1095 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1096 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1097 };
1098 };
1099
1f53170b 1100 spi0 {
1101 spi0_clk: spi0-clk {
1102 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1103 };
1104 spi0_cs0: spi0-cs0 {
1105 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1106 };
1107 spi0_tx: spi0-tx {
1108 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1109 };
1110 spi0_rx: spi0-rx {
1111 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1112 };
1113 spi0_cs1: spi0-cs1 {
1114 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1115 };
1116 };
1117 spi1 {
1118 spi1_clk: spi1-clk {
1119 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1120 };
1121 spi1_cs0: spi1-cs0 {
1122 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1123 };
1124 spi1_rx: spi1-rx {
1125 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1126 };
1127 spi1_tx: spi1-tx {
1128 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1129 };
1130 };
1131
1132 spi2 {
1133 spi2_cs1: spi2-cs1 {
1134 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1135 };
1136 spi2_clk: spi2-clk {
1137 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1138 };
1139 spi2_cs0: spi2-cs0 {
1140 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1141 };
1142 spi2_rx: spi2-rx {
1143 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1144 };
1145 spi2_tx: spi2-tx {
1146 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1147 };
1148 };
1149
2ab557b7
HS		 1150 uart0 {
1151 uart0_xfer: uart0-xfer {
1152 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1153 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1154 };
1155
1156 uart0_cts: uart0-cts {
1157 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1158 };
1159
1160 uart0_rts: uart0-rts {
1161 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1162 };
1163 };
1164
1165 uart1 {
1166 uart1_xfer: uart1-xfer {
1167 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1168 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1169 };
1170
1171 uart1_cts: uart1-cts {
1172 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1173 };
1174
1175 uart1_rts: uart1-rts {
1176 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1177 };
1178 };
1179
1180 uart2 {
1181 uart2_xfer: uart2-xfer {
1182 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1183 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1184 };
1185 /* no rts / cts for uart2 */
1186 };
1187
1188 uart3 {
1189 uart3_xfer: uart3-xfer {
1190 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1191 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1192 };
1193
1194 uart3_cts: uart3-cts {
1195 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1196 };
1197
1198 uart3_rts: uart3-rts {
1199 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1200 };
1201 };
1202
1203 uart4 {
1204 uart4_xfer: uart4-xfer {
1205 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1206 <5 13 3 &pcfg_pull_none>;
1207 };
1208
1209 uart4_cts: uart4-cts {
1210 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1211 };
1212
1213 uart4_rts: uart4-rts {
1214 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1215 };
1216 };
df542df3 1217
b67d6bc3
CW		 1218 tsadc {
1219 otp_out: otp-out {
1220 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1221 };
1222 };
1223
df542df3
DA		 1224 pwm0 {
1225 pwm0_pin: pwm0-pin {
1226 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1227 };
1228 };
1229
1230 pwm1 {
1231 pwm1_pin: pwm1-pin {
1232 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1233 };
1234 };
1235
1236 pwm2 {
1237 pwm2_pin: pwm2-pin {
1238 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1239 };
1240 };
1241
1242 pwm3 {
1243 pwm3_pin: pwm3-pin {
1244 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1245 };
1246 };
3d3fb74a
RC		 1247
1248 gmac {
1249 rgmii_pins: rgmii-pins {
1250 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1251 <3 31 3 &pcfg_pull_none>,
1252 <3 26 3 &pcfg_pull_none>,
1253 <3 27 3 &pcfg_pull_none>,
1254 <3 28 3 &pcfg_pull_none_12ma>,
1255 <3 29 3 &pcfg_pull_none_12ma>,
1256 <3 24 3 &pcfg_pull_none_12ma>,
1257 <3 25 3 &pcfg_pull_none_12ma>,
1258 <4 0 3 &pcfg_pull_none>,
1259 <4 5 3 &pcfg_pull_none>,
1260 <4 6 3 &pcfg_pull_none>,
1261 <4 9 3 &pcfg_pull_none_12ma>,
1262 <4 4 3 &pcfg_pull_none_12ma>,
1263 <4 1 3 &pcfg_pull_none>,
1264 <4 3 3 &pcfg_pull_none>;
1265 };
1266
1267 rmii_pins: rmii-pins {
1268 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1269 <3 31 3 &pcfg_pull_none>,
1270 <3 28 3 &pcfg_pull_none>,
1271 <3 29 3 &pcfg_pull_none>,
1272 <4 0 3 &pcfg_pull_none>,
1273 <4 5 3 &pcfg_pull_none>,
1274 <4 4 3 &pcfg_pull_none>,
1275 <4 1 3 &pcfg_pull_none>,
1276 <4 2 3 &pcfg_pull_none>,
1277 <4 3 3 &pcfg_pull_none>;
1278 };
1279 };
2ab557b7
HS		 1280 };
1281};
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