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ARM: dts: rockchip: add rk3288 hdmi nodes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
b67d6bc3 18#include <dt-bindings/thermal/thermal.h>
2ab557b7
HS		 19#include "skeleton.dtsi"
20
21/ {
22 compatible = "rockchip,rk3288";
23
24 interrupt-parent = <&gic>;
25
26 aliases {
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
d7f9a388
DA		 33 mshc0 = &emmc;
34 mshc1 = &sdmmc;
35 mshc2 = &sdio0;
36 mshc3 = &sdio1;
2ab557b7
HS		 37 serial0 = &uart0;
38 serial1 = &uart1;
39 serial2 = &uart2;
40 serial3 = &uart3;
41 serial4 = &uart4;
1f53170b 42 spi0 = &spi0;
43 spi1 = &spi1;
44 spi2 = &spi2;
2ab557b7
HS		 45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
08bcc754 50 enable-method = "rockchip,rk3066-smp";
fbdbc732 51 rockchip,pmu = <&pmu>;
2ab557b7 52
be8a77c5 53 cpu0: cpu@500 {
2ab557b7
HS		 54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x500>;
044542af 57 resets = <&cru SRST_CORE0>;
be8a77c5
HS		 58 operating-points = <
59 /* KHz uV */
60 1608000 1350000
61 1512000 1300000
62 1416000 1200000
63 1200000 1100000
64 1008000 1050000
65 816000 1000000
66 696000 950000
67 600000 900000
68 408000 900000
69 312000 900000
70 216000 900000
71 126000 900000
72 >;
b67d6bc3 73 #cooling-cells = <2>; /* min followed by max */
be8a77c5
HS		 74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
2ab557b7
HS		 76 };
77 cpu@501 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a12";
80 reg = <0x501>;
044542af 81 resets = <&cru SRST_CORE1>;
2ab557b7
HS		 82 };
83 cpu@502 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x502>;
044542af 87 resets = <&cru SRST_CORE2>;
2ab557b7
HS		 88 };
89 cpu@503 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x503>;
044542af 93 resets = <&cru SRST_CORE3>;
2ab557b7
HS		 94 };
95 };
96
982891c3
HS		 97 amba {
98 compatible = "arm,amba-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges;
102
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
108 #dma-cells = <1>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
111 };
112
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
118 #dma-cells = <1>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
121 status = "disabled";
122 };
123
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
129 #dma-cells = <1>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
132 };
133 };
134
2ab557b7
HS		 135 xin24m: oscillator {
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
139 #clock-cells = <0>;
140 };
141
142 timer {
143 compatible = "arm,armv7-timer";
e2405a59 144 arm,cpu-registers-not-fw-configured;
2ab557b7
HS		 145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
150 };
151
a29cb8c4
DK		 152 display-subsystem {
153 compatible = "rockchip,display-subsystem";
154 ports = <&vopl_out>, <&vopb_out>;
155 };
156
85095bf3
DA		 157 sdmmc: dwmmc@ff0c0000 {
158 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 159 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 160 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
161 clock-names = "biu", "ciu";
162 fifo-depth = <0x100>;
163 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
164 reg = <0xff0c0000 0x4000>;
165 status = "disabled";
166 };
167
f1a07231
AK		 168 sdio0: dwmmc@ff0d0000 {
169 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 170 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 171 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
172 clock-names = "biu", "ciu";
173 fifo-depth = <0x100>;
174 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
175 reg = <0xff0d0000 0x4000>;
176 status = "disabled";
177 };
178
179 sdio1: dwmmc@ff0e0000 {
180 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 181 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 182 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
183 clock-names = "biu", "ciu";
184 fifo-depth = <0x100>;
185 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
186 reg = <0xff0e0000 0x4000>;
187 status = "disabled";
188 };
189
85095bf3
DA		 190 emmc: dwmmc@ff0f0000 {
191 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 192 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 193 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
194 clock-names = "biu", "ciu";
195 fifo-depth = <0x100>;
196 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
197 reg = <0xff0f0000 0x4000>;
198 status = "disabled";
199 };
200
f23a6179
HS		 201 saradc: saradc@ff100000 {
202 compatible = "rockchip,saradc";
203 reg = <0xff100000 0x100>;
204 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
205 #io-channel-cells = <1>;
206 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
207 clock-names = "saradc", "apb_pclk";
208 status = "disabled";
209 };
210
1f53170b 211 spi0: spi@ff110000 {
212 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
213 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
214 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 215 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
216 dma-names = "tx", "rx";
1f53170b 217 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
220 reg = <0xff110000 0x1000>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 status = "disabled";
224 };
225
226 spi1: spi@ff120000 {
227 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
228 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
229 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 230 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
231 dma-names = "tx", "rx";
1f53170b 232 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
235 reg = <0xff120000 0x1000>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 status = "disabled";
239 };
240
241 spi2: spi@ff130000 {
242 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
243 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
244 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 245 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
246 dma-names = "tx", "rx";
1f53170b 247 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
250 reg = <0xff130000 0x1000>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 status = "disabled";
254 };
255
2ab557b7
HS		 256 i2c1: i2c@ff140000 {
257 compatible = "rockchip,rk3288-i2c";
258 reg = <0xff140000 0x1000>;
259 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 clock-names = "i2c";
263 clocks = <&cru PCLK_I2C1>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&i2c1_xfer>;
266 status = "disabled";
267 };
268
269 i2c3: i2c@ff150000 {
270 compatible = "rockchip,rk3288-i2c";
271 reg = <0xff150000 0x1000>;
272 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clock-names = "i2c";
276 clocks = <&cru PCLK_I2C3>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c3_xfer>;
279 status = "disabled";
280 };
281
282 i2c4: i2c@ff160000 {
283 compatible = "rockchip,rk3288-i2c";
284 reg = <0xff160000 0x1000>;
285 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 clock-names = "i2c";
289 clocks = <&cru PCLK_I2C4>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c4_xfer>;
292 status = "disabled";
293 };
294
295 i2c5: i2c@ff170000 {
296 compatible = "rockchip,rk3288-i2c";
297 reg = <0xff170000 0x1000>;
298 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clock-names = "i2c";
302 clocks = <&cru PCLK_I2C5>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c5_xfer>;
305 status = "disabled";
306 };
307
308 uart0: serial@ff180000 {
309 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
310 reg = <0xff180000 0x100>;
311 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
312 reg-shift = <2>;
313 reg-io-width = <4>;
314 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
315 clock-names = "baudclk", "apb_pclk";
316 pinctrl-names = "default";
317 pinctrl-0 = <&uart0_xfer>;
318 status = "disabled";
319 };
320
321 uart1: serial@ff190000 {
322 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
323 reg = <0xff190000 0x100>;
324 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
325 reg-shift = <2>;
326 reg-io-width = <4>;
327 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
328 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart1_xfer>;
331 status = "disabled";
332 };
333
334 uart2: serial@ff690000 {
335 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
336 reg = <0xff690000 0x100>;
337 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
338 reg-shift = <2>;
339 reg-io-width = <4>;
340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
341 clock-names = "baudclk", "apb_pclk";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart2_xfer>;
344 status = "disabled";
345 };
346
347 uart3: serial@ff1b0000 {
348 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
349 reg = <0xff1b0000 0x100>;
350 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
351 reg-shift = <2>;
352 reg-io-width = <4>;
353 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
354 clock-names = "baudclk", "apb_pclk";
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart3_xfer>;
357 status = "disabled";
358 };
359
360 uart4: serial@ff1c0000 {
361 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
362 reg = <0xff1c0000 0x100>;
363 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
364 reg-shift = <2>;
365 reg-io-width = <4>;
366 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
367 clock-names = "baudclk", "apb_pclk";
368 pinctrl-names = "default";
369 pinctrl-0 = <&uart4_xfer>;
370 status = "disabled";
371 };
372
b67d6bc3
CW		 373 thermal-zones {
374 #include "rk3288-thermal.dtsi"
375 };
376
377 tsadc: tsadc@ff280000 {
378 compatible = "rockchip,rk3288-tsadc";
379 reg = <0xff280000 0x100>;
380 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
382 clock-names = "tsadc", "apb_pclk";
383 resets = <&cru SRST_TSADC>;
384 reset-names = "tsadc-apb";
385 pinctrl-names = "default";
386 pinctrl-0 = <&otp_out>;
387 #thermal-sensor-cells = <1>;
388 rockchip,hw-tshut-temp = <95000>;
389 status = "disabled";
390 };
391
c9c32c50
DA		 392 usb_host0_ehci: usb@ff500000 {
393 compatible = "generic-ehci";
394 reg = <0xff500000 0x100>;
395 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru HCLK_USBHOST0>;
397 clock-names = "usbhost";
398 status = "disabled";
399 };
400
401 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
402
12dd3653
KY		 403 usb_host1: usb@ff540000 {
404 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
405 "snps,dwc2";
406 reg = <0xff540000 0x40000>;
407 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&cru HCLK_USBHOST1>;
409 clock-names = "otg";
410 status = "disabled";
411 };
412
413 usb_otg: usb@ff580000 {
414 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
415 "snps,dwc2";
416 reg = <0xff580000 0x40000>;
417 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru HCLK_OTG0>;
419 clock-names = "otg";
420 status = "disabled";
421 };
422
c9c32c50
DA		 423 usb_hsic: usb@ff5c0000 {
424 compatible = "generic-ehci";
425 reg = <0xff5c0000 0x100>;
426 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cru HCLK_HSIC>;
428 clock-names = "usbhost";
429 status = "disabled";
430 };
431
2ab557b7
HS		 432 i2c0: i2c@ff650000 {
433 compatible = "rockchip,rk3288-i2c";
434 reg = <0xff650000 0x1000>;
435 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438 clock-names = "i2c";
439 clocks = <&cru PCLK_I2C0>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c0_xfer>;
442 status = "disabled";
443 };
444
445 i2c2: i2c@ff660000 {
446 compatible = "rockchip,rk3288-i2c";
447 reg = <0xff660000 0x1000>;
448 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 clock-names = "i2c";
452 clocks = <&cru PCLK_I2C2>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c2_xfer>;
455 status = "disabled";
456 };
457
df542df3
DA		 458 pwm0: pwm@ff680000 {
459 compatible = "rockchip,rk3288-pwm";
460 reg = <0xff680000 0x10>;
461 #pwm-cells = <3>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pwm0_pin>;
464 clocks = <&cru PCLK_PWM>;
465 clock-names = "pwm";
466 status = "disabled";
467 };
468
469 pwm1: pwm@ff680010 {
470 compatible = "rockchip,rk3288-pwm";
471 reg = <0xff680010 0x10>;
472 #pwm-cells = <3>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&pwm1_pin>;
475 clocks = <&cru PCLK_PWM>;
476 clock-names = "pwm";
477 status = "disabled";
478 };
479
480 pwm2: pwm@ff680020 {
481 compatible = "rockchip,rk3288-pwm";
482 reg = <0xff680020 0x10>;
483 #pwm-cells = <3>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&pwm2_pin>;
486 clocks = <&cru PCLK_PWM>;
487 clock-names = "pwm";
488 status = "disabled";
489 };
490
491 pwm3: pwm@ff680030 {
492 compatible = "rockchip,rk3288-pwm";
493 reg = <0xff680030 0x10>;
494 #pwm-cells = <2>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pwm3_pin>;
497 clocks = <&cru PCLK_PWM>;
498 clock-names = "pwm";
499 status = "disabled";
500 };
501
1123d412
KY		 502 bus_intmem@ff700000 {
503 compatible = "mmio-sram";
504 reg = <0xff700000 0x18000>;
505 #address-cells = <1>;
506 #size-cells = <1>;
507 ranges = <0 0xff700000 0x18000>;
508 smp-sram@0 {
509 compatible = "rockchip,rk3066-smp-sram";
510 reg = <0x00 0x10>;
511 };
512 };
513
eecfe981
CZ		 514 sram@ff720000 {
515 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
516 reg = <0xff720000 0x1000>;
517 };
518
2ab557b7
HS		 519 pmu: power-management@ff730000 {
520 compatible = "rockchip,rk3288-pmu", "syscon";
521 reg = <0xff730000 0x100>;
522 };
523
524 sgrf: syscon@ff740000 {
525 compatible = "rockchip,rk3288-sgrf", "syscon";
526 reg = <0xff740000 0x1000>;
527 };
528
529 cru: clock-controller@ff760000 {
530 compatible = "rockchip,rk3288-cru";
531 reg = <0xff760000 0x1000>;
532 rockchip,grf = <&grf>;
533 #clock-cells = <1>;
534 #reset-cells = <1>;
cd78d0cd
KY		 535 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
536 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
537 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
538 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
539 <&cru PCLK_PERI>;
540 assigned-clock-rates = <594000000>, <400000000>,
541 <500000000>, <300000000>,
542 <150000000>, <75000000>,
543 <300000000>, <150000000>,
544 <75000000>;
2ab557b7
HS		 545 };
546
547 grf: syscon@ff770000 {
548 compatible = "rockchip,rk3288-grf", "syscon";
549 reg = <0xff770000 0x1000>;
550 };
551
552 wdt: watchdog@ff800000 {
553 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
554 reg = <0xff800000 0x100>;
555 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
556 status = "disabled";
557 };
558
a0f95e35
J		 559 i2s: i2s@ff890000 {
560 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
561 reg = <0xff890000 0x10000>;
562 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
566 dma-names = "tx", "rx";
567 clock-names = "i2s_hclk", "i2s_clk";
568 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2s0_bus>;
571 status = "disabled";
572 };
573
a29cb8c4
DK		 574 vopb: vop@ff930000 {
575 compatible = "rockchip,rk3288-vop";
576 reg = <0xff930000 0x19c>;
577 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
579 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
580 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
581 reset-names = "axi", "ahb", "dclk";
582 iommus = <&vopb_mmu>;
583 status = "disabled";
584
585 vopb_out: port {
586 #address-cells = <1>;
587 #size-cells = <0>;
d5a1df48
AY		 588
589 vopb_out_hdmi: endpoint@0 {
590 reg = <0>;
591 remote-endpoint = <&hdmi_in_vopb>;
592 };
a29cb8c4
DK		 593 };
594 };
595
7cae068b
DK		 596 vopb_mmu: iommu@ff930300 {
597 compatible = "rockchip,iommu";
598 reg = <0xff930300 0x100>;
599 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-names = "vopb_mmu";
601 #iommu-cells = <0>;
602 status = "disabled";
603 };
604
a29cb8c4
DK		 605 vopl: vop@ff940000 {
606 compatible = "rockchip,rk3288-vop";
607 reg = <0xff940000 0x19c>;
608 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
610 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
611 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
612 reset-names = "axi", "ahb", "dclk";
613 iommus = <&vopl_mmu>;
614 status = "disabled";
615
616 vopl_out: port {
617 #address-cells = <1>;
618 #size-cells = <0>;
d5a1df48
AY		 619
620 vopl_out_hdmi: endpoint@0 {
621 reg = <0>;
622 remote-endpoint = <&hdmi_in_vopl>;
623 };
a29cb8c4
DK		 624 };
625 };
626
7cae068b
DK		 627 vopl_mmu: iommu@ff940300 {
628 compatible = "rockchip,iommu";
629 reg = <0xff940300 0x100>;
630 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
631 interrupt-names = "vopl_mmu";
632 #iommu-cells = <0>;
633 status = "disabled";
634 };
635
d5a1df48
AY		 636 hdmi: hdmi@ff980000 {
637 compatible = "rockchip,rk3288-dw-hdmi";
638 reg = <0xff980000 0x20000>;
639 reg-io-width = <4>;
640 ddc-i2c-bus = <&i2c5>;
641 rockchip,grf = <&grf>;
642 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
644 clock-names = "iahb", "isfr";
645 status = "disabled";
646
647 ports {
648 hdmi_in: port {
649 #address-cells = <1>;
650 #size-cells = <0>;
651 hdmi_in_vopb: endpoint@0 {
652 reg = <0>;
653 remote-endpoint = <&vopb_out_hdmi>;
654 };
655 hdmi_in_vopl: endpoint@1 {
656 reg = <1>;
657 remote-endpoint = <&vopl_out_hdmi>;
658 };
659 };
660 };
661 };
662
2ab557b7
HS		 663 gic: interrupt-controller@ffc01000 {
664 compatible = "arm,gic-400";
665 interrupt-controller;
666 #interrupt-cells = <3>;
667 #address-cells = <0>;
668
669 reg = <0xffc01000 0x1000>,
670 <0xffc02000 0x1000>,
671 <0xffc04000 0x2000>,
672 <0xffc06000 0x2000>;
673 interrupts = <GIC_PPI 9 0xf04>;
674 };
675
676 pinctrl: pinctrl {
677 compatible = "rockchip,rk3288-pinctrl";
678 rockchip,grf = <&grf>;
679 rockchip,pmu = <&pmu>;
680 #address-cells = <1>;
681 #size-cells = <1>;
682 ranges;
683
684 gpio0: gpio0@ff750000 {
685 compatible = "rockchip,gpio-bank";
686 reg = <0xff750000 0x100>;
687 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cru PCLK_GPIO0>;
689
690 gpio-controller;
691 #gpio-cells = <2>;
692
693 interrupt-controller;
694 #interrupt-cells = <2>;
695 };
696
697 gpio1: gpio1@ff780000 {
698 compatible = "rockchip,gpio-bank";
699 reg = <0xff780000 0x100>;
700 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&cru PCLK_GPIO1>;
702
703 gpio-controller;
704 #gpio-cells = <2>;
705
706 interrupt-controller;
707 #interrupt-cells = <2>;
708 };
709
710 gpio2: gpio2@ff790000 {
711 compatible = "rockchip,gpio-bank";
712 reg = <0xff790000 0x100>;
713 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cru PCLK_GPIO2>;
715
716 gpio-controller;
717 #gpio-cells = <2>;
718
719 interrupt-controller;
720 #interrupt-cells = <2>;
721 };
722
723 gpio3: gpio3@ff7a0000 {
724 compatible = "rockchip,gpio-bank";
725 reg = <0xff7a0000 0x100>;
726 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&cru PCLK_GPIO3>;
728
729 gpio-controller;
730 #gpio-cells = <2>;
731
732 interrupt-controller;
733 #interrupt-cells = <2>;
734 };
735
736 gpio4: gpio4@ff7b0000 {
737 compatible = "rockchip,gpio-bank";
738 reg = <0xff7b0000 0x100>;
739 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&cru PCLK_GPIO4>;
741
742 gpio-controller;
743 #gpio-cells = <2>;
744
745 interrupt-controller;
746 #interrupt-cells = <2>;
747 };
748
749 gpio5: gpio5@ff7c0000 {
750 compatible = "rockchip,gpio-bank";
751 reg = <0xff7c0000 0x100>;
752 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cru PCLK_GPIO5>;
754
755 gpio-controller;
756 #gpio-cells = <2>;
757
758 interrupt-controller;
759 #interrupt-cells = <2>;
760 };
761
762 gpio6: gpio6@ff7d0000 {
763 compatible = "rockchip,gpio-bank";
764 reg = <0xff7d0000 0x100>;
765 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&cru PCLK_GPIO6>;
767
768 gpio-controller;
769 #gpio-cells = <2>;
770
771 interrupt-controller;
772 #interrupt-cells = <2>;
773 };
774
775 gpio7: gpio7@ff7e0000 {
776 compatible = "rockchip,gpio-bank";
777 reg = <0xff7e0000 0x100>;
778 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&cru PCLK_GPIO7>;
780
781 gpio-controller;
782 #gpio-cells = <2>;
783
784 interrupt-controller;
785 #interrupt-cells = <2>;
786 };
787
788 gpio8: gpio8@ff7f0000 {
789 compatible = "rockchip,gpio-bank";
790 reg = <0xff7f0000 0x100>;
791 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&cru PCLK_GPIO8>;
793
794 gpio-controller;
795 #gpio-cells = <2>;
796
797 interrupt-controller;
798 #interrupt-cells = <2>;
799 };
800
801 pcfg_pull_up: pcfg-pull-up {
802 bias-pull-up;
803 };
804
805 pcfg_pull_down: pcfg-pull-down {
806 bias-pull-down;
807 };
808
809 pcfg_pull_none: pcfg-pull-none {
810 bias-disable;
811 };
812
eecfe981
CZ		 813 sleep {
814 global_pwroff: global-pwroff {
815 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
816 };
817
818 ddrio_pwroff: ddrio-pwroff {
819 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
820 };
821
822 ddr0_retention: ddr0-retention {
823 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
824 };
825
826 ddr1_retention: ddr1-retention {
827 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
828 };
829 };
830
2ab557b7
HS		 831 i2c0 {
832 i2c0_xfer: i2c0-xfer {
833 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
834 <0 16 RK_FUNC_1 &pcfg_pull_none>;
835 };
836 };
837
838 i2c1 {
839 i2c1_xfer: i2c1-xfer {
840 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
841 <8 5 RK_FUNC_1 &pcfg_pull_none>;
842 };
843 };
844
845 i2c2 {
846 i2c2_xfer: i2c2-xfer {
847 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
848 <6 10 RK_FUNC_1 &pcfg_pull_none>;
849 };
850 };
851
852 i2c3 {
853 i2c3_xfer: i2c3-xfer {
854 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
855 <2 17 RK_FUNC_1 &pcfg_pull_none>;
856 };
857 };
858
859 i2c4 {
860 i2c4_xfer: i2c4-xfer {
861 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
862 <7 18 RK_FUNC_1 &pcfg_pull_none>;
863 };
864 };
865
866 i2c5 {
867 i2c5_xfer: i2c5-xfer {
868 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
869 <7 20 RK_FUNC_1 &pcfg_pull_none>;
a0f95e35
J		 870 };
871 };
872
873 i2s0 {
874 i2s0_bus: i2s0-bus {
875 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
876 <6 1 RK_FUNC_1 &pcfg_pull_none>,
877 <6 2 RK_FUNC_1 &pcfg_pull_none>,
878 <6 3 RK_FUNC_1 &pcfg_pull_none>,
879 <6 4 RK_FUNC_1 &pcfg_pull_none>,
880 <6 8 RK_FUNC_1 &pcfg_pull_none>;
2ab557b7
HS		 881 };
882 };
883
884 sdmmc {
885 sdmmc_clk: sdmmc-clk {
886 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
887 };
888
889 sdmmc_cmd: sdmmc-cmd {
890 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
891 };
892
893 sdmmc_cd: sdmcc-cd {
894 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
895 };
896
897 sdmmc_bus1: sdmmc-bus1 {
898 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
899 };
900
901 sdmmc_bus4: sdmmc-bus4 {
902 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
903 <6 17 RK_FUNC_1 &pcfg_pull_up>,
904 <6 18 RK_FUNC_1 &pcfg_pull_up>,
905 <6 19 RK_FUNC_1 &pcfg_pull_up>;
906 };
907 };
908
f1a07231
AK		 909 sdio0 {
910 sdio0_bus1: sdio0-bus1 {
911 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
912 };
913
914 sdio0_bus4: sdio0-bus4 {
915 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
916 <4 21 RK_FUNC_1 &pcfg_pull_up>,
917 <4 22 RK_FUNC_1 &pcfg_pull_up>,
918 <4 23 RK_FUNC_1 &pcfg_pull_up>;
919 };
920
921 sdio0_cmd: sdio0-cmd {
922 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
923 };
924
925 sdio0_clk: sdio0-clk {
926 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
927 };
928
929 sdio0_cd: sdio0-cd {
930 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
931 };
932
933 sdio0_wp: sdio0-wp {
934 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
935 };
936
937 sdio0_pwr: sdio0-pwr {
938 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
939 };
940
941 sdio0_bkpwr: sdio0-bkpwr {
942 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
943 };
944
945 sdio0_int: sdio0-int {
946 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
947 };
948 };
949
950 sdio1 {
951 sdio1_bus1: sdio1-bus1 {
952 rockchip,pins = <3 24 4 &pcfg_pull_up>;
953 };
954
955 sdio1_bus4: sdio1-bus4 {
956 rockchip,pins = <3 24 4 &pcfg_pull_up>,
957 <3 25 4 &pcfg_pull_up>,
958 <3 26 4 &pcfg_pull_up>,
959 <3 27 4 &pcfg_pull_up>;
960 };
961
962 sdio1_cd: sdio1-cd {
963 rockchip,pins = <3 28 4 &pcfg_pull_up>;
964 };
965
966 sdio1_wp: sdio1-wp {
967 rockchip,pins = <3 29 4 &pcfg_pull_up>;
968 };
969
970 sdio1_bkpwr: sdio1-bkpwr {
971 rockchip,pins = <3 30 4 &pcfg_pull_up>;
972 };
973
974 sdio1_int: sdio1-int {
975 rockchip,pins = <3 31 4 &pcfg_pull_up>;
976 };
977
978 sdio1_cmd: sdio1-cmd {
979 rockchip,pins = <4 6 4 &pcfg_pull_up>;
980 };
981
982 sdio1_clk: sdio1-clk {
983 rockchip,pins = <4 7 4 &pcfg_pull_none>;
984 };
985
986 sdio1_pwr: sdio1-pwr {
987 rockchip,pins = <4 9 4 &pcfg_pull_up>;
988 };
989 };
990
2ab557b7
HS		 991 emmc {
992 emmc_clk: emmc-clk {
993 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
994 };
995
996 emmc_cmd: emmc-cmd {
997 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
998 };
999
1000 emmc_pwr: emmc-pwr {
1001 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1002 };
1003
1004 emmc_bus1: emmc-bus1 {
1005 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1006 };
1007
1008 emmc_bus4: emmc-bus4 {
1009 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1010 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1011 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1012 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1013 };
1014
1015 emmc_bus8: emmc-bus8 {
1016 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1017 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1018 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1019 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1020 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1021 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1022 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1023 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1024 };
1025 };
1026
1f53170b 1027 spi0 {
1028 spi0_clk: spi0-clk {
1029 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1030 };
1031 spi0_cs0: spi0-cs0 {
1032 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1033 };
1034 spi0_tx: spi0-tx {
1035 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1036 };
1037 spi0_rx: spi0-rx {
1038 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1039 };
1040 spi0_cs1: spi0-cs1 {
1041 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1042 };
1043 };
1044 spi1 {
1045 spi1_clk: spi1-clk {
1046 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1047 };
1048 spi1_cs0: spi1-cs0 {
1049 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1050 };
1051 spi1_rx: spi1-rx {
1052 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1053 };
1054 spi1_tx: spi1-tx {
1055 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1056 };
1057 };
1058
1059 spi2 {
1060 spi2_cs1: spi2-cs1 {
1061 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1062 };
1063 spi2_clk: spi2-clk {
1064 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1065 };
1066 spi2_cs0: spi2-cs0 {
1067 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1068 };
1069 spi2_rx: spi2-rx {
1070 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1071 };
1072 spi2_tx: spi2-tx {
1073 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1074 };
1075 };
1076
2ab557b7
HS		 1077 uart0 {
1078 uart0_xfer: uart0-xfer {
1079 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1080 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1081 };
1082
1083 uart0_cts: uart0-cts {
1084 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1085 };
1086
1087 uart0_rts: uart0-rts {
1088 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1089 };
1090 };
1091
1092 uart1 {
1093 uart1_xfer: uart1-xfer {
1094 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1095 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1096 };
1097
1098 uart1_cts: uart1-cts {
1099 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1100 };
1101
1102 uart1_rts: uart1-rts {
1103 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1104 };
1105 };
1106
1107 uart2 {
1108 uart2_xfer: uart2-xfer {
1109 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1110 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1111 };
1112 /* no rts / cts for uart2 */
1113 };
1114
1115 uart3 {
1116 uart3_xfer: uart3-xfer {
1117 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1118 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1119 };
1120
1121 uart3_cts: uart3-cts {
1122 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1123 };
1124
1125 uart3_rts: uart3-rts {
1126 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1127 };
1128 };
1129
1130 uart4 {
1131 uart4_xfer: uart4-xfer {
1132 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1133 <5 13 3 &pcfg_pull_none>;
1134 };
1135
1136 uart4_cts: uart4-cts {
1137 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1138 };
1139
1140 uart4_rts: uart4-rts {
1141 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1142 };
1143 };
df542df3 1144
b67d6bc3
CW		 1145 tsadc {
1146 otp_out: otp-out {
1147 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1148 };
1149 };
1150
df542df3
DA		 1151 pwm0 {
1152 pwm0_pin: pwm0-pin {
1153 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1154 };
1155 };
1156
1157 pwm1 {
1158 pwm1_pin: pwm1-pin {
1159 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1160 };
1161 };
1162
1163 pwm2 {
1164 pwm2_pin: pwm2-pin {
1165 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1166 };
1167 };
1168
1169 pwm3 {
1170 pwm3_pin: pwm3-pin {
1171 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1172 };
1173 };
2ab557b7
HS		 1174 };
1175};
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