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2ab557b7 HS |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License as published by | |
4 | * the Free Software Foundation; either version 2 of the License, or | |
5 | * (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #include <dt-bindings/gpio/gpio.h> | |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
16 | #include <dt-bindings/pinctrl/rockchip.h> | |
17 | #include <dt-bindings/clock/rk3288-cru.h> | |
18 | #include "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | compatible = "rockchip,rk3288"; | |
22 | ||
23 | interrupt-parent = <&gic>; | |
24 | ||
25 | aliases { | |
26 | i2c0 = &i2c0; | |
27 | i2c1 = &i2c1; | |
28 | i2c2 = &i2c2; | |
29 | i2c3 = &i2c3; | |
30 | i2c4 = &i2c4; | |
31 | i2c5 = &i2c5; | |
32 | serial0 = &uart0; | |
33 | serial1 = &uart1; | |
34 | serial2 = &uart2; | |
35 | serial3 = &uart3; | |
36 | serial4 = &uart4; | |
37 | }; | |
38 | ||
39 | cpus { | |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42 | ||
43 | cpu@500 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a12"; | |
46 | reg = <0x500>; | |
47 | }; | |
48 | cpu@501 { | |
49 | device_type = "cpu"; | |
50 | compatible = "arm,cortex-a12"; | |
51 | reg = <0x501>; | |
52 | }; | |
53 | cpu@502 { | |
54 | device_type = "cpu"; | |
55 | compatible = "arm,cortex-a12"; | |
56 | reg = <0x502>; | |
57 | }; | |
58 | cpu@503 { | |
59 | device_type = "cpu"; | |
60 | compatible = "arm,cortex-a12"; | |
61 | reg = <0x503>; | |
62 | }; | |
63 | }; | |
64 | ||
65 | xin24m: oscillator { | |
66 | compatible = "fixed-clock"; | |
67 | clock-frequency = <24000000>; | |
68 | clock-output-names = "xin24m"; | |
69 | #clock-cells = <0>; | |
70 | }; | |
71 | ||
72 | timer { | |
73 | compatible = "arm,armv7-timer"; | |
74 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
75 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
76 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
77 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
78 | clock-frequency = <24000000>; | |
79 | }; | |
80 | ||
85095bf3 DA |
81 | sdmmc: dwmmc@ff0c0000 { |
82 | compatible = "rockchip,rk3288-dw-mshc"; | |
83 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; | |
84 | clock-names = "biu", "ciu"; | |
85 | fifo-depth = <0x100>; | |
86 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
87 | reg = <0xff0c0000 0x4000>; | |
88 | status = "disabled"; | |
89 | }; | |
90 | ||
f1a07231 AK |
91 | sdio0: dwmmc@ff0d0000 { |
92 | compatible = "rockchip,rk3288-dw-mshc"; | |
93 | clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; | |
94 | clock-names = "biu", "ciu"; | |
95 | fifo-depth = <0x100>; | |
96 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
97 | reg = <0xff0d0000 0x4000>; | |
98 | status = "disabled"; | |
99 | }; | |
100 | ||
101 | sdio1: dwmmc@ff0e0000 { | |
102 | compatible = "rockchip,rk3288-dw-mshc"; | |
103 | clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; | |
104 | clock-names = "biu", "ciu"; | |
105 | fifo-depth = <0x100>; | |
106 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
107 | reg = <0xff0e0000 0x4000>; | |
108 | status = "disabled"; | |
109 | }; | |
110 | ||
85095bf3 DA |
111 | emmc: dwmmc@ff0f0000 { |
112 | compatible = "rockchip,rk3288-dw-mshc"; | |
113 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; | |
114 | clock-names = "biu", "ciu"; | |
115 | fifo-depth = <0x100>; | |
116 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
117 | reg = <0xff0f0000 0x4000>; | |
118 | status = "disabled"; | |
119 | }; | |
120 | ||
f23a6179 HS |
121 | saradc: saradc@ff100000 { |
122 | compatible = "rockchip,saradc"; | |
123 | reg = <0xff100000 0x100>; | |
124 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
125 | #io-channel-cells = <1>; | |
126 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
127 | clock-names = "saradc", "apb_pclk"; | |
128 | status = "disabled"; | |
129 | }; | |
130 | ||
2ab557b7 HS |
131 | i2c1: i2c@ff140000 { |
132 | compatible = "rockchip,rk3288-i2c"; | |
133 | reg = <0xff140000 0x1000>; | |
134 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
135 | #address-cells = <1>; | |
136 | #size-cells = <0>; | |
137 | clock-names = "i2c"; | |
138 | clocks = <&cru PCLK_I2C1>; | |
139 | pinctrl-names = "default"; | |
140 | pinctrl-0 = <&i2c1_xfer>; | |
141 | status = "disabled"; | |
142 | }; | |
143 | ||
144 | i2c3: i2c@ff150000 { | |
145 | compatible = "rockchip,rk3288-i2c"; | |
146 | reg = <0xff150000 0x1000>; | |
147 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | clock-names = "i2c"; | |
151 | clocks = <&cru PCLK_I2C3>; | |
152 | pinctrl-names = "default"; | |
153 | pinctrl-0 = <&i2c3_xfer>; | |
154 | status = "disabled"; | |
155 | }; | |
156 | ||
157 | i2c4: i2c@ff160000 { | |
158 | compatible = "rockchip,rk3288-i2c"; | |
159 | reg = <0xff160000 0x1000>; | |
160 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
161 | #address-cells = <1>; | |
162 | #size-cells = <0>; | |
163 | clock-names = "i2c"; | |
164 | clocks = <&cru PCLK_I2C4>; | |
165 | pinctrl-names = "default"; | |
166 | pinctrl-0 = <&i2c4_xfer>; | |
167 | status = "disabled"; | |
168 | }; | |
169 | ||
170 | i2c5: i2c@ff170000 { | |
171 | compatible = "rockchip,rk3288-i2c"; | |
172 | reg = <0xff170000 0x1000>; | |
173 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | clock-names = "i2c"; | |
177 | clocks = <&cru PCLK_I2C5>; | |
178 | pinctrl-names = "default"; | |
179 | pinctrl-0 = <&i2c5_xfer>; | |
180 | status = "disabled"; | |
181 | }; | |
182 | ||
183 | uart0: serial@ff180000 { | |
184 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
185 | reg = <0xff180000 0x100>; | |
186 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
187 | reg-shift = <2>; | |
188 | reg-io-width = <4>; | |
189 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
190 | clock-names = "baudclk", "apb_pclk"; | |
191 | pinctrl-names = "default"; | |
192 | pinctrl-0 = <&uart0_xfer>; | |
193 | status = "disabled"; | |
194 | }; | |
195 | ||
196 | uart1: serial@ff190000 { | |
197 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
198 | reg = <0xff190000 0x100>; | |
199 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
200 | reg-shift = <2>; | |
201 | reg-io-width = <4>; | |
202 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
203 | clock-names = "baudclk", "apb_pclk"; | |
204 | pinctrl-names = "default"; | |
205 | pinctrl-0 = <&uart1_xfer>; | |
206 | status = "disabled"; | |
207 | }; | |
208 | ||
209 | uart2: serial@ff690000 { | |
210 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
211 | reg = <0xff690000 0x100>; | |
212 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
213 | reg-shift = <2>; | |
214 | reg-io-width = <4>; | |
215 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
216 | clock-names = "baudclk", "apb_pclk"; | |
217 | pinctrl-names = "default"; | |
218 | pinctrl-0 = <&uart2_xfer>; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | uart3: serial@ff1b0000 { | |
223 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
224 | reg = <0xff1b0000 0x100>; | |
225 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
226 | reg-shift = <2>; | |
227 | reg-io-width = <4>; | |
228 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
229 | clock-names = "baudclk", "apb_pclk"; | |
230 | pinctrl-names = "default"; | |
231 | pinctrl-0 = <&uart3_xfer>; | |
232 | status = "disabled"; | |
233 | }; | |
234 | ||
235 | uart4: serial@ff1c0000 { | |
236 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
237 | reg = <0xff1c0000 0x100>; | |
238 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
239 | reg-shift = <2>; | |
240 | reg-io-width = <4>; | |
241 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; | |
242 | clock-names = "baudclk", "apb_pclk"; | |
243 | pinctrl-names = "default"; | |
244 | pinctrl-0 = <&uart4_xfer>; | |
245 | status = "disabled"; | |
246 | }; | |
247 | ||
c9c32c50 DA |
248 | usb_host0_ehci: usb@ff500000 { |
249 | compatible = "generic-ehci"; | |
250 | reg = <0xff500000 0x100>; | |
251 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
252 | clocks = <&cru HCLK_USBHOST0>; | |
253 | clock-names = "usbhost"; | |
254 | status = "disabled"; | |
255 | }; | |
256 | ||
257 | /* NOTE: ohci@ff520000 doesn't actually work on hardware */ | |
258 | ||
12dd3653 KY |
259 | usb_host1: usb@ff540000 { |
260 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
261 | "snps,dwc2"; | |
262 | reg = <0xff540000 0x40000>; | |
263 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
264 | clocks = <&cru HCLK_USBHOST1>; | |
265 | clock-names = "otg"; | |
266 | status = "disabled"; | |
267 | }; | |
268 | ||
269 | usb_otg: usb@ff580000 { | |
270 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
271 | "snps,dwc2"; | |
272 | reg = <0xff580000 0x40000>; | |
273 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
274 | clocks = <&cru HCLK_OTG0>; | |
275 | clock-names = "otg"; | |
276 | status = "disabled"; | |
277 | }; | |
278 | ||
c9c32c50 DA |
279 | usb_hsic: usb@ff5c0000 { |
280 | compatible = "generic-ehci"; | |
281 | reg = <0xff5c0000 0x100>; | |
282 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
283 | clocks = <&cru HCLK_HSIC>; | |
284 | clock-names = "usbhost"; | |
285 | status = "disabled"; | |
286 | }; | |
287 | ||
2ab557b7 HS |
288 | i2c0: i2c@ff650000 { |
289 | compatible = "rockchip,rk3288-i2c"; | |
290 | reg = <0xff650000 0x1000>; | |
291 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
292 | #address-cells = <1>; | |
293 | #size-cells = <0>; | |
294 | clock-names = "i2c"; | |
295 | clocks = <&cru PCLK_I2C0>; | |
296 | pinctrl-names = "default"; | |
297 | pinctrl-0 = <&i2c0_xfer>; | |
298 | status = "disabled"; | |
299 | }; | |
300 | ||
301 | i2c2: i2c@ff660000 { | |
302 | compatible = "rockchip,rk3288-i2c"; | |
303 | reg = <0xff660000 0x1000>; | |
304 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
305 | #address-cells = <1>; | |
306 | #size-cells = <0>; | |
307 | clock-names = "i2c"; | |
308 | clocks = <&cru PCLK_I2C2>; | |
309 | pinctrl-names = "default"; | |
310 | pinctrl-0 = <&i2c2_xfer>; | |
311 | status = "disabled"; | |
312 | }; | |
313 | ||
df542df3 DA |
314 | pwm0: pwm@ff680000 { |
315 | compatible = "rockchip,rk3288-pwm"; | |
316 | reg = <0xff680000 0x10>; | |
317 | #pwm-cells = <3>; | |
318 | pinctrl-names = "default"; | |
319 | pinctrl-0 = <&pwm0_pin>; | |
320 | clocks = <&cru PCLK_PWM>; | |
321 | clock-names = "pwm"; | |
322 | status = "disabled"; | |
323 | }; | |
324 | ||
325 | pwm1: pwm@ff680010 { | |
326 | compatible = "rockchip,rk3288-pwm"; | |
327 | reg = <0xff680010 0x10>; | |
328 | #pwm-cells = <3>; | |
329 | pinctrl-names = "default"; | |
330 | pinctrl-0 = <&pwm1_pin>; | |
331 | clocks = <&cru PCLK_PWM>; | |
332 | clock-names = "pwm"; | |
333 | status = "disabled"; | |
334 | }; | |
335 | ||
336 | pwm2: pwm@ff680020 { | |
337 | compatible = "rockchip,rk3288-pwm"; | |
338 | reg = <0xff680020 0x10>; | |
339 | #pwm-cells = <3>; | |
340 | pinctrl-names = "default"; | |
341 | pinctrl-0 = <&pwm2_pin>; | |
342 | clocks = <&cru PCLK_PWM>; | |
343 | clock-names = "pwm"; | |
344 | status = "disabled"; | |
345 | }; | |
346 | ||
347 | pwm3: pwm@ff680030 { | |
348 | compatible = "rockchip,rk3288-pwm"; | |
349 | reg = <0xff680030 0x10>; | |
350 | #pwm-cells = <2>; | |
351 | pinctrl-names = "default"; | |
352 | pinctrl-0 = <&pwm3_pin>; | |
353 | clocks = <&cru PCLK_PWM>; | |
354 | clock-names = "pwm"; | |
355 | status = "disabled"; | |
356 | }; | |
357 | ||
2ab557b7 HS |
358 | pmu: power-management@ff730000 { |
359 | compatible = "rockchip,rk3288-pmu", "syscon"; | |
360 | reg = <0xff730000 0x100>; | |
361 | }; | |
362 | ||
363 | sgrf: syscon@ff740000 { | |
364 | compatible = "rockchip,rk3288-sgrf", "syscon"; | |
365 | reg = <0xff740000 0x1000>; | |
366 | }; | |
367 | ||
368 | cru: clock-controller@ff760000 { | |
369 | compatible = "rockchip,rk3288-cru"; | |
370 | reg = <0xff760000 0x1000>; | |
371 | rockchip,grf = <&grf>; | |
372 | #clock-cells = <1>; | |
373 | #reset-cells = <1>; | |
374 | }; | |
375 | ||
376 | grf: syscon@ff770000 { | |
377 | compatible = "rockchip,rk3288-grf", "syscon"; | |
378 | reg = <0xff770000 0x1000>; | |
379 | }; | |
380 | ||
381 | wdt: watchdog@ff800000 { | |
382 | compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; | |
383 | reg = <0xff800000 0x100>; | |
384 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
385 | status = "disabled"; | |
386 | }; | |
387 | ||
388 | gic: interrupt-controller@ffc01000 { | |
389 | compatible = "arm,gic-400"; | |
390 | interrupt-controller; | |
391 | #interrupt-cells = <3>; | |
392 | #address-cells = <0>; | |
393 | ||
394 | reg = <0xffc01000 0x1000>, | |
395 | <0xffc02000 0x1000>, | |
396 | <0xffc04000 0x2000>, | |
397 | <0xffc06000 0x2000>; | |
398 | interrupts = <GIC_PPI 9 0xf04>; | |
399 | }; | |
400 | ||
401 | pinctrl: pinctrl { | |
402 | compatible = "rockchip,rk3288-pinctrl"; | |
403 | rockchip,grf = <&grf>; | |
404 | rockchip,pmu = <&pmu>; | |
405 | #address-cells = <1>; | |
406 | #size-cells = <1>; | |
407 | ranges; | |
408 | ||
409 | gpio0: gpio0@ff750000 { | |
410 | compatible = "rockchip,gpio-bank"; | |
411 | reg = <0xff750000 0x100>; | |
412 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
413 | clocks = <&cru PCLK_GPIO0>; | |
414 | ||
415 | gpio-controller; | |
416 | #gpio-cells = <2>; | |
417 | ||
418 | interrupt-controller; | |
419 | #interrupt-cells = <2>; | |
420 | }; | |
421 | ||
422 | gpio1: gpio1@ff780000 { | |
423 | compatible = "rockchip,gpio-bank"; | |
424 | reg = <0xff780000 0x100>; | |
425 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
426 | clocks = <&cru PCLK_GPIO1>; | |
427 | ||
428 | gpio-controller; | |
429 | #gpio-cells = <2>; | |
430 | ||
431 | interrupt-controller; | |
432 | #interrupt-cells = <2>; | |
433 | }; | |
434 | ||
435 | gpio2: gpio2@ff790000 { | |
436 | compatible = "rockchip,gpio-bank"; | |
437 | reg = <0xff790000 0x100>; | |
438 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
439 | clocks = <&cru PCLK_GPIO2>; | |
440 | ||
441 | gpio-controller; | |
442 | #gpio-cells = <2>; | |
443 | ||
444 | interrupt-controller; | |
445 | #interrupt-cells = <2>; | |
446 | }; | |
447 | ||
448 | gpio3: gpio3@ff7a0000 { | |
449 | compatible = "rockchip,gpio-bank"; | |
450 | reg = <0xff7a0000 0x100>; | |
451 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
452 | clocks = <&cru PCLK_GPIO3>; | |
453 | ||
454 | gpio-controller; | |
455 | #gpio-cells = <2>; | |
456 | ||
457 | interrupt-controller; | |
458 | #interrupt-cells = <2>; | |
459 | }; | |
460 | ||
461 | gpio4: gpio4@ff7b0000 { | |
462 | compatible = "rockchip,gpio-bank"; | |
463 | reg = <0xff7b0000 0x100>; | |
464 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
465 | clocks = <&cru PCLK_GPIO4>; | |
466 | ||
467 | gpio-controller; | |
468 | #gpio-cells = <2>; | |
469 | ||
470 | interrupt-controller; | |
471 | #interrupt-cells = <2>; | |
472 | }; | |
473 | ||
474 | gpio5: gpio5@ff7c0000 { | |
475 | compatible = "rockchip,gpio-bank"; | |
476 | reg = <0xff7c0000 0x100>; | |
477 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
478 | clocks = <&cru PCLK_GPIO5>; | |
479 | ||
480 | gpio-controller; | |
481 | #gpio-cells = <2>; | |
482 | ||
483 | interrupt-controller; | |
484 | #interrupt-cells = <2>; | |
485 | }; | |
486 | ||
487 | gpio6: gpio6@ff7d0000 { | |
488 | compatible = "rockchip,gpio-bank"; | |
489 | reg = <0xff7d0000 0x100>; | |
490 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
491 | clocks = <&cru PCLK_GPIO6>; | |
492 | ||
493 | gpio-controller; | |
494 | #gpio-cells = <2>; | |
495 | ||
496 | interrupt-controller; | |
497 | #interrupt-cells = <2>; | |
498 | }; | |
499 | ||
500 | gpio7: gpio7@ff7e0000 { | |
501 | compatible = "rockchip,gpio-bank"; | |
502 | reg = <0xff7e0000 0x100>; | |
503 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
504 | clocks = <&cru PCLK_GPIO7>; | |
505 | ||
506 | gpio-controller; | |
507 | #gpio-cells = <2>; | |
508 | ||
509 | interrupt-controller; | |
510 | #interrupt-cells = <2>; | |
511 | }; | |
512 | ||
513 | gpio8: gpio8@ff7f0000 { | |
514 | compatible = "rockchip,gpio-bank"; | |
515 | reg = <0xff7f0000 0x100>; | |
516 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
517 | clocks = <&cru PCLK_GPIO8>; | |
518 | ||
519 | gpio-controller; | |
520 | #gpio-cells = <2>; | |
521 | ||
522 | interrupt-controller; | |
523 | #interrupt-cells = <2>; | |
524 | }; | |
525 | ||
526 | pcfg_pull_up: pcfg-pull-up { | |
527 | bias-pull-up; | |
528 | }; | |
529 | ||
530 | pcfg_pull_down: pcfg-pull-down { | |
531 | bias-pull-down; | |
532 | }; | |
533 | ||
534 | pcfg_pull_none: pcfg-pull-none { | |
535 | bias-disable; | |
536 | }; | |
537 | ||
538 | i2c0 { | |
539 | i2c0_xfer: i2c0-xfer { | |
540 | rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, | |
541 | <0 16 RK_FUNC_1 &pcfg_pull_none>; | |
542 | }; | |
543 | }; | |
544 | ||
545 | i2c1 { | |
546 | i2c1_xfer: i2c1-xfer { | |
547 | rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, | |
548 | <8 5 RK_FUNC_1 &pcfg_pull_none>; | |
549 | }; | |
550 | }; | |
551 | ||
552 | i2c2 { | |
553 | i2c2_xfer: i2c2-xfer { | |
554 | rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, | |
555 | <6 10 RK_FUNC_1 &pcfg_pull_none>; | |
556 | }; | |
557 | }; | |
558 | ||
559 | i2c3 { | |
560 | i2c3_xfer: i2c3-xfer { | |
561 | rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
562 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
563 | }; | |
564 | }; | |
565 | ||
566 | i2c4 { | |
567 | i2c4_xfer: i2c4-xfer { | |
568 | rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, | |
569 | <7 18 RK_FUNC_1 &pcfg_pull_none>; | |
570 | }; | |
571 | }; | |
572 | ||
573 | i2c5 { | |
574 | i2c5_xfer: i2c5-xfer { | |
575 | rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, | |
576 | <7 20 RK_FUNC_1 &pcfg_pull_none>; | |
577 | }; | |
578 | }; | |
579 | ||
580 | sdmmc { | |
581 | sdmmc_clk: sdmmc-clk { | |
582 | rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; | |
583 | }; | |
584 | ||
585 | sdmmc_cmd: sdmmc-cmd { | |
586 | rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; | |
587 | }; | |
588 | ||
589 | sdmmc_cd: sdmcc-cd { | |
590 | rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; | |
591 | }; | |
592 | ||
593 | sdmmc_bus1: sdmmc-bus1 { | |
594 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; | |
595 | }; | |
596 | ||
597 | sdmmc_bus4: sdmmc-bus4 { | |
598 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, | |
599 | <6 17 RK_FUNC_1 &pcfg_pull_up>, | |
600 | <6 18 RK_FUNC_1 &pcfg_pull_up>, | |
601 | <6 19 RK_FUNC_1 &pcfg_pull_up>; | |
602 | }; | |
603 | }; | |
604 | ||
f1a07231 AK |
605 | sdio0 { |
606 | sdio0_bus1: sdio0-bus1 { | |
607 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; | |
608 | }; | |
609 | ||
610 | sdio0_bus4: sdio0-bus4 { | |
611 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, | |
612 | <4 21 RK_FUNC_1 &pcfg_pull_up>, | |
613 | <4 22 RK_FUNC_1 &pcfg_pull_up>, | |
614 | <4 23 RK_FUNC_1 &pcfg_pull_up>; | |
615 | }; | |
616 | ||
617 | sdio0_cmd: sdio0-cmd { | |
618 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; | |
619 | }; | |
620 | ||
621 | sdio0_clk: sdio0-clk { | |
622 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; | |
623 | }; | |
624 | ||
625 | sdio0_cd: sdio0-cd { | |
626 | rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; | |
627 | }; | |
628 | ||
629 | sdio0_wp: sdio0-wp { | |
630 | rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; | |
631 | }; | |
632 | ||
633 | sdio0_pwr: sdio0-pwr { | |
634 | rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; | |
635 | }; | |
636 | ||
637 | sdio0_bkpwr: sdio0-bkpwr { | |
638 | rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; | |
639 | }; | |
640 | ||
641 | sdio0_int: sdio0-int { | |
642 | rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; | |
643 | }; | |
644 | }; | |
645 | ||
646 | sdio1 { | |
647 | sdio1_bus1: sdio1-bus1 { | |
648 | rockchip,pins = <3 24 4 &pcfg_pull_up>; | |
649 | }; | |
650 | ||
651 | sdio1_bus4: sdio1-bus4 { | |
652 | rockchip,pins = <3 24 4 &pcfg_pull_up>, | |
653 | <3 25 4 &pcfg_pull_up>, | |
654 | <3 26 4 &pcfg_pull_up>, | |
655 | <3 27 4 &pcfg_pull_up>; | |
656 | }; | |
657 | ||
658 | sdio1_cd: sdio1-cd { | |
659 | rockchip,pins = <3 28 4 &pcfg_pull_up>; | |
660 | }; | |
661 | ||
662 | sdio1_wp: sdio1-wp { | |
663 | rockchip,pins = <3 29 4 &pcfg_pull_up>; | |
664 | }; | |
665 | ||
666 | sdio1_bkpwr: sdio1-bkpwr { | |
667 | rockchip,pins = <3 30 4 &pcfg_pull_up>; | |
668 | }; | |
669 | ||
670 | sdio1_int: sdio1-int { | |
671 | rockchip,pins = <3 31 4 &pcfg_pull_up>; | |
672 | }; | |
673 | ||
674 | sdio1_cmd: sdio1-cmd { | |
675 | rockchip,pins = <4 6 4 &pcfg_pull_up>; | |
676 | }; | |
677 | ||
678 | sdio1_clk: sdio1-clk { | |
679 | rockchip,pins = <4 7 4 &pcfg_pull_none>; | |
680 | }; | |
681 | ||
682 | sdio1_pwr: sdio1-pwr { | |
683 | rockchip,pins = <4 9 4 &pcfg_pull_up>; | |
684 | }; | |
685 | }; | |
686 | ||
2ab557b7 HS |
687 | emmc { |
688 | emmc_clk: emmc-clk { | |
689 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
690 | }; | |
691 | ||
692 | emmc_cmd: emmc-cmd { | |
693 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; | |
694 | }; | |
695 | ||
696 | emmc_pwr: emmc-pwr { | |
697 | rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; | |
698 | }; | |
699 | ||
700 | emmc_bus1: emmc-bus1 { | |
701 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
702 | }; | |
703 | ||
704 | emmc_bus4: emmc-bus4 { | |
705 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
706 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
707 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
708 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
709 | }; | |
710 | ||
711 | emmc_bus8: emmc-bus8 { | |
712 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
713 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
714 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
715 | <3 3 RK_FUNC_2 &pcfg_pull_up>, | |
716 | <3 4 RK_FUNC_2 &pcfg_pull_up>, | |
717 | <3 5 RK_FUNC_2 &pcfg_pull_up>, | |
718 | <3 6 RK_FUNC_2 &pcfg_pull_up>, | |
719 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
720 | }; | |
721 | }; | |
722 | ||
723 | uart0 { | |
724 | uart0_xfer: uart0-xfer { | |
725 | rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, | |
726 | <4 17 RK_FUNC_1 &pcfg_pull_none>; | |
727 | }; | |
728 | ||
729 | uart0_cts: uart0-cts { | |
730 | rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; | |
731 | }; | |
732 | ||
733 | uart0_rts: uart0-rts { | |
734 | rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; | |
735 | }; | |
736 | }; | |
737 | ||
738 | uart1 { | |
739 | uart1_xfer: uart1-xfer { | |
740 | rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, | |
741 | <5 9 RK_FUNC_1 &pcfg_pull_none>; | |
742 | }; | |
743 | ||
744 | uart1_cts: uart1-cts { | |
745 | rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; | |
746 | }; | |
747 | ||
748 | uart1_rts: uart1-rts { | |
749 | rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; | |
750 | }; | |
751 | }; | |
752 | ||
753 | uart2 { | |
754 | uart2_xfer: uart2-xfer { | |
755 | rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, | |
756 | <7 23 RK_FUNC_1 &pcfg_pull_none>; | |
757 | }; | |
758 | /* no rts / cts for uart2 */ | |
759 | }; | |
760 | ||
761 | uart3 { | |
762 | uart3_xfer: uart3-xfer { | |
763 | rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, | |
764 | <7 8 RK_FUNC_1 &pcfg_pull_none>; | |
765 | }; | |
766 | ||
767 | uart3_cts: uart3-cts { | |
768 | rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; | |
769 | }; | |
770 | ||
771 | uart3_rts: uart3-rts { | |
772 | rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; | |
773 | }; | |
774 | }; | |
775 | ||
776 | uart4 { | |
777 | uart4_xfer: uart4-xfer { | |
778 | rockchip,pins = <5 12 3 &pcfg_pull_up>, | |
779 | <5 13 3 &pcfg_pull_none>; | |
780 | }; | |
781 | ||
782 | uart4_cts: uart4-cts { | |
783 | rockchip,pins = <5 14 3 &pcfg_pull_none>; | |
784 | }; | |
785 | ||
786 | uart4_rts: uart4-rts { | |
787 | rockchip,pins = <5 15 3 &pcfg_pull_none>; | |
788 | }; | |
789 | }; | |
df542df3 DA |
790 | |
791 | pwm0 { | |
792 | pwm0_pin: pwm0-pin { | |
793 | rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; | |
794 | }; | |
795 | }; | |
796 | ||
797 | pwm1 { | |
798 | pwm1_pin: pwm1-pin { | |
799 | rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; | |
800 | }; | |
801 | }; | |
802 | ||
803 | pwm2 { | |
804 | pwm2_pin: pwm2-pin { | |
805 | rockchip,pins = <7 22 3 &pcfg_pull_none>; | |
806 | }; | |
807 | }; | |
808 | ||
809 | pwm3 { | |
810 | pwm3_pin: pwm3-pin { | |
811 | rockchip,pins = <7 23 3 &pcfg_pull_none>; | |
812 | }; | |
813 | }; | |
2ab557b7 HS |
814 | }; |
815 | }; |