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f75efdd7 HS |
1 | /* |
2 | * Copyright (c) 2013 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <dt-bindings/interrupt-controller/irq.h> | |
17 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
18 | #include "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | interrupt-parent = <&gic>; | |
22 | ||
23 | soc { | |
24 | #address-cells = <1>; | |
25 | #size-cells = <1>; | |
26 | compatible = "simple-bus"; | |
27 | ranges; | |
28 | ||
29 | gic: interrupt-controller@1013d000 { | |
30 | compatible = "arm,cortex-a9-gic"; | |
31 | interrupt-controller; | |
32 | #interrupt-cells = <3>; | |
33 | reg = <0x1013d000 0x1000>, | |
34 | <0x1013c100 0x0100>; | |
35 | }; | |
36 | ||
37 | L2: l2-cache-controller@10138000 { | |
38 | compatible = "arm,pl310-cache"; | |
39 | reg = <0x10138000 0x1000>; | |
40 | cache-unified; | |
41 | cache-level = <2>; | |
42 | }; | |
43 | ||
f95a2b3d HS |
44 | global-timer@1013c200 { |
45 | compatible = "arm,cortex-a9-global-timer"; | |
46 | reg = <0x1013c200 0x20>; | |
47 | interrupts = <GIC_PPI 11 0x304>; | |
48 | clocks = <&dummy150m>; | |
49 | }; | |
50 | ||
f75efdd7 HS |
51 | local-timer@1013c600 { |
52 | compatible = "arm,cortex-a9-twd-timer"; | |
53 | reg = <0x1013c600 0x20>; | |
54 | interrupts = <GIC_PPI 13 0x304>; | |
55 | clocks = <&dummy150m>; | |
56 | }; | |
57 | ||
58 | uart0: serial@10124000 { | |
59 | compatible = "snps,dw-apb-uart"; | |
60 | reg = <0x10124000 0x400>; | |
61 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
62 | reg-shift = <2>; | |
63 | reg-io-width = <1>; | |
64 | clocks = <&clk_gates1 8>; | |
65 | status = "disabled"; | |
66 | }; | |
67 | ||
68 | uart1: serial@10126000 { | |
69 | compatible = "snps,dw-apb-uart"; | |
70 | reg = <0x10126000 0x400>; | |
71 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
72 | reg-shift = <2>; | |
73 | reg-io-width = <1>; | |
74 | clocks = <&clk_gates1 10>; | |
75 | status = "disabled"; | |
76 | }; | |
77 | ||
78 | uart2: serial@20064000 { | |
79 | compatible = "snps,dw-apb-uart"; | |
80 | reg = <0x20064000 0x400>; | |
81 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
82 | reg-shift = <2>; | |
83 | reg-io-width = <1>; | |
84 | clocks = <&clk_gates1 12>; | |
85 | status = "disabled"; | |
86 | }; | |
87 | ||
88 | uart3: serial@20068000 { | |
89 | compatible = "snps,dw-apb-uart"; | |
90 | reg = <0x20068000 0x400>; | |
91 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
92 | reg-shift = <2>; | |
93 | reg-io-width = <1>; | |
94 | clocks = <&clk_gates1 14>; | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | dwmmc@10214000 { | |
99 | compatible = "rockchip,rk2928-dw-mshc"; | |
100 | reg = <0x10214000 0x1000>; | |
101 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
102 | #address-cells = <1>; | |
103 | #size-cells = <0>; | |
104 | ||
105 | clocks = <&clk_gates5 10>, <&clk_gates2 11>; | |
106 | clock-names = "biu", "ciu"; | |
107 | ||
108 | status = "disabled"; | |
109 | }; | |
110 | ||
111 | dwmmc@10218000 { | |
112 | compatible = "rockchip,rk2928-dw-mshc"; | |
113 | reg = <0x10218000 0x1000>; | |
114 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
115 | #address-cells = <1>; | |
116 | #size-cells = <0>; | |
117 | ||
118 | clocks = <&clk_gates5 11>, <&clk_gates2 13>; | |
119 | clock-names = "biu", "ciu"; | |
120 | ||
121 | status = "disabled"; | |
122 | }; | |
123 | }; | |
124 | }; |