[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / rk3xxx.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &emac;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		mshc0 = &emmc;
		mshc1 = &mmc0;
		mshc2 = &mmc1;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		spi0 = &spi0;
		spi1 = &spi1;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dmac1_s: dma-controller@20018000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20018000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			arm,pl330-broken-no-flushp;
			clocks = <&cru ACLK_DMA1>;
			clock-names = "apb_pclk";
		};

		dmac1_ns: dma-controller@2001c000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x2001c000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			arm,pl330-broken-no-flushp;
			clocks = <&cru ACLK_DMA1>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		dmac2: dma-controller@20078000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20078000 0x4000>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			arm,pl330-broken-no-flushp;
			clocks = <&cru ACLK_DMA2>;
			clock-names = "apb_pclk";
		};
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
		clock-output-names = "xin24m";
	};

	L2: l2-cache-controller@10138000 {
		compatible = "arm,pl310-cache";
		reg = <0x10138000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	scu@1013c000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x1013c000 0x100>;
	};

	global_timer: global-timer@1013c200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x1013c200 0x20>;
		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cru CORE_PERI>;
	};

	local_timer: local-timer@1013c600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x1013c600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cru CORE_PERI>;
	};

	gic: interrupt-controller@1013d000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x1013d000 0x1000>,
		      <0x1013c100 0x0100>;
	};

	uart0: serial@10124000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10124000 0x400>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		status = "disabled";
	};

	uart1: serial@10126000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10126000 0x400>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		status = "disabled";
	};

	usb_otg: usb@10180000 {
		compatible = "rockchip,rk3066-usb", "snps,dwc2";
		reg = <0x10180000 0x40000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG0>;
		clock-names = "otg";
		dr_mode = "otg";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <275>;
		g-tx-fifo-size = <256 128 128 64 64 32>;
		phys = <&usbphy0>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_host: usb@101c0000 {
		compatible = "snps,dwc2";
		reg = <0x101c0000 0x40000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG1>;
		clock-names = "otg";
		dr_mode = "host";
		phys = <&usbphy1>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	emac: ethernet@10204000 {
		compatible = "snps,arc-emac";
		reg = <0x10204000 0x3c>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
		clock-names = "hclk", "macref";
		max-speed = <100>;
		phy-mode = "rmii";

		status = "disabled";
	};

	mmc0: dwmmc@10214000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x10214000 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
		clock-names = "biu", "ciu";
		dmas = <&dmac2 1>;
		dma-names = "rx-tx";
		fifo-depth = <256>;
		resets = <&cru SRST_SDMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	mmc1: dwmmc@10218000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x10218000 0x1000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
		clock-names = "biu", "ciu";
		dmas = <&dmac2 3>;
		dma-names = "rx-tx";
		fifo-depth = <256>;
		resets = <&cru SRST_SDIO>;
		reset-names = "reset";
		status = "disabled";
	};

	emmc: dwmmc@1021c000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x1021c000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
		clock-names = "biu", "ciu";
		dmas = <&dmac2 4>;
		dma-names = "rx-tx";
		fifo-depth = <256>;
		resets = <&cru SRST_EMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	pmu: pmu@20004000 {
		compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
		reg = <0x20004000 0x100>;

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x40>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-bootloader = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
		};
	};

	grf: grf@20008000 {
		compatible = "syscon";
		reg = <0x20008000 0x200>;
	};

	i2c0: i2c@2002d000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2002d000 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;

		status = "disabled";
	};

	i2c1: i2c@2002f000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2002f000 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C1>;
		clock-names = "i2c";

		status = "disabled";
	};

	pwm0: pwm@20030000 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20030000 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM01>;
		status = "disabled";
	};

	pwm1: pwm@20030010 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20030010 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM01>;
		status = "disabled";
	};

	wdt: watchdog@2004c000 {
		compatible = "snps,dw-wdt";
		reg = <0x2004c000 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pwm2: pwm@20050020 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20050020 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM23>;
		status = "disabled";
	};

	pwm3: pwm@20050030 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20050030 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM23>;
		status = "disabled";
	};

	i2c2: i2c@20056000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x20056000 0x1000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C2>;
		clock-names = "i2c";

		status = "disabled";
	};

	i2c3: i2c@2005a000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2005a000 0x1000>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C3>;
		clock-names = "i2c";

		status = "disabled";
	};

	i2c4: i2c@2005e000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2005e000 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C4>;
		clock-names = "i2c";

		status = "disabled";
	};

	uart2: serial@20064000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20064000 0x400>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		status = "disabled";
	};

	uart3: serial@20068000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20068000 0x400>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		status = "disabled";
	};

	saradc: saradc@2006c000 {
		compatible = "rockchip,saradc";
		reg = <0x2006c000 0x100>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	spi0: spi@20070000 {
		compatible = "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x20070000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&dmac2 10>, <&dmac2 11>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	spi1: spi@20074000 {
		compatible = "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x20074000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&dmac2 12>, <&dmac2 13>;
		dma-names = "tx", "rx";
		status = "disabled";
	};
};
Commit	Line	Data
f75efdd7 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
d6250a1f HS	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
f75efdd7	9	*
d6250a1f HS	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
f75efdd7 HS	42	*/
	43
	44	#include <dt-bindings/interrupt-controller/irq.h>
	45	#include <dt-bindings/interrupt-controller/arm-gic.h>
b60ab70b	46	#include <dt-bindings/soc/rockchip,boot-mode.h>
f75efdd7 HS	47
f75efdd7 HS	48	/ {
80f6defc JMC	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51
f75efdd7 HS	52	interrupt-parent = <&gic>;
f75efdd7 HS	53
9cdffd8c	54	aliases {
b3e4b953	55	ethernet0 = &emac;
9cdffd8c HS	56	i2c0 = &i2c0;
	57	i2c1 = &i2c1;
	58	i2c2 = &i2c2;
	59	i2c3 = &i2c3;
	60	i2c4 = &i2c4;
4ff4ae12 HS	61	mshc0 = &emmc;
	62	mshc1 = &mmc0;
	63	mshc2 = &mmc1;
e5b0deda JC	64	serial0 = &uart0;
	65	serial1 = &uart1;
	66	serial2 = &uart2;
	67	serial3 = &uart3;
39c2bd78 HS	68	spi0 = &spi0;
39c2bd78 HS	69	spi1 = &spi1;
9cdffd8c HS	70	};
9cdffd8c HS	71
ac42f481	72	amba {
2ef7d5f3	73	compatible = "simple-bus";
ac42f481 HS	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	ranges;
	77
	78	dmac1_s: dma-controller@20018000 {
	79	compatible = "arm,pl330", "arm,primecell";
	80	reg = <0x20018000 0x4000>;
	81	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	82	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	83	#dma-cells = <1>;
9bed8b41	84	arm,pl330-broken-no-flushp;
ac42f481 HS	85	clocks = <&cru ACLK_DMA1>;
	86	clock-names = "apb_pclk";
	87	};
	88
	89	dmac1_ns: dma-controller@2001c000 {
	90	compatible = "arm,pl330", "arm,primecell";
	91	reg = <0x2001c000 0x4000>;
	92	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	93	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	94	#dma-cells = <1>;
9bed8b41	95	arm,pl330-broken-no-flushp;
ac42f481 HS	96	clocks = <&cru ACLK_DMA1>;
	97	clock-names = "apb_pclk";
	98	status = "disabled";
	99	};
	100
	101	dmac2: dma-controller@20078000 {
	102	compatible = "arm,pl330", "arm,primecell";
	103	reg = <0x20078000 0x4000>;
	104	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	105	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	106	#dma-cells = <1>;
9bed8b41	107	arm,pl330-broken-no-flushp;
ac42f481 HS	108	clocks = <&cru ACLK_DMA2>;
	109	clock-names = "apb_pclk";
	110	};
	111	};
	112
560106c1 HS	113	xin24m: oscillator {
	114	compatible = "fixed-clock";
	115	clock-frequency = <24000000>;
	116	#clock-cells = <0>;
	117	clock-output-names = "xin24m";
	118	};
	119
c3030d30 HS	120	L2: l2-cache-controller@10138000 {
	121	compatible = "arm,pl310-cache";
	122	reg = <0x10138000 0x1000>;
	123	cache-unified;
	124	cache-level = <2>;
	125	};
	126
ff84b90e HS	127	scu@1013c000 {
	128	compatible = "arm,cortex-a9-scu";
	129	reg = <0x1013c000 0x100>;
	130	};
	131
e40b43d6	132	global_timer: global-timer@1013c200 {
c3030d30 HS	133	compatible = "arm,cortex-a9-global-timer";
c3030d30 HS	134	reg = <0x1013c200 0x20>;
2e1aa605	135	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_EDGE_RISING)>;
c3030d30 HS	136	clocks = <&cru CORE_PERI>;
	137	};
	138
e40b43d6	139	local_timer: local-timer@1013c600 {
c3030d30 HS	140	compatible = "arm,cortex-a9-twd-timer";
c3030d30 HS	141	reg = <0x1013c600 0x20>;
2e1aa605	142	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_EDGE_RISING)>;
c3030d30 HS	143	clocks = <&cru CORE_PERI>;
	144	};
	145
ff84b90e HS	146	gic: interrupt-controller@1013d000 {
	147	compatible = "arm,cortex-a9-gic";
	148	interrupt-controller;
	149	#interrupt-cells = <3>;
	150	reg = <0x1013d000 0x1000>,
	151	<0x1013c100 0x0100>;
	152	};
	153
c3030d30 HS	154	uart0: serial@10124000 {
	155	compatible = "snps,dw-apb-uart";
	156	reg = <0x10124000 0x400>;
	157	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	158	reg-shift = <2>;
	159	reg-io-width = <1>;
69667ca2 HS	160	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	161	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
c3030d30 HS	162	status = "disabled";
	163	};
	164
	165	uart1: serial@10126000 {
	166	compatible = "snps,dw-apb-uart";
	167	reg = <0x10126000 0x400>;
	168	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	169	reg-shift = <2>;
	170	reg-io-width = <1>;
69667ca2 HS	171	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	172	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
c3030d30 HS	173	status = "disabled";
	174	};
	175
fd14e6f9 HS	176	usb_otg: usb@10180000 {
	177	compatible = "rockchip,rk3066-usb", "snps,dwc2";
	178	reg = <0x10180000 0x40000>;
	179	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	180	clocks = <&cru HCLK_OTG0>;
	181	clock-names = "otg";
ec32bd9f HS	182	dr_mode = "otg";
	183	g-np-tx-fifo-size = <16>;
	184	g-rx-fifo-size = <275>;
	185	g-tx-fifo-size = <256 128 128 64 64 32>;
760bb977 HS	186	phys = <&usbphy0>;
760bb977 HS	187	phy-names = "usb2-phy";
fd14e6f9 HS	188	status = "disabled";
	189	};
	190
	191	usb_host: usb@101c0000 {
	192	compatible = "snps,dwc2";
	193	reg = <0x101c0000 0x40000>;
	194	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	195	clocks = <&cru HCLK_OTG1>;
	196	clock-names = "otg";
ec32bd9f	197	dr_mode = "host";
760bb977 HS	198	phys = <&usbphy1>;
760bb977 HS	199	phy-names = "usb2-phy";
fd14e6f9 HS	200	status = "disabled";
	201	};
	202
18ec91e1 RP	203	emac: ethernet@10204000 {
	204	compatible = "snps,arc-emac";
	205	reg = <0x10204000 0x3c>;
	206	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209
	210	rockchip,grf = <&grf>;
	211
	212	clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
	213	clock-names = "hclk", "macref";
	214	max-speed = <100>;
	215	phy-mode = "rmii";
	216
	217	status = "disabled";
	218	};
	219
e40b43d6	220	mmc0: dwmmc@10214000 {
c3030d30 HS	221	compatible = "rockchip,rk2928-dw-mshc";
	222	reg = <0x10214000 0x1000>;
	223	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
c3030d30 HS	224	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
c3030d30 HS	225	clock-names = "biu", "ciu";
94bbdd77 AK	226	dmas = <&dmac2 1>;
94bbdd77 AK	227	dma-names = "rx-tx";
4c1e3ff7	228	fifo-depth = <256>;
ee0024fd HS	229	resets = <&cru SRST_SDMMC>;
ee0024fd HS	230	reset-names = "reset";
c3030d30 HS	231	status = "disabled";
	232	};
	233
e40b43d6	234	mmc1: dwmmc@10218000 {
c3030d30 HS	235	compatible = "rockchip,rk2928-dw-mshc";
	236	reg = <0x10218000 0x1000>;
	237	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
c3030d30 HS	238	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
c3030d30 HS	239	clock-names = "biu", "ciu";
94bbdd77 AK	240	dmas = <&dmac2 3>;
94bbdd77 AK	241	dma-names = "rx-tx";
4c1e3ff7	242	fifo-depth = <256>;
ee0024fd HS	243	resets = <&cru SRST_SDIO>;
ee0024fd HS	244	reset-names = "reset";
c3030d30	245	status = "disabled";
f75efdd7	246	};
ff84b90e	247
4ff4ae12 HS	248	emmc: dwmmc@1021c000 {
	249	compatible = "rockchip,rk2928-dw-mshc";
	250	reg = <0x1021c000 0x1000>;
	251	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
4ff4ae12 HS	252	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
4ff4ae12 HS	253	clock-names = "biu", "ciu";
94bbdd77 AK	254	dmas = <&dmac2 4>;
94bbdd77 AK	255	dma-names = "rx-tx";
4c1e3ff7	256	fifo-depth = <256>;
ee0024fd HS	257	resets = <&cru SRST_EMMC>;
ee0024fd HS	258	reset-names = "reset";
4ff4ae12 HS	259	status = "disabled";
	260	};
	261
ff84b90e	262	pmu: pmu@20004000 {
b60ab70b	263	compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
ff84b90e	264	reg = <0x20004000 0x100>;
b60ab70b AY	265
	266	reboot-mode {
	267	compatible = "syscon-reboot-mode";
	268	offset = <0x40>;
	269	mode-normal = <BOOT_NORMAL>;
	270	mode-recovery = <BOOT_RECOVERY>;
	271	mode-bootloader = <BOOT_FASTBOOT>;
	272	mode-loader = <BOOT_BL_DOWNLOAD>;
	273	};
ff84b90e HS	274	};
	275
	276	grf: grf@20008000 {
	277	compatible = "syscon";
	278	reg = <0x20008000 0x200>;
	279	};
	280
9cdffd8c HS	281	i2c0: i2c@2002d000 {
	282	compatible = "rockchip,rk3066-i2c";
	283	reg = <0x2002d000 0x1000>;
	284	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	285	#address-cells = <1>;
	286	#size-cells = <0>;
	287
	288	rockchip,grf = <&grf>;
9cdffd8c HS	289
	290	clock-names = "i2c";
	291	clocks = <&cru PCLK_I2C0>;
	292
	293	status = "disabled";
	294	};
	295
	296	i2c1: i2c@2002f000 {
	297	compatible = "rockchip,rk3066-i2c";
	298	reg = <0x2002f000 0x1000>;
	299	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	300	#address-cells = <1>;
	301	#size-cells = <0>;
	302
	303	rockchip,grf = <&grf>;
	304
	305	clocks = <&cru PCLK_I2C1>;
	306	clock-names = "i2c";
	307
	308	status = "disabled";
	309	};
	310
550c7f4e BG	311	pwm0: pwm@20030000 {
	312	compatible = "rockchip,rk2928-pwm";
	313	reg = <0x20030000 0x10>;
	314	#pwm-cells = <2>;
	315	clocks = <&cru PCLK_PWM01>;
	316	status = "disabled";
	317	};
	318
	319	pwm1: pwm@20030010 {
	320	compatible = "rockchip,rk2928-pwm";
	321	reg = <0x20030010 0x10>;
	322	#pwm-cells = <2>;
	323	clocks = <&cru PCLK_PWM01>;
	324	status = "disabled";
	325	};
	326
eb2b9d47 HS	327	wdt: watchdog@2004c000 {
	328	compatible = "snps,dw-wdt";
	329	reg = <0x2004c000 0x100>;
	330	clocks = <&cru PCLK_WDT>;
	331	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	332	status = "disabled";
	333	};
	334
550c7f4e BG	335	pwm2: pwm@20050020 {
	336	compatible = "rockchip,rk2928-pwm";
	337	reg = <0x20050020 0x10>;
	338	#pwm-cells = <2>;
	339	clocks = <&cru PCLK_PWM23>;
	340	status = "disabled";
	341	};
	342
	343	pwm3: pwm@20050030 {
	344	compatible = "rockchip,rk2928-pwm";
	345	reg = <0x20050030 0x10>;
	346	#pwm-cells = <2>;
	347	clocks = <&cru PCLK_PWM23>;
	348	status = "disabled";
	349	};
	350
9cdffd8c HS	351	i2c2: i2c@20056000 {
	352	compatible = "rockchip,rk3066-i2c";
	353	reg = <0x20056000 0x1000>;
	354	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	355	#address-cells = <1>;
	356	#size-cells = <0>;
	357
	358	rockchip,grf = <&grf>;
	359
	360	clocks = <&cru PCLK_I2C2>;
	361	clock-names = "i2c";
	362
	363	status = "disabled";
	364	};
	365
	366	i2c3: i2c@2005a000 {
	367	compatible = "rockchip,rk3066-i2c";
	368	reg = <0x2005a000 0x1000>;
	369	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	370	#address-cells = <1>;
	371	#size-cells = <0>;
	372
	373	rockchip,grf = <&grf>;
	374
	375	clocks = <&cru PCLK_I2C3>;
	376	clock-names = "i2c";
	377
	378	status = "disabled";
	379	};
	380
	381	i2c4: i2c@2005e000 {
	382	compatible = "rockchip,rk3066-i2c";
	383	reg = <0x2005e000 0x1000>;
	384	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	385	#address-cells = <1>;
	386	#size-cells = <0>;
	387
	388	rockchip,grf = <&grf>;
	389
	390	clocks = <&cru PCLK_I2C4>;
	391	clock-names = "i2c";
	392
	393	status = "disabled";
	394	};
	395
ff84b90e HS	396	uart2: serial@20064000 {
	397	compatible = "snps,dw-apb-uart";
	398	reg = <0x20064000 0x400>;
	399	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	400	reg-shift = <2>;
	401	reg-io-width = <1>;
69667ca2 HS	402	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	403	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
ff84b90e HS	404	status = "disabled";
	405	};
	406
	407	uart3: serial@20068000 {
	408	compatible = "snps,dw-apb-uart";
	409	reg = <0x20068000 0x400>;
	410	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	411	reg-shift = <2>;
	412	reg-io-width = <1>;
69667ca2 HS	413	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	414	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
ff84b90e HS	415	status = "disabled";
ff84b90e HS	416	};
f23a6179 HS	417
	418	saradc: saradc@2006c000 {
	419	compatible = "rockchip,saradc";
	420	reg = <0x2006c000 0x100>;
	421	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	422	#io-channel-cells = <1>;
	423	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	424	clock-names = "saradc", "apb_pclk";
3d4267a5 CW	425	resets = <&cru SRST_SARADC>;
3d4267a5 CW	426	reset-names = "saradc-apb";
f23a6179 HS	427	status = "disabled";
f23a6179 HS	428	};
39c2bd78 HS	429
	430	spi0: spi@20070000 {
	431	compatible = "rockchip,rk3066-spi";
	432	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	433	clock-names = "spiclk", "apb_pclk";
	434	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	435	reg = <0x20070000 0x1000>;
	436	#address-cells = <1>;
	437	#size-cells = <0>;
b3e3a7b2 JC	438	dmas = <&dmac2 10>, <&dmac2 11>;
b3e3a7b2 JC	439	dma-names = "tx", "rx";
39c2bd78 HS	440	status = "disabled";
	441	};
	442
	443	spi1: spi@20074000 {
	444	compatible = "rockchip,rk3066-spi";
	445	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	446	clock-names = "spiclk", "apb_pclk";
	447	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	448	reg = <0x20074000 0x1000>;
	449	#address-cells = <1>;
	450	#size-cells = <0>;
b3e3a7b2 JC	451	dmas = <&dmac2 12>, <&dmac2 13>;
b3e3a7b2 JC	452	dma-names = "tx", "rx";
39c2bd78 HS	453	status = "disabled";
39c2bd78 HS	454	};
f75efdd7	455	};