]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/boot/dts/rv1108.dtsi
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: rockchip: add BQ Edison 2 QC devicetree
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / rv1108.dtsi
CommitLineData
fce152a6 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
60101816
AY		 2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
7e2a9035 6#include <dt-bindings/clock/rv1108-cru.h>
60101816 7#include <dt-bindings/pinctrl/rockchip.h>
f6d3f1e8 8#include <dt-bindings/thermal/thermal.h>
60101816
AY		 9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
96800f03 13 compatible = "rockchip,rv1108";
60101816
AY		 14
15 interrupt-parent = <&gic>;
16
17 aliases {
32cb77a2
AY		 18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
60101816
AY		 22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
84ea3a13 35 clock-latency = <40000>;
38baa5a9 36 clocks = <&cru ARMCLK>;
f6d3f1e8
RH		 37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
38baa5a9
AY		 39 operating-points-v2 = <&cpu_opp_table>;
40 };
41 };
42
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
45
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
50 };
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
55 };
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
60 };
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
60101816
AY		 65 };
66 };
67
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
c955b7ae 70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 71 };
72
73 timer {
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
507bc2f5 77 arm,cpu-registers-not-fw-configured;
60101816
AY		 78 clock-frequency = <24000000>;
79 };
80
81 xin24m: oscillator {
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
86 };
87
88 amba {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 pdma: pdma@102a0000 {
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
98 #dma-cells = <1>;
99 arm,pl330-broken-no-flushp;
100 clocks = <&cru ACLK_DMAC>;
101 clock-names = "apb_pclk";
102 };
103 };
104
105 bus_intmem@10080000 {
106 compatible = "mmio-sram";
107 reg = <0x10080000 0x2000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x10080000 0x2000>;
111 };
112
113 uart2: serial@10210000 {
96800f03 114 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 115 reg = <0x10210000 0x100>;
116 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
117 reg-shift = <2>;
118 reg-io-width = <4>;
119 clock-frequency = <24000000>;
120 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
121 clock-names = "baudclk", "apb_pclk";
7d2cecb0
OS		 122 dmas = <&pdma 6>, <&pdma 7>;
123 #dma-cells = <2>;
60101816
AY		 124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
126 status = "disabled";
127 };
128
129 uart1: serial@10220000 {
96800f03 130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 131 reg = <0x10220000 0x100>;
132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 clock-frequency = <24000000>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 clock-names = "baudclk", "apb_pclk";
7d2cecb0
OS		 138 dmas = <&pdma 4>, <&pdma 5>;
139 #dma-cells = <2>;
60101816
AY		 140 pinctrl-names = "default";
141 pinctrl-0 = <&uart1_xfer>;
142 status = "disabled";
143 };
144
145 uart0: serial@10230000 {
96800f03 146 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 147 reg = <0x10230000 0x100>;
148 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
149 reg-shift = <2>;
150 reg-io-width = <4>;
151 clock-frequency = <24000000>;
152 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
153 clock-names = "baudclk", "apb_pclk";
7d2cecb0
OS		 154 dmas = <&pdma 2>, <&pdma 3>;
155 #dma-cells = <2>;
60101816
AY		 156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
158 status = "disabled";
159 };
160
32cb77a2
AY		 161 i2c1: i2c@10240000 {
162 compatible = "rockchip,rv1108-i2c";
163 reg = <0x10240000 0x1000>;
164 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
168 clock-names = "i2c", "pclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c1_xfer>;
171 rockchip,grf = <&grf>;
172 status = "disabled";
173 };
174
175 i2c2: i2c@10250000 {
176 compatible = "rockchip,rv1108-i2c";
177 reg = <0x10250000 0x1000>;
178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
182 clock-names = "i2c", "pclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&i2c2m1_xfer>;
185 rockchip,grf = <&grf>;
186 status = "disabled";
187 };
188
189 i2c3: i2c@10260000 {
190 compatible = "rockchip,rv1108-i2c";
191 reg = <0x10260000 0x1000>;
192 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
196 clock-names = "i2c", "pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&i2c3_xfer>;
199 rockchip,grf = <&grf>;
200 status = "disabled";
201 };
202
4d1dc2d1
AY		 203 spi: spi@10270000 {
204 compatible = "rockchip,rv1108-spi";
205 reg = <0x10270000 0x1000>;
206 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
208 clock-names = "spiclk", "apb_pclk";
209 dmas = <&pdma 8>, <&pdma 9>;
210 #dma-cells = <2>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 status = "disabled";
214 };
215
0c2d34aa
AY		 216 pwm4: pwm@10280000 {
217 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
218 reg = <0x10280000 0x10>;
219 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
221 clock-names = "pwm", "pclk";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pwm4_pin>;
224 #pwm-cells = <3>;
225 status = "disabled";
226 };
227
228 pwm5: pwm@10280010 {
229 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
230 reg = <0x10280010 0x10>;
231 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
233 clock-names = "pwm", "pclk";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pwm5_pin>;
236 #pwm-cells = <3>;
237 status = "disabled";
238 };
239
240 pwm6: pwm@10280020 {
241 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
242 reg = <0x10280020 0x10>;
243 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
245 clock-names = "pwm", "pclk";
246 pinctrl-names = "default";
247 pinctrl-0 = <&pwm6_pin>;
248 #pwm-cells = <3>;
249 status = "disabled";
250 };
251
252 pwm7: pwm@10280030 {
253 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
254 reg = <0x10280030 0x10>;
255 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
257 clock-names = "pwm", "pclk";
258 pinctrl-names = "default";
259 pinctrl-0 = <&pwm7_pin>;
260 #pwm-cells = <3>;
261 status = "disabled";
262 };
263
60101816 264 grf: syscon@10300000 {
24f9f5bb 265 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
60101816 266 reg = <0x10300000 0x1000>;
24f9f5bb
FW		 267 #address-cells = <1>;
268 #size-cells = <1>;
269
270 u2phy: usb2-phy@100 {
271 compatible = "rockchip,rv1108-usb2phy";
272 reg = <0x100 0x0c>;
273 clocks = <&cru SCLK_USBPHY>;
274 clock-names = "phyclk";
275 #clock-cells = <0>;
276 clock-output-names = "usbphy";
277 rockchip,usbgrf = <&usbgrf>;
278 status = "disabled";
279
280 u2phy_otg: otg-port {
281 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
282 interrupt-names = "otg-mux";
283 #phy-cells = <0>;
284 status = "disabled";
285 };
286
287 u2phy_host: host-port {
288 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-names = "linestate";
290 #phy-cells = <0>;
291 status = "disabled";
292 };
293 };
60101816
AY		 294 };
295
5584b967
AY		 296 watchdog: wdt@10360000 {
297 compatible = "snps,dw-wdt";
298 reg = <0x10360000 0x100>;
299 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru PCLK_WDT>;
301 clock-names = "pclk_wdt";
302 status = "disabled";
303 };
304
f6d3f1e8
RH		 305 thermal-zones {
306 soc_thermal: soc-thermal {
307 polling-delay-passive = <20>;
308 polling-delay = <1000>;
309 sustainable-power = <50>;
310 thermal-sensors = <&tsadc 0>;
311
312 trips {
313 threshold: trip-point0 {
314 temperature = <70000>;
315 hysteresis = <2000>;
316 type = "passive";
317 };
318 target: trip-point1 {
319 temperature = <85000>;
320 hysteresis = <2000>;
321 type = "passive";
322 };
323 soc_crit: soc-crit {
324 temperature = <95000>;
325 hysteresis = <2000>;
326 type = "critical";
327 };
328 };
329
330 cooling-maps {
331 map0 {
332 trip = <&target>;
333 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
334 contribution = <4096>;
335 };
336 };
337 };
338 };
339
fb03abbc
RH		 340 tsadc: tsadc@10370000 {
341 compatible = "rockchip,rv1108-tsadc";
342 reg = <0x10370000 0x100>;
343 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
344 assigned-clocks = <&cru SCLK_TSADC>;
345 assigned-clock-rates = <750000>;
346 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
347 clock-names = "tsadc", "apb_pclk";
348 pinctrl-names = "init", "default", "sleep";
349 pinctrl-0 = <&otp_gpio>;
350 pinctrl-1 = <&otp_out>;
351 pinctrl-2 = <&otp_gpio>;
352 resets = <&cru SRST_TSADC>;
353 reset-names = "tsadc-apb";
354 rockchip,hw-tshut-temp = <120000>;
355 #thermal-sensor-cells = <1>;
356 status = "disabled";
357 };
358
0e6ff96f
AY		 359 adc: adc@1038c000 {
360 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
361 reg = <0x1038c000 0x100>;
362 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
363 #io-channel-cells = <1>;
364 clock-frequency = <1000000>;
365 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
366 clock-names = "saradc", "apb_pclk";
367 status = "disabled";
368 };
369
32cb77a2
AY		 370 i2c0: i2c@20000000 {
371 compatible = "rockchip,rv1108-i2c";
372 reg = <0x20000000 0x1000>;
373 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
377 clock-names = "i2c", "pclk";
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c0_xfer>;
380 rockchip,grf = <&grf>;
381 status = "disabled";
382 };
383
0c2d34aa
AY		 384 pwm0: pwm@20040000 {
385 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
386 reg = <0x20040000 0x10>;
387 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
389 clock-names = "pwm", "pclk";
390 pinctrl-names = "default";
391 pinctrl-0 = <&pwm0_pin>;
392 #pwm-cells = <3>;
393 status = "disabled";
394 };
395
396 pwm1: pwm@20040010 {
397 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
398 reg = <0x20040010 0x10>;
399 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
401 clock-names = "pwm", "pclk";
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm1_pin>;
404 #pwm-cells = <3>;
405 status = "disabled";
406 };
407
408 pwm2: pwm@20040020 {
409 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
410 reg = <0x20040020 0x10>;
411 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
413 clock-names = "pwm", "pclk";
414 pinctrl-names = "default";
415 pinctrl-0 = <&pwm2_pin>;
416 #pwm-cells = <3>;
417 status = "disabled";
418 };
419
420 pwm3: pwm@20040030 {
421 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
422 reg = <0x20040030 0x10>;
423 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
425 clock-names = "pwm", "pclk";
426 pinctrl-names = "default";
427 pinctrl-0 = <&pwm3_pin>;
428 #pwm-cells = <3>;
429 status = "disabled";
430 };
431
60101816 432 pmugrf: syscon@20060000 {
96800f03 433 compatible = "rockchip,rv1108-pmugrf", "syscon";
60101816
AY		 434 reg = <0x20060000 0x1000>;
435 };
436
24f9f5bb
FW		 437 usbgrf: syscon@202a0000 {
438 compatible = "rockchip,rv1108-usbgrf", "syscon";
439 reg = <0x202a0000 0x1000>;
440 };
441
60101816 442 cru: clock-controller@20200000 {
96800f03 443 compatible = "rockchip,rv1108-cru";
60101816
AY		 444 reg = <0x20200000 0x1000>;
445 rockchip,grf = <&grf>;
446 #clock-cells = <1>;
447 #reset-cells = <1>;
448 };
449
450 emmc: dwmmc@30110000 {
96800f03 451 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 452 reg = <0x30110000 0x4000>;
453 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 454 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
455 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
456 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
457 fifo-depth = <0x100>;
0f4dc7e1 458 max-frequency = <150000000>;
60101816
AY		 459 status = "disabled";
460 };
461
462 sdio: dwmmc@30120000 {
96800f03 463 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 464 reg = <0x30120000 0x4000>;
465 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 466 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
467 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
468 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
469 fifo-depth = <0x100>;
0f4dc7e1 470 max-frequency = <150000000>;
60101816
AY		 471 status = "disabled";
472 };
473
474 sdmmc: dwmmc@30130000 {
96800f03 475 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 476 reg = <0x30130000 0x4000>;
477 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 478 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
479 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
480 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
481 fifo-depth = <0x100>;
0f4dc7e1 482 max-frequency = <100000000>;
d416364f
AY		 483 pinctrl-names = "default";
484 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
60101816
AY		 485 status = "disabled";
486 };
487
24f9f5bb
FW		 488 usb_host_ehci: usb@30140000 {
489 compatible = "generic-ehci";
490 reg = <0x30140000 0x20000>;
491 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&cru HCLK_HOST0>, <&u2phy>;
493 clock-names = "usbhost", "utmi";
494 phys = <&u2phy_host>;
495 phy-names = "usb";
496 status = "disabled";
497 };
498
499 usb_host_ohci: usb@30160000 {
500 compatible = "generic-ohci";
501 reg = <0x30160000 0x20000>;
502 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru HCLK_HOST0>, <&u2phy>;
504 clock-names = "usbhost", "utmi";
505 phys = <&u2phy_host>;
506 phy-names = "usb";
507 status = "disabled";
508 };
509
510 usb_otg: usb@30180000 {
511 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
512 "snps,dwc2";
513 reg = <0x30180000 0x40000>;
514 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cru HCLK_OTG>;
516 clock-names = "otg";
517 dr_mode = "otg";
518 g-np-tx-fifo-size = <16>;
519 g-rx-fifo-size = <280>;
520 g-tx-fifo-size = <256 128 128 64 32 16>;
521 g-use-dma;
522 phys = <&u2phy_otg>;
523 phy-names = "usb2-phy";
524 status = "disabled";
525 };
526
7d015bd7
OS		 527 gmac: eth@30200000 {
528 compatible = "rockchip,rv1108-gmac";
529 reg = <0x30200000 0x10000>;
530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
532 interrupt-names = "macirq", "eth_wake_irq";
533 clocks = <&cru SCLK_MAC>,
534 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
535 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
536 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
537 clock-names = "stmmaceth",
538 "mac_clk_rx", "mac_clk_tx",
539 "clk_mac_ref", "clk_mac_refout",
540 "aclk_mac", "pclk_mac";
541 /* rv1108 only supports an rmii interface */
542 phy-mode = "rmii";
543 pinctrl-names = "default";
544 pinctrl-0 = <&rmii_pins>;
545 rockchip,grf = <&grf>;
546 status = "disabled";
547 };
548
60101816
AY		 549 gic: interrupt-controller@32010000 {
550 compatible = "arm,gic-400";
551 interrupt-controller;
552 #interrupt-cells = <3>;
553 #address-cells = <0>;
554
555 reg = <0x32011000 0x1000>,
387720c9 556 <0x32012000 0x2000>,
60101816
AY		 557 <0x32014000 0x2000>,
558 <0x32016000 0x2000>;
559 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
560 };
561
562 pinctrl: pinctrl {
b9c6dcab 563 compatible = "rockchip,rv1108-pinctrl";
60101816
AY		 564 rockchip,grf = <&grf>;
565 rockchip,pmu = <&pmugrf>;
566 #address-cells = <1>;
567 #size-cells = <1>;
568 ranges;
569
570 gpio0: gpio0@20030000 {
571 compatible = "rockchip,gpio-bank";
572 reg = <0x20030000 0x100>;
573 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 574 clocks = <&cru PCLK_GPIO0_PMU>;
60101816
AY		 575
576 gpio-controller;
577 #gpio-cells = <2>;
578
579 interrupt-controller;
580 #interrupt-cells = <2>;
581 };
582
583 gpio1: gpio1@10310000 {
584 compatible = "rockchip,gpio-bank";
585 reg = <0x10310000 0x100>;
586 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 587 clocks = <&cru PCLK_GPIO1>;
60101816
AY		 588
589 gpio-controller;
590 #gpio-cells = <2>;
591
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 };
595
596 gpio2: gpio2@10320000 {
597 compatible = "rockchip,gpio-bank";
598 reg = <0x10320000 0x100>;
599 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 600 clocks = <&cru PCLK_GPIO2>;
60101816
AY		 601
602 gpio-controller;
603 #gpio-cells = <2>;
604
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 };
608
609 gpio3: gpio3@10330000 {
610 compatible = "rockchip,gpio-bank";
611 reg = <0x10330000 0x100>;
612 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 613 clocks = <&cru PCLK_GPIO3>;
60101816
AY		 614
615 gpio-controller;
616 #gpio-cells = <2>;
617
618 interrupt-controller;
619 #interrupt-cells = <2>;
620 };
621
622 pcfg_pull_up: pcfg-pull-up {
623 bias-pull-up;
624 };
625
626 pcfg_pull_down: pcfg-pull-down {
627 bias-pull-down;
628 };
629
630 pcfg_pull_none: pcfg-pull-none {
631 bias-disable;
632 };
633
634 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
635 drive-strength = <8>;
636 };
637
638 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
639 drive-strength = <12>;
640 };
641
32cb77a2
AY		 642 pcfg_pull_none_smt: pcfg-pull-none-smt {
643 bias-disable;
644 input-schmitt-enable;
645 };
646
60101816
AY		 647 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
648 bias-pull-up;
649 drive-strength = <8>;
650 };
651
652 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
653 drive-strength = <4>;
654 };
655
656 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
657 bias-pull-up;
658 drive-strength = <4>;
659 };
660
661 pcfg_output_high: pcfg-output-high {
662 output-high;
663 };
664
665 pcfg_output_low: pcfg-output-low {
666 output-low;
667 };
668
669 pcfg_input_high: pcfg-input-high {
670 bias-pull-up;
671 input-enable;
672 };
673
bdd98681
OS		 674 emmc {
675 emmc_bus8: emmc-bus8 {
676 rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
677 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
678 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
679 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
680 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
681 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
682 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
683 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
684 };
685
686 emmc_clk: emmc-clk {
687 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
688 };
689
690 emmc_cmd: emmc-cmd {
691 rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
692 };
693 };
694
7d015bd7
OS		 695 gmac {
696 rmii_pins: rmii-pins {
697 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
698 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
699 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
700 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
701 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
702 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
703 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
704 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
705 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
706 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
707 };
708 };
709
32cb77a2
AY		 710 i2c0 {
711 i2c0_xfer: i2c0-xfer {
712 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
713 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
714 };
715 };
716
60101816
AY		 717 i2c1 {
718 i2c1_xfer: i2c1-xfer {
719 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
720 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
721 };
722 };
723
724 i2c2m1 {
725 i2c2m1_xfer: i2c2m1-xfer {
726 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
727 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
728 };
729
730 i2c2m1_gpio: i2c2m1-gpio {
731 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
732 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
733 };
734 };
735
736 i2c2m05v {
737 i2c2m05v_xfer: i2c2m05v-xfer {
738 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
739 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
740 };
741
742 i2c2m05v_gpio: i2c2m05v-gpio {
743 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
744 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
745 };
746 };
747
748 i2c3 {
749 i2c3_xfer: i2c3-xfer {
750 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
751 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
752 };
753 };
754
0c2d34aa
AY		 755 pwm0 {
756 pwm0_pin: pwm0-pin {
757 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
758 };
759 };
760
761 pwm1 {
762 pwm1_pin: pwm1-pin {
763 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
764 };
765 };
766
767 pwm2 {
768 pwm2_pin: pwm2-pin {
769 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
770 };
771 };
772
773 pwm3 {
774 pwm3_pin: pwm3-pin {
775 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
776 };
777 };
778
779 pwm4 {
780 pwm4_pin: pwm4-pin {
781 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
782 };
783 };
784
785 pwm5 {
786 pwm5_pin: pwm5-pin {
787 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
788 };
789 };
790
791 pwm6 {
792 pwm6_pin: pwm6-pin {
793 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
794 };
795 };
796
797 pwm7 {
798 pwm7_pin: pwm7-pin {
799 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
800 };
801 };
802
c458e1b5
JC		 803 sdmmc {
804 sdmmc_clk: sdmmc-clk {
805 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
806 };
807
808 sdmmc_cmd: sdmmc-cmd {
809 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
810 };
811
812 sdmmc_cd: sdmmc-cd {
813 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
814 };
815
816 sdmmc_bus1: sdmmc-bus1 {
817 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
818 };
819
820 sdmmc_bus4: sdmmc-bus4 {
821 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
822 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
823 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
824 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
825 };
826 };
827
fb03abbc
RH		 828 tsadc {
829 otp_out: otp-out {
830 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
831 };
832
833 otp_gpio: otp-gpio {
834 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
835 };
836 };
837
60101816
AY		 838 uart0 {
839 uart0_xfer: uart0-xfer {
840 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
841 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
842 };
843
844 uart0_cts: uart0-cts {
845 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
846 };
847
848 uart0_rts: uart0-rts {
849 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
850 };
851
852 uart0_rts_gpio: uart0-rts-gpio {
853 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
854 };
855 };
856
857 uart1 {
858 uart1_xfer: uart1-xfer {
859 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
860 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
861 };
862
863 uart1_cts: uart1-cts {
864 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
865 };
866
867 uart1_rts: uart1-rts {
868 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
869 };
870 };
871
872 uart2m0 {
873 uart2m0_xfer: uart2m0-xfer {
874 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
875 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
876 };
877 };
878
879 uart2m1 {
880 uart2m1_xfer: uart2m1-xfer {
881 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
882 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
883 };
884 };
885
886 uart2_5v {
887 uart2_5v_cts: uart2_5v-cts {
888 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
889 };
890
891 uart2_5v_rts: uart2_5v-rts {
892 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
893 };
894 };
895 };
896};
Ubuntu Hirsute Linux kernel mirror