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dt-bindings: update grf-binding for rv1108 SoCs
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / rv1108.dtsi
CommitLineData
60101816
AY		 1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
7e2a9035 44#include <dt-bindings/clock/rv1108-cru.h>
60101816
AY		 45#include <dt-bindings/pinctrl/rockchip.h>
46/ {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
96800f03 50 compatible = "rockchip,rv1108";
60101816
AY		 51
52 interrupt-parent = <&gic>;
53
54 aliases {
32cb77a2
AY		 55 i2c0 = &i2c0;
56 i2c1 = &i2c1;
57 i2c2 = &i2c2;
58 i2c3 = &i2c3;
60101816
AY		 59 serial0 = &uart0;
60 serial1 = &uart1;
61 serial2 = &uart2;
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 cpu0: cpu@f00 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a7";
71 reg = <0xf00>;
38baa5a9
AY		 72 clocks = <&cru ARMCLK>;
73 operating-points-v2 = <&cpu_opp_table>;
74 };
75 };
76
77 cpu_opp_table: opp_table {
78 compatible = "operating-points-v2";
79
80 opp-408000000 {
81 opp-hz = /bits/ 64 <408000000>;
82 opp-microvolt = <975000>;
83 clock-latency-ns = <40000>;
84 };
85 opp-600000000 {
86 opp-hz = /bits/ 64 <600000000>;
87 opp-microvolt = <975000>;
88 clock-latency-ns = <40000>;
89 };
90 opp-816000000 {
91 opp-hz = /bits/ 64 <816000000>;
92 opp-microvolt = <1025000>;
93 clock-latency-ns = <40000>;
94 };
95 opp-1008000000 {
96 opp-hz = /bits/ 64 <1008000000>;
97 opp-microvolt = <1150000>;
98 clock-latency-ns = <40000>;
60101816
AY		 99 };
100 };
101
102 arm-pmu {
103 compatible = "arm,cortex-a7-pmu";
104 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
105 };
106
107 timer {
108 compatible = "arm,armv7-timer";
109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
110 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
111 clock-frequency = <24000000>;
112 };
113
114 xin24m: oscillator {
115 compatible = "fixed-clock";
116 clock-frequency = <24000000>;
117 clock-output-names = "xin24m";
118 #clock-cells = <0>;
119 };
120
121 amba {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
126
127 pdma: pdma@102a0000 {
128 compatible = "arm,pl330", "arm,primecell";
129 reg = <0x102a0000 0x4000>;
130 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
131 #dma-cells = <1>;
132 arm,pl330-broken-no-flushp;
133 clocks = <&cru ACLK_DMAC>;
134 clock-names = "apb_pclk";
135 };
136 };
137
138 bus_intmem@10080000 {
139 compatible = "mmio-sram";
140 reg = <0x10080000 0x2000>;
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges = <0 0x10080000 0x2000>;
144 };
145
146 uart2: serial@10210000 {
96800f03 147 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 148 reg = <0x10210000 0x100>;
149 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
150 reg-shift = <2>;
151 reg-io-width = <4>;
152 clock-frequency = <24000000>;
153 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
154 clock-names = "baudclk", "apb_pclk";
155 pinctrl-names = "default";
156 pinctrl-0 = <&uart2m0_xfer>;
157 status = "disabled";
158 };
159
160 uart1: serial@10220000 {
96800f03 161 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 162 reg = <0x10220000 0x100>;
163 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
164 reg-shift = <2>;
165 reg-io-width = <4>;
166 clock-frequency = <24000000>;
167 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
168 clock-names = "baudclk", "apb_pclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&uart1_xfer>;
171 status = "disabled";
172 };
173
174 uart0: serial@10230000 {
96800f03 175 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 176 reg = <0x10230000 0x100>;
177 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
178 reg-shift = <2>;
179 reg-io-width = <4>;
180 clock-frequency = <24000000>;
181 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
182 clock-names = "baudclk", "apb_pclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
185 status = "disabled";
186 };
187
32cb77a2
AY		 188 i2c1: i2c@10240000 {
189 compatible = "rockchip,rv1108-i2c";
190 reg = <0x10240000 0x1000>;
191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
195 clock-names = "i2c", "pclk";
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2c1_xfer>;
198 rockchip,grf = <&grf>;
199 status = "disabled";
200 };
201
202 i2c2: i2c@10250000 {
203 compatible = "rockchip,rv1108-i2c";
204 reg = <0x10250000 0x1000>;
205 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
209 clock-names = "i2c", "pclk";
210 pinctrl-names = "default";
211 pinctrl-0 = <&i2c2m1_xfer>;
212 rockchip,grf = <&grf>;
213 status = "disabled";
214 };
215
216 i2c3: i2c@10260000 {
217 compatible = "rockchip,rv1108-i2c";
218 reg = <0x10260000 0x1000>;
219 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
223 clock-names = "i2c", "pclk";
224 pinctrl-names = "default";
225 pinctrl-0 = <&i2c3_xfer>;
226 rockchip,grf = <&grf>;
227 status = "disabled";
228 };
229
4d1dc2d1
AY		 230 spi: spi@10270000 {
231 compatible = "rockchip,rv1108-spi";
232 reg = <0x10270000 0x1000>;
233 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
235 clock-names = "spiclk", "apb_pclk";
236 dmas = <&pdma 8>, <&pdma 9>;
237 #dma-cells = <2>;
238 #address-cells = <1>;
239 #size-cells = <0>;
240 status = "disabled";
241 };
242
0c2d34aa
AY		 243 pwm4: pwm@10280000 {
244 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
245 reg = <0x10280000 0x10>;
246 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
248 clock-names = "pwm", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&pwm4_pin>;
251 #pwm-cells = <3>;
252 status = "disabled";
253 };
254
255 pwm5: pwm@10280010 {
256 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
257 reg = <0x10280010 0x10>;
258 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
260 clock-names = "pwm", "pclk";
261 pinctrl-names = "default";
262 pinctrl-0 = <&pwm5_pin>;
263 #pwm-cells = <3>;
264 status = "disabled";
265 };
266
267 pwm6: pwm@10280020 {
268 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
269 reg = <0x10280020 0x10>;
270 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
272 clock-names = "pwm", "pclk";
273 pinctrl-names = "default";
274 pinctrl-0 = <&pwm6_pin>;
275 #pwm-cells = <3>;
276 status = "disabled";
277 };
278
279 pwm7: pwm@10280030 {
280 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
281 reg = <0x10280030 0x10>;
282 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
284 clock-names = "pwm", "pclk";
285 pinctrl-names = "default";
286 pinctrl-0 = <&pwm7_pin>;
287 #pwm-cells = <3>;
288 status = "disabled";
289 };
290
60101816 291 grf: syscon@10300000 {
96800f03 292 compatible = "rockchip,rv1108-grf", "syscon";
60101816
AY		 293 reg = <0x10300000 0x1000>;
294 };
295
5584b967
AY		 296 watchdog: wdt@10360000 {
297 compatible = "snps,dw-wdt";
298 reg = <0x10360000 0x100>;
299 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru PCLK_WDT>;
301 clock-names = "pclk_wdt";
302 status = "disabled";
303 };
304
0e6ff96f
AY		 305 adc: adc@1038c000 {
306 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
307 reg = <0x1038c000 0x100>;
308 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
309 #io-channel-cells = <1>;
310 clock-frequency = <1000000>;
311 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
312 clock-names = "saradc", "apb_pclk";
313 status = "disabled";
314 };
315
32cb77a2
AY		 316 i2c0: i2c@20000000 {
317 compatible = "rockchip,rv1108-i2c";
318 reg = <0x20000000 0x1000>;
319 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
323 clock-names = "i2c", "pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c0_xfer>;
326 rockchip,grf = <&grf>;
327 status = "disabled";
328 };
329
0c2d34aa
AY		 330 pwm0: pwm@20040000 {
331 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
332 reg = <0x20040000 0x10>;
333 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
335 clock-names = "pwm", "pclk";
336 pinctrl-names = "default";
337 pinctrl-0 = <&pwm0_pin>;
338 #pwm-cells = <3>;
339 status = "disabled";
340 };
341
342 pwm1: pwm@20040010 {
343 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
344 reg = <0x20040010 0x10>;
345 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
347 clock-names = "pwm", "pclk";
348 pinctrl-names = "default";
349 pinctrl-0 = <&pwm1_pin>;
350 #pwm-cells = <3>;
351 status = "disabled";
352 };
353
354 pwm2: pwm@20040020 {
355 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
356 reg = <0x20040020 0x10>;
357 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
359 clock-names = "pwm", "pclk";
360 pinctrl-names = "default";
361 pinctrl-0 = <&pwm2_pin>;
362 #pwm-cells = <3>;
363 status = "disabled";
364 };
365
366 pwm3: pwm@20040030 {
367 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
368 reg = <0x20040030 0x10>;
369 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
371 clock-names = "pwm", "pclk";
372 pinctrl-names = "default";
373 pinctrl-0 = <&pwm3_pin>;
374 #pwm-cells = <3>;
375 status = "disabled";
376 };
377
60101816 378 pmugrf: syscon@20060000 {
96800f03 379 compatible = "rockchip,rv1108-pmugrf", "syscon";
60101816
AY		 380 reg = <0x20060000 0x1000>;
381 };
382
383 cru: clock-controller@20200000 {
96800f03 384 compatible = "rockchip,rv1108-cru";
60101816
AY		 385 reg = <0x20200000 0x1000>;
386 rockchip,grf = <&grf>;
387 #clock-cells = <1>;
388 #reset-cells = <1>;
389 };
390
391 emmc: dwmmc@30110000 {
96800f03 392 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 393 reg = <0x30110000 0x4000>;
394 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 395 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
396 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
397 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
398 fifo-depth = <0x100>;
0f4dc7e1 399 max-frequency = <150000000>;
60101816
AY		 400 status = "disabled";
401 };
402
403 sdio: dwmmc@30120000 {
96800f03 404 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 405 reg = <0x30120000 0x4000>;
406 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 407 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
408 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
409 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
410 fifo-depth = <0x100>;
0f4dc7e1 411 max-frequency = <150000000>;
60101816
AY		 412 status = "disabled";
413 };
414
415 sdmmc: dwmmc@30130000 {
96800f03 416 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 417 reg = <0x30130000 0x4000>;
418 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 419 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
420 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
421 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
422 fifo-depth = <0x100>;
0f4dc7e1 423 max-frequency = <100000000>;
d416364f
AY		 424 pinctrl-names = "default";
425 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
60101816
AY		 426 status = "disabled";
427 };
428
429 gic: interrupt-controller@32010000 {
430 compatible = "arm,gic-400";
431 interrupt-controller;
432 #interrupt-cells = <3>;
433 #address-cells = <0>;
434
435 reg = <0x32011000 0x1000>,
387720c9 436 <0x32012000 0x2000>,
60101816
AY		 437 <0x32014000 0x2000>,
438 <0x32016000 0x2000>;
439 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
440 };
441
442 pinctrl: pinctrl {
b9c6dcab 443 compatible = "rockchip,rv1108-pinctrl";
60101816
AY		 444 rockchip,grf = <&grf>;
445 rockchip,pmu = <&pmugrf>;
446 #address-cells = <1>;
447 #size-cells = <1>;
448 ranges;
449
450 gpio0: gpio0@20030000 {
451 compatible = "rockchip,gpio-bank";
452 reg = <0x20030000 0x100>;
453 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&xin24m>;
455
456 gpio-controller;
457 #gpio-cells = <2>;
458
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 };
462
463 gpio1: gpio1@10310000 {
464 compatible = "rockchip,gpio-bank";
465 reg = <0x10310000 0x100>;
466 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&xin24m>;
468
469 gpio-controller;
470 #gpio-cells = <2>;
471
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 };
475
476 gpio2: gpio2@10320000 {
477 compatible = "rockchip,gpio-bank";
478 reg = <0x10320000 0x100>;
479 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&xin24m>;
481
482 gpio-controller;
483 #gpio-cells = <2>;
484
485 interrupt-controller;
486 #interrupt-cells = <2>;
487 };
488
489 gpio3: gpio3@10330000 {
490 compatible = "rockchip,gpio-bank";
491 reg = <0x10330000 0x100>;
492 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&xin24m>;
494
495 gpio-controller;
496 #gpio-cells = <2>;
497
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 };
501
502 pcfg_pull_up: pcfg-pull-up {
503 bias-pull-up;
504 };
505
506 pcfg_pull_down: pcfg-pull-down {
507 bias-pull-down;
508 };
509
510 pcfg_pull_none: pcfg-pull-none {
511 bias-disable;
512 };
513
514 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
515 drive-strength = <8>;
516 };
517
518 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
519 drive-strength = <12>;
520 };
521
32cb77a2
AY		 522 pcfg_pull_none_smt: pcfg-pull-none-smt {
523 bias-disable;
524 input-schmitt-enable;
525 };
526
60101816
AY		 527 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
528 bias-pull-up;
529 drive-strength = <8>;
530 };
531
532 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
533 drive-strength = <4>;
534 };
535
536 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
537 bias-pull-up;
538 drive-strength = <4>;
539 };
540
541 pcfg_output_high: pcfg-output-high {
542 output-high;
543 };
544
545 pcfg_output_low: pcfg-output-low {
546 output-low;
547 };
548
549 pcfg_input_high: pcfg-input-high {
550 bias-pull-up;
551 input-enable;
552 };
553
32cb77a2
AY		 554 i2c0 {
555 i2c0_xfer: i2c0-xfer {
556 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
557 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
558 };
559 };
560
60101816
AY		 561 i2c1 {
562 i2c1_xfer: i2c1-xfer {
563 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
564 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
565 };
566 };
567
568 i2c2m1 {
569 i2c2m1_xfer: i2c2m1-xfer {
570 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
571 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
572 };
573
574 i2c2m1_gpio: i2c2m1-gpio {
575 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
576 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
577 };
578 };
579
580 i2c2m05v {
581 i2c2m05v_xfer: i2c2m05v-xfer {
582 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
583 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
584 };
585
586 i2c2m05v_gpio: i2c2m05v-gpio {
587 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
588 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
589 };
590 };
591
592 i2c3 {
593 i2c3_xfer: i2c3-xfer {
594 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
595 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
596 };
597 };
598
0c2d34aa
AY		 599 pwm0 {
600 pwm0_pin: pwm0-pin {
601 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
602 };
603 };
604
605 pwm1 {
606 pwm1_pin: pwm1-pin {
607 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
608 };
609 };
610
611 pwm2 {
612 pwm2_pin: pwm2-pin {
613 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
614 };
615 };
616
617 pwm3 {
618 pwm3_pin: pwm3-pin {
619 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
620 };
621 };
622
623 pwm4 {
624 pwm4_pin: pwm4-pin {
625 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
626 };
627 };
628
629 pwm5 {
630 pwm5_pin: pwm5-pin {
631 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
632 };
633 };
634
635 pwm6 {
636 pwm6_pin: pwm6-pin {
637 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
638 };
639 };
640
641 pwm7 {
642 pwm7_pin: pwm7-pin {
643 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
644 };
645 };
646
c458e1b5
JC		 647 sdmmc {
648 sdmmc_clk: sdmmc-clk {
649 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
650 };
651
652 sdmmc_cmd: sdmmc-cmd {
653 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
654 };
655
656 sdmmc_cd: sdmmc-cd {
657 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
658 };
659
660 sdmmc_bus1: sdmmc-bus1 {
661 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
662 };
663
664 sdmmc_bus4: sdmmc-bus4 {
665 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
666 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
667 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
668 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
669 };
670 };
671
60101816
AY		 672 uart0 {
673 uart0_xfer: uart0-xfer {
674 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
675 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
676 };
677
678 uart0_cts: uart0-cts {
679 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
680 };
681
682 uart0_rts: uart0-rts {
683 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
684 };
685
686 uart0_rts_gpio: uart0-rts-gpio {
687 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
688 };
689 };
690
691 uart1 {
692 uart1_xfer: uart1-xfer {
693 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
694 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
695 };
696
697 uart1_cts: uart1-cts {
698 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
699 };
700
701 uart1_rts: uart1-rts {
702 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
703 };
704 };
705
706 uart2m0 {
707 uart2m0_xfer: uart2m0-xfer {
708 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
709 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
710 };
711 };
712
713 uart2m1 {
714 uart2m1_xfer: uart2m1-xfer {
715 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
716 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
717 };
718 };
719
720 uart2_5v {
721 uart2_5v_cts: uart2_5v-cts {
722 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
723 };
724
725 uart2_5v_rts: uart2_5v-rts {
726 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
727 };
728 };
729 };
730};
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