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ARM: dts: rockchip: add rk322x iommu nodes
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / rv1108.dtsi
CommitLineData
60101816
AY		 1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
7e2a9035 44#include <dt-bindings/clock/rv1108-cru.h>
60101816
AY		 45#include <dt-bindings/pinctrl/rockchip.h>
46/ {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
96800f03 50 compatible = "rockchip,rv1108";
60101816
AY		 51
52 interrupt-parent = <&gic>;
53
54 aliases {
32cb77a2
AY		 55 i2c0 = &i2c0;
56 i2c1 = &i2c1;
57 i2c2 = &i2c2;
58 i2c3 = &i2c3;
60101816
AY		 59 serial0 = &uart0;
60 serial1 = &uart1;
61 serial2 = &uart2;
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 cpu0: cpu@f00 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a7";
71 reg = <0xf00>;
72 };
73 };
74
75 arm-pmu {
76 compatible = "arm,cortex-a7-pmu";
77 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
78 };
79
80 timer {
81 compatible = "arm,armv7-timer";
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
84 clock-frequency = <24000000>;
85 };
86
87 xin24m: oscillator {
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
90 clock-output-names = "xin24m";
91 #clock-cells = <0>;
92 };
93
94 amba {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99
100 pdma: pdma@102a0000 {
101 compatible = "arm,pl330", "arm,primecell";
102 reg = <0x102a0000 0x4000>;
103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
104 #dma-cells = <1>;
105 arm,pl330-broken-no-flushp;
106 clocks = <&cru ACLK_DMAC>;
107 clock-names = "apb_pclk";
108 };
109 };
110
111 bus_intmem@10080000 {
112 compatible = "mmio-sram";
113 reg = <0x10080000 0x2000>;
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0 0x10080000 0x2000>;
117 };
118
119 uart2: serial@10210000 {
96800f03 120 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 121 reg = <0x10210000 0x100>;
122 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
123 reg-shift = <2>;
124 reg-io-width = <4>;
125 clock-frequency = <24000000>;
126 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
127 clock-names = "baudclk", "apb_pclk";
128 pinctrl-names = "default";
129 pinctrl-0 = <&uart2m0_xfer>;
130 status = "disabled";
131 };
132
133 uart1: serial@10220000 {
96800f03 134 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 135 reg = <0x10220000 0x100>;
136 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
139 clock-frequency = <24000000>;
140 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
141 clock-names = "baudclk", "apb_pclk";
142 pinctrl-names = "default";
143 pinctrl-0 = <&uart1_xfer>;
144 status = "disabled";
145 };
146
147 uart0: serial@10230000 {
96800f03 148 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 149 reg = <0x10230000 0x100>;
150 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
151 reg-shift = <2>;
152 reg-io-width = <4>;
153 clock-frequency = <24000000>;
154 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
155 clock-names = "baudclk", "apb_pclk";
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
158 status = "disabled";
159 };
160
32cb77a2
AY		 161 i2c1: i2c@10240000 {
162 compatible = "rockchip,rv1108-i2c";
163 reg = <0x10240000 0x1000>;
164 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
168 clock-names = "i2c", "pclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c1_xfer>;
171 rockchip,grf = <&grf>;
172 status = "disabled";
173 };
174
175 i2c2: i2c@10250000 {
176 compatible = "rockchip,rv1108-i2c";
177 reg = <0x10250000 0x1000>;
178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
182 clock-names = "i2c", "pclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&i2c2m1_xfer>;
185 rockchip,grf = <&grf>;
186 status = "disabled";
187 };
188
189 i2c3: i2c@10260000 {
190 compatible = "rockchip,rv1108-i2c";
191 reg = <0x10260000 0x1000>;
192 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
196 clock-names = "i2c", "pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&i2c3_xfer>;
199 rockchip,grf = <&grf>;
200 status = "disabled";
201 };
202
4d1dc2d1
AY		 203 spi: spi@10270000 {
204 compatible = "rockchip,rv1108-spi";
205 reg = <0x10270000 0x1000>;
206 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
208 clock-names = "spiclk", "apb_pclk";
209 dmas = <&pdma 8>, <&pdma 9>;
210 #dma-cells = <2>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 status = "disabled";
214 };
215
0c2d34aa
AY		 216 pwm4: pwm@10280000 {
217 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
218 reg = <0x10280000 0x10>;
219 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
221 clock-names = "pwm", "pclk";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pwm4_pin>;
224 #pwm-cells = <3>;
225 status = "disabled";
226 };
227
228 pwm5: pwm@10280010 {
229 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
230 reg = <0x10280010 0x10>;
231 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
233 clock-names = "pwm", "pclk";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pwm5_pin>;
236 #pwm-cells = <3>;
237 status = "disabled";
238 };
239
240 pwm6: pwm@10280020 {
241 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
242 reg = <0x10280020 0x10>;
243 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
245 clock-names = "pwm", "pclk";
246 pinctrl-names = "default";
247 pinctrl-0 = <&pwm6_pin>;
248 #pwm-cells = <3>;
249 status = "disabled";
250 };
251
252 pwm7: pwm@10280030 {
253 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
254 reg = <0x10280030 0x10>;
255 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
257 clock-names = "pwm", "pclk";
258 pinctrl-names = "default";
259 pinctrl-0 = <&pwm7_pin>;
260 #pwm-cells = <3>;
261 status = "disabled";
262 };
263
60101816 264 grf: syscon@10300000 {
96800f03 265 compatible = "rockchip,rv1108-grf", "syscon";
60101816
AY		 266 reg = <0x10300000 0x1000>;
267 };
268
5584b967
AY		 269 watchdog: wdt@10360000 {
270 compatible = "snps,dw-wdt";
271 reg = <0x10360000 0x100>;
272 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cru PCLK_WDT>;
274 clock-names = "pclk_wdt";
275 status = "disabled";
276 };
277
0e6ff96f
AY		 278 adc: adc@1038c000 {
279 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
280 reg = <0x1038c000 0x100>;
281 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
282 #io-channel-cells = <1>;
283 clock-frequency = <1000000>;
284 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
285 clock-names = "saradc", "apb_pclk";
286 status = "disabled";
287 };
288
32cb77a2
AY		 289 i2c0: i2c@20000000 {
290 compatible = "rockchip,rv1108-i2c";
291 reg = <0x20000000 0x1000>;
292 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
296 clock-names = "i2c", "pclk";
297 pinctrl-names = "default";
298 pinctrl-0 = <&i2c0_xfer>;
299 rockchip,grf = <&grf>;
300 status = "disabled";
301 };
302
0c2d34aa
AY		 303 pwm0: pwm@20040000 {
304 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
305 reg = <0x20040000 0x10>;
306 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
308 clock-names = "pwm", "pclk";
309 pinctrl-names = "default";
310 pinctrl-0 = <&pwm0_pin>;
311 #pwm-cells = <3>;
312 status = "disabled";
313 };
314
315 pwm1: pwm@20040010 {
316 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
317 reg = <0x20040010 0x10>;
318 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
320 clock-names = "pwm", "pclk";
321 pinctrl-names = "default";
322 pinctrl-0 = <&pwm1_pin>;
323 #pwm-cells = <3>;
324 status = "disabled";
325 };
326
327 pwm2: pwm@20040020 {
328 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
329 reg = <0x20040020 0x10>;
330 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
332 clock-names = "pwm", "pclk";
333 pinctrl-names = "default";
334 pinctrl-0 = <&pwm2_pin>;
335 #pwm-cells = <3>;
336 status = "disabled";
337 };
338
339 pwm3: pwm@20040030 {
340 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
341 reg = <0x20040030 0x10>;
342 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
344 clock-names = "pwm", "pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&pwm3_pin>;
347 #pwm-cells = <3>;
348 status = "disabled";
349 };
350
60101816 351 pmugrf: syscon@20060000 {
96800f03 352 compatible = "rockchip,rv1108-pmugrf", "syscon";
60101816
AY		 353 reg = <0x20060000 0x1000>;
354 };
355
356 cru: clock-controller@20200000 {
96800f03 357 compatible = "rockchip,rv1108-cru";
60101816
AY		 358 reg = <0x20200000 0x1000>;
359 rockchip,grf = <&grf>;
360 #clock-cells = <1>;
361 #reset-cells = <1>;
362 };
363
364 emmc: dwmmc@30110000 {
96800f03 365 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 366 reg = <0x30110000 0x4000>;
367 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 368 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
369 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
370 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
371 fifo-depth = <0x100>;
0f4dc7e1 372 max-frequency = <150000000>;
60101816
AY		 373 status = "disabled";
374 };
375
376 sdio: dwmmc@30120000 {
96800f03 377 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 378 reg = <0x30120000 0x4000>;
379 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 380 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
381 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
382 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
383 fifo-depth = <0x100>;
0f4dc7e1 384 max-frequency = <150000000>;
60101816
AY		 385 status = "disabled";
386 };
387
388 sdmmc: dwmmc@30130000 {
96800f03 389 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 390 reg = <0x30130000 0x4000>;
391 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 392 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
393 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
394 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
395 fifo-depth = <0x100>;
0f4dc7e1 396 max-frequency = <100000000>;
d416364f
AY		 397 pinctrl-names = "default";
398 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
60101816
AY		 399 status = "disabled";
400 };
401
402 gic: interrupt-controller@32010000 {
403 compatible = "arm,gic-400";
404 interrupt-controller;
405 #interrupt-cells = <3>;
406 #address-cells = <0>;
407
408 reg = <0x32011000 0x1000>,
387720c9 409 <0x32012000 0x2000>,
60101816
AY		 410 <0x32014000 0x2000>,
411 <0x32016000 0x2000>;
412 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
413 };
414
415 pinctrl: pinctrl {
b9c6dcab 416 compatible = "rockchip,rv1108-pinctrl";
60101816
AY		 417 rockchip,grf = <&grf>;
418 rockchip,pmu = <&pmugrf>;
419 #address-cells = <1>;
420 #size-cells = <1>;
421 ranges;
422
423 gpio0: gpio0@20030000 {
424 compatible = "rockchip,gpio-bank";
425 reg = <0x20030000 0x100>;
426 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&xin24m>;
428
429 gpio-controller;
430 #gpio-cells = <2>;
431
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
435
436 gpio1: gpio1@10310000 {
437 compatible = "rockchip,gpio-bank";
438 reg = <0x10310000 0x100>;
439 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&xin24m>;
441
442 gpio-controller;
443 #gpio-cells = <2>;
444
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 };
448
449 gpio2: gpio2@10320000 {
450 compatible = "rockchip,gpio-bank";
451 reg = <0x10320000 0x100>;
452 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&xin24m>;
454
455 gpio-controller;
456 #gpio-cells = <2>;
457
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 };
461
462 gpio3: gpio3@10330000 {
463 compatible = "rockchip,gpio-bank";
464 reg = <0x10330000 0x100>;
465 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&xin24m>;
467
468 gpio-controller;
469 #gpio-cells = <2>;
470
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 };
474
475 pcfg_pull_up: pcfg-pull-up {
476 bias-pull-up;
477 };
478
479 pcfg_pull_down: pcfg-pull-down {
480 bias-pull-down;
481 };
482
483 pcfg_pull_none: pcfg-pull-none {
484 bias-disable;
485 };
486
487 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
488 drive-strength = <8>;
489 };
490
491 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
492 drive-strength = <12>;
493 };
494
32cb77a2
AY		 495 pcfg_pull_none_smt: pcfg-pull-none-smt {
496 bias-disable;
497 input-schmitt-enable;
498 };
499
60101816
AY		 500 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
501 bias-pull-up;
502 drive-strength = <8>;
503 };
504
505 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
506 drive-strength = <4>;
507 };
508
509 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
510 bias-pull-up;
511 drive-strength = <4>;
512 };
513
514 pcfg_output_high: pcfg-output-high {
515 output-high;
516 };
517
518 pcfg_output_low: pcfg-output-low {
519 output-low;
520 };
521
522 pcfg_input_high: pcfg-input-high {
523 bias-pull-up;
524 input-enable;
525 };
526
32cb77a2
AY		 527 i2c0 {
528 i2c0_xfer: i2c0-xfer {
529 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
530 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
531 };
532 };
533
60101816
AY		 534 i2c1 {
535 i2c1_xfer: i2c1-xfer {
536 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
537 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
538 };
539 };
540
541 i2c2m1 {
542 i2c2m1_xfer: i2c2m1-xfer {
543 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
544 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
545 };
546
547 i2c2m1_gpio: i2c2m1-gpio {
548 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
549 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
550 };
551 };
552
553 i2c2m05v {
554 i2c2m05v_xfer: i2c2m05v-xfer {
555 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
556 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
557 };
558
559 i2c2m05v_gpio: i2c2m05v-gpio {
560 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
561 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
562 };
563 };
564
565 i2c3 {
566 i2c3_xfer: i2c3-xfer {
567 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
568 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
569 };
570 };
571
0c2d34aa
AY		 572 pwm0 {
573 pwm0_pin: pwm0-pin {
574 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
575 };
576 };
577
578 pwm1 {
579 pwm1_pin: pwm1-pin {
580 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
581 };
582 };
583
584 pwm2 {
585 pwm2_pin: pwm2-pin {
586 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
587 };
588 };
589
590 pwm3 {
591 pwm3_pin: pwm3-pin {
592 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
593 };
594 };
595
596 pwm4 {
597 pwm4_pin: pwm4-pin {
598 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
599 };
600 };
601
602 pwm5 {
603 pwm5_pin: pwm5-pin {
604 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
605 };
606 };
607
608 pwm6 {
609 pwm6_pin: pwm6-pin {
610 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
611 };
612 };
613
614 pwm7 {
615 pwm7_pin: pwm7-pin {
616 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
617 };
618 };
619
c458e1b5
JC		 620 sdmmc {
621 sdmmc_clk: sdmmc-clk {
622 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
623 };
624
625 sdmmc_cmd: sdmmc-cmd {
626 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
627 };
628
629 sdmmc_cd: sdmmc-cd {
630 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
631 };
632
633 sdmmc_bus1: sdmmc-bus1 {
634 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
635 };
636
637 sdmmc_bus4: sdmmc-bus4 {
638 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
639 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
640 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
641 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
642 };
643 };
644
60101816
AY		 645 uart0 {
646 uart0_xfer: uart0-xfer {
647 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
648 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
649 };
650
651 uart0_cts: uart0-cts {
652 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
653 };
654
655 uart0_rts: uart0-rts {
656 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
657 };
658
659 uart0_rts_gpio: uart0-rts-gpio {
660 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
661 };
662 };
663
664 uart1 {
665 uart1_xfer: uart1-xfer {
666 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
667 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
668 };
669
670 uart1_cts: uart1-cts {
671 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
672 };
673
674 uart1_rts: uart1-rts {
675 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
676 };
677 };
678
679 uart2m0 {
680 uart2m0_xfer: uart2m0-xfer {
681 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
682 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
683 };
684 };
685
686 uart2m1 {
687 uart2m1_xfer: uart2m1-xfer {
688 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
689 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
690 };
691 };
692
693 uart2_5v {
694 uart2_5v_cts: uart2_5v-cts {
695 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
696 };
697
698 uart2_5v_rts: uart2_5v-rts {
699 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
700 };
701 };
702 };
703};
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