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ARM: dts: rockchip: remove clock-names property from 'generic-ehci' nodes
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / rv1108.dtsi
CommitLineData
fce152a6 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
60101816
AY		 2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
7e2a9035 6#include <dt-bindings/clock/rv1108-cru.h>
60101816 7#include <dt-bindings/pinctrl/rockchip.h>
f6d3f1e8 8#include <dt-bindings/thermal/thermal.h>
60101816
AY		 9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
96800f03 13 compatible = "rockchip,rv1108";
60101816
AY		 14
15 interrupt-parent = <&gic>;
16
17 aliases {
32cb77a2
AY		 18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
60101816
AY		 22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
84ea3a13 35 clock-latency = <40000>;
38baa5a9 36 clocks = <&cru ARMCLK>;
f6d3f1e8
RH		 37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
38baa5a9
AY		 39 operating-points-v2 = <&cpu_opp_table>;
40 };
41 };
42
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
45
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
50 };
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
55 };
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
60 };
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
60101816
AY		 65 };
66 };
67
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
c955b7ae 70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 71 };
72
73 timer {
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
507bc2f5 77 arm,cpu-registers-not-fw-configured;
60101816
AY		 78 clock-frequency = <24000000>;
79 };
80
81 xin24m: oscillator {
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
86 };
87
0c1cb8b0 88 amba: bus {
60101816
AY		 89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 pdma: pdma@102a0000 {
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
98 #dma-cells = <1>;
99 arm,pl330-broken-no-flushp;
100 clocks = <&cru ACLK_DMAC>;
101 clock-names = "apb_pclk";
102 };
103 };
104
048e9a44 105 bus_intmem: sram@10080000 {
60101816
AY		 106 compatible = "mmio-sram";
107 reg = <0x10080000 0x2000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x10080000 0x2000>;
111 };
112
113 uart2: serial@10210000 {
96800f03 114 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 115 reg = <0x10210000 0x100>;
116 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
117 reg-shift = <2>;
118 reg-io-width = <4>;
119 clock-frequency = <24000000>;
120 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
121 clock-names = "baudclk", "apb_pclk";
7d2cecb0 122 dmas = <&pdma 6>, <&pdma 7>;
60101816
AY		 123 pinctrl-names = "default";
124 pinctrl-0 = <&uart2m0_xfer>;
125 status = "disabled";
126 };
127
128 uart1: serial@10220000 {
96800f03 129 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 130 reg = <0x10220000 0x100>;
131 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
132 reg-shift = <2>;
133 reg-io-width = <4>;
134 clock-frequency = <24000000>;
135 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
136 clock-names = "baudclk", "apb_pclk";
7d2cecb0 137 dmas = <&pdma 4>, <&pdma 5>;
60101816
AY		 138 pinctrl-names = "default";
139 pinctrl-0 = <&uart1_xfer>;
140 status = "disabled";
141 };
142
143 uart0: serial@10230000 {
96800f03 144 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
60101816
AY		 145 reg = <0x10230000 0x100>;
146 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
147 reg-shift = <2>;
148 reg-io-width = <4>;
149 clock-frequency = <24000000>;
150 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
151 clock-names = "baudclk", "apb_pclk";
7d2cecb0 152 dmas = <&pdma 2>, <&pdma 3>;
60101816
AY		 153 pinctrl-names = "default";
154 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
155 status = "disabled";
156 };
157
32cb77a2
AY		 158 i2c1: i2c@10240000 {
159 compatible = "rockchip,rv1108-i2c";
160 reg = <0x10240000 0x1000>;
161 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
165 clock-names = "i2c", "pclk";
166 pinctrl-names = "default";
167 pinctrl-0 = <&i2c1_xfer>;
168 rockchip,grf = <&grf>;
169 status = "disabled";
170 };
171
172 i2c2: i2c@10250000 {
173 compatible = "rockchip,rv1108-i2c";
174 reg = <0x10250000 0x1000>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
179 clock-names = "i2c", "pclk";
180 pinctrl-names = "default";
181 pinctrl-0 = <&i2c2m1_xfer>;
182 rockchip,grf = <&grf>;
183 status = "disabled";
184 };
185
186 i2c3: i2c@10260000 {
187 compatible = "rockchip,rv1108-i2c";
188 reg = <0x10260000 0x1000>;
189 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
190 #address-cells = <1>;
191 #size-cells = <0>;
192 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
193 clock-names = "i2c", "pclk";
194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c3_xfer>;
196 rockchip,grf = <&grf>;
197 status = "disabled";
198 };
199
4d1dc2d1
AY		 200 spi: spi@10270000 {
201 compatible = "rockchip,rv1108-spi";
202 reg = <0x10270000 0x1000>;
203 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
205 clock-names = "spiclk", "apb_pclk";
206 dmas = <&pdma 8>, <&pdma 9>;
a4b0e36d 207 dma-names = "tx", "rx";
4d1dc2d1
AY		 208 #address-cells = <1>;
209 #size-cells = <0>;
210 status = "disabled";
211 };
212
0c2d34aa
AY		 213 pwm4: pwm@10280000 {
214 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
215 reg = <0x10280000 0x10>;
216 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
218 clock-names = "pwm", "pclk";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pwm4_pin>;
221 #pwm-cells = <3>;
222 status = "disabled";
223 };
224
225 pwm5: pwm@10280010 {
226 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
227 reg = <0x10280010 0x10>;
228 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
230 clock-names = "pwm", "pclk";
231 pinctrl-names = "default";
232 pinctrl-0 = <&pwm5_pin>;
233 #pwm-cells = <3>;
234 status = "disabled";
235 };
236
237 pwm6: pwm@10280020 {
238 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
239 reg = <0x10280020 0x10>;
240 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
242 clock-names = "pwm", "pclk";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pwm6_pin>;
245 #pwm-cells = <3>;
246 status = "disabled";
247 };
248
249 pwm7: pwm@10280030 {
250 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
251 reg = <0x10280030 0x10>;
252 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
254 clock-names = "pwm", "pclk";
255 pinctrl-names = "default";
256 pinctrl-0 = <&pwm7_pin>;
257 #pwm-cells = <3>;
258 status = "disabled";
259 };
260
60101816 261 grf: syscon@10300000 {
24f9f5bb 262 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
60101816 263 reg = <0x10300000 0x1000>;
24f9f5bb
FW		 264 #address-cells = <1>;
265 #size-cells = <1>;
266
267 u2phy: usb2-phy@100 {
268 compatible = "rockchip,rv1108-usb2phy";
269 reg = <0x100 0x0c>;
270 clocks = <&cru SCLK_USBPHY>;
271 clock-names = "phyclk";
272 #clock-cells = <0>;
273 clock-output-names = "usbphy";
274 rockchip,usbgrf = <&usbgrf>;
275 status = "disabled";
276
277 u2phy_otg: otg-port {
278 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "otg-mux";
280 #phy-cells = <0>;
281 status = "disabled";
282 };
283
284 u2phy_host: host-port {
285 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-names = "linestate";
287 #phy-cells = <0>;
288 status = "disabled";
289 };
290 };
60101816
AY		 291 };
292
7841b88a
OS		 293 timer: timer@10350000 {
294 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
295 reg = <0x10350000 0x20>;
296 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&xin24m>, <&cru PCLK_TIMER>;
298 clock-names = "timer", "pclk";
299 };
300
5584b967
AY		 301 watchdog: wdt@10360000 {
302 compatible = "snps,dw-wdt";
303 reg = <0x10360000 0x100>;
304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru PCLK_WDT>;
306 clock-names = "pclk_wdt";
307 status = "disabled";
308 };
309
f6d3f1e8
RH		 310 thermal-zones {
311 soc_thermal: soc-thermal {
312 polling-delay-passive = <20>;
313 polling-delay = <1000>;
314 sustainable-power = <50>;
315 thermal-sensors = <&tsadc 0>;
316
317 trips {
318 threshold: trip-point0 {
319 temperature = <70000>;
320 hysteresis = <2000>;
321 type = "passive";
322 };
323 target: trip-point1 {
324 temperature = <85000>;
325 hysteresis = <2000>;
326 type = "passive";
327 };
328 soc_crit: soc-crit {
329 temperature = <95000>;
330 hysteresis = <2000>;
331 type = "critical";
332 };
333 };
334
335 cooling-maps {
336 map0 {
337 trip = <&target>;
338 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 contribution = <4096>;
340 };
341 };
342 };
343 };
344
fb03abbc
RH		 345 tsadc: tsadc@10370000 {
346 compatible = "rockchip,rv1108-tsadc";
347 reg = <0x10370000 0x100>;
348 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
349 assigned-clocks = <&cru SCLK_TSADC>;
350 assigned-clock-rates = <750000>;
351 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
352 clock-names = "tsadc", "apb_pclk";
353 pinctrl-names = "init", "default", "sleep";
354 pinctrl-0 = <&otp_gpio>;
355 pinctrl-1 = <&otp_out>;
356 pinctrl-2 = <&otp_gpio>;
357 resets = <&cru SRST_TSADC>;
358 reset-names = "tsadc-apb";
359 rockchip,hw-tshut-temp = <120000>;
360 #thermal-sensor-cells = <1>;
361 status = "disabled";
362 };
363
0e6ff96f
AY		 364 adc: adc@1038c000 {
365 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
366 reg = <0x1038c000 0x100>;
367 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
368 #io-channel-cells = <1>;
0e6ff96f
AY		 369 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
370 clock-names = "saradc", "apb_pclk";
371 status = "disabled";
372 };
373
32cb77a2
AY		 374 i2c0: i2c@20000000 {
375 compatible = "rockchip,rv1108-i2c";
376 reg = <0x20000000 0x1000>;
377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
381 clock-names = "i2c", "pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c0_xfer>;
384 rockchip,grf = <&grf>;
385 status = "disabled";
386 };
387
0c2d34aa
AY		 388 pwm0: pwm@20040000 {
389 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
390 reg = <0x20040000 0x10>;
391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
393 clock-names = "pwm", "pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&pwm0_pin>;
396 #pwm-cells = <3>;
397 status = "disabled";
398 };
399
400 pwm1: pwm@20040010 {
401 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
402 reg = <0x20040010 0x10>;
403 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
405 clock-names = "pwm", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm1_pin>;
408 #pwm-cells = <3>;
409 status = "disabled";
410 };
411
412 pwm2: pwm@20040020 {
413 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
414 reg = <0x20040020 0x10>;
415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
417 clock-names = "pwm", "pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&pwm2_pin>;
420 #pwm-cells = <3>;
421 status = "disabled";
422 };
423
424 pwm3: pwm@20040030 {
425 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
426 reg = <0x20040030 0x10>;
427 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
429 clock-names = "pwm", "pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pwm3_pin>;
432 #pwm-cells = <3>;
433 status = "disabled";
434 };
435
60101816 436 pmugrf: syscon@20060000 {
96800f03 437 compatible = "rockchip,rv1108-pmugrf", "syscon";
60101816
AY		 438 reg = <0x20060000 0x1000>;
439 };
440
24f9f5bb
FW		 441 usbgrf: syscon@202a0000 {
442 compatible = "rockchip,rv1108-usbgrf", "syscon";
443 reg = <0x202a0000 0x1000>;
444 };
445
60101816 446 cru: clock-controller@20200000 {
96800f03 447 compatible = "rockchip,rv1108-cru";
60101816
AY		 448 reg = <0x20200000 0x1000>;
449 rockchip,grf = <&grf>;
450 #clock-cells = <1>;
451 #reset-cells = <1>;
452 };
453
fed1fc51 454 emmc: mmc@30110000 {
96800f03 455 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 456 reg = <0x30110000 0x4000>;
457 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 458 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
459 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
460 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
461 fifo-depth = <0x100>;
0f4dc7e1 462 max-frequency = <150000000>;
60101816
AY		 463 status = "disabled";
464 };
465
fed1fc51 466 sdio: mmc@30120000 {
96800f03 467 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 468 reg = <0x30120000 0x4000>;
469 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 470 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
471 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
472 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
473 fifo-depth = <0x100>;
0f4dc7e1 474 max-frequency = <150000000>;
60101816
AY		 475 status = "disabled";
476 };
477
fed1fc51 478 sdmmc: mmc@30130000 {
96800f03 479 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0f4dc7e1
HS		 480 reg = <0x30130000 0x4000>;
481 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
60101816
AY		 482 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
483 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
484 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
485 fifo-depth = <0x100>;
0f4dc7e1 486 max-frequency = <100000000>;
d416364f
AY		 487 pinctrl-names = "default";
488 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
60101816
AY		 489 status = "disabled";
490 };
491
24f9f5bb
FW		 492 usb_host_ehci: usb@30140000 {
493 compatible = "generic-ehci";
494 reg = <0x30140000 0x20000>;
495 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cru HCLK_HOST0>, <&u2phy>;
24f9f5bb
FW		 497 phys = <&u2phy_host>;
498 phy-names = "usb";
499 status = "disabled";
500 };
501
502 usb_host_ohci: usb@30160000 {
503 compatible = "generic-ohci";
504 reg = <0x30160000 0x20000>;
505 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&cru HCLK_HOST0>, <&u2phy>;
507 clock-names = "usbhost", "utmi";
508 phys = <&u2phy_host>;
509 phy-names = "usb";
510 status = "disabled";
511 };
512
513 usb_otg: usb@30180000 {
514 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
515 "snps,dwc2";
516 reg = <0x30180000 0x40000>;
517 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru HCLK_OTG>;
519 clock-names = "otg";
520 dr_mode = "otg";
521 g-np-tx-fifo-size = <16>;
522 g-rx-fifo-size = <280>;
523 g-tx-fifo-size = <256 128 128 64 32 16>;
24f9f5bb
FW		 524 phys = <&u2phy_otg>;
525 phy-names = "usb2-phy";
526 status = "disabled";
527 };
528
7d015bd7
OS		 529 gmac: eth@30200000 {
530 compatible = "rockchip,rv1108-gmac";
531 reg = <0x30200000 0x10000>;
532 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-names = "macirq", "eth_wake_irq";
535 clocks = <&cru SCLK_MAC>,
536 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
537 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
538 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
539 clock-names = "stmmaceth",
540 "mac_clk_rx", "mac_clk_tx",
541 "clk_mac_ref", "clk_mac_refout",
542 "aclk_mac", "pclk_mac";
543 /* rv1108 only supports an rmii interface */
544 phy-mode = "rmii";
545 pinctrl-names = "default";
546 pinctrl-0 = <&rmii_pins>;
547 rockchip,grf = <&grf>;
548 status = "disabled";
549 };
550
60101816
AY		 551 gic: interrupt-controller@32010000 {
552 compatible = "arm,gic-400";
553 interrupt-controller;
554 #interrupt-cells = <3>;
555 #address-cells = <0>;
556
557 reg = <0x32011000 0x1000>,
387720c9 558 <0x32012000 0x2000>,
60101816
AY		 559 <0x32014000 0x2000>,
560 <0x32016000 0x2000>;
561 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
562 };
563
564 pinctrl: pinctrl {
b9c6dcab 565 compatible = "rockchip,rv1108-pinctrl";
60101816
AY		 566 rockchip,grf = <&grf>;
567 rockchip,pmu = <&pmugrf>;
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges;
571
572 gpio0: gpio0@20030000 {
573 compatible = "rockchip,gpio-bank";
574 reg = <0x20030000 0x100>;
575 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 576 clocks = <&cru PCLK_GPIO0_PMU>;
60101816
AY		 577
578 gpio-controller;
579 #gpio-cells = <2>;
580
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 };
584
585 gpio1: gpio1@10310000 {
586 compatible = "rockchip,gpio-bank";
587 reg = <0x10310000 0x100>;
588 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 589 clocks = <&cru PCLK_GPIO1>;
60101816
AY		 590
591 gpio-controller;
592 #gpio-cells = <2>;
593
594 interrupt-controller;
595 #interrupt-cells = <2>;
596 };
597
598 gpio2: gpio2@10320000 {
599 compatible = "rockchip,gpio-bank";
600 reg = <0x10320000 0x100>;
601 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 602 clocks = <&cru PCLK_GPIO2>;
60101816
AY		 603
604 gpio-controller;
605 #gpio-cells = <2>;
606
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 };
610
611 gpio3: gpio3@10330000 {
612 compatible = "rockchip,gpio-bank";
613 reg = <0x10330000 0x100>;
614 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
efc2e0bd 615 clocks = <&cru PCLK_GPIO3>;
60101816
AY		 616
617 gpio-controller;
618 #gpio-cells = <2>;
619
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 };
623
624 pcfg_pull_up: pcfg-pull-up {
625 bias-pull-up;
626 };
627
628 pcfg_pull_down: pcfg-pull-down {
629 bias-pull-down;
630 };
631
632 pcfg_pull_none: pcfg-pull-none {
633 bias-disable;
634 };
635
636 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
637 drive-strength = <8>;
638 };
639
640 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
641 drive-strength = <12>;
642 };
643
32cb77a2
AY		 644 pcfg_pull_none_smt: pcfg-pull-none-smt {
645 bias-disable;
646 input-schmitt-enable;
647 };
648
60101816
AY		 649 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
650 bias-pull-up;
651 drive-strength = <8>;
652 };
653
654 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
655 drive-strength = <4>;
656 };
657
658 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
659 bias-pull-up;
660 drive-strength = <4>;
661 };
662
663 pcfg_output_high: pcfg-output-high {
664 output-high;
665 };
666
667 pcfg_output_low: pcfg-output-low {
668 output-low;
669 };
670
671 pcfg_input_high: pcfg-input-high {
672 bias-pull-up;
673 input-enable;
674 };
675
bdd98681
OS		 676 emmc {
677 emmc_bus8: emmc-bus8 {
07f08d9c
HS		 678 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
679 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
680 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
681 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
682 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
683 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
684 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
685 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
bdd98681
OS		 686 };
687
688 emmc_clk: emmc-clk {
07f08d9c 689 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
bdd98681
OS		 690 };
691
692 emmc_cmd: emmc-cmd {
07f08d9c 693 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
bdd98681
OS		 694 };
695 };
696
7d015bd7
OS		 697 gmac {
698 rmii_pins: rmii-pins {
07f08d9c
HS		 699 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
700 <1 RK_PC3 2 &pcfg_pull_none>,
701 <1 RK_PC4 2 &pcfg_pull_none>,
702 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
703 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
704 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
705 <1 RK_PB5 3 &pcfg_pull_none>,
706 <1 RK_PB6 3 &pcfg_pull_none>,
707 <1 RK_PB7 3 &pcfg_pull_none>,
708 <1 RK_PC2 3 &pcfg_pull_none>;
7d015bd7
OS		 709 };
710 };
711
32cb77a2
AY		 712 i2c0 {
713 i2c0_xfer: i2c0-xfer {
07f08d9c
HS		 714 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
715 <0 RK_PB2 1 &pcfg_pull_none_smt>;
32cb77a2
AY		 716 };
717 };
718
60101816
AY		 719 i2c1 {
720 i2c1_xfer: i2c1-xfer {
07f08d9c
HS		 721 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
722 <2 RK_PD4 1 &pcfg_pull_up>;
60101816
AY		 723 };
724 };
725
726 i2c2m1 {
727 i2c2m1_xfer: i2c2m1-xfer {
07f08d9c
HS		 728 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
729 <0 RK_PC6 3 &pcfg_pull_none>;
60101816
AY		 730 };
731
732 i2c2m1_gpio: i2c2m1-gpio {
733 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
734 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
735 };
736 };
737
738 i2c2m05v {
739 i2c2m05v_xfer: i2c2m05v-xfer {
07f08d9c
HS		 740 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
741 <1 RK_PD4 2 &pcfg_pull_none>;
60101816
AY		 742 };
743
744 i2c2m05v_gpio: i2c2m05v-gpio {
745 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
746 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
747 };
748 };
749
750 i2c3 {
751 i2c3_xfer: i2c3-xfer {
07f08d9c
HS		 752 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
753 <0 RK_PC4 2 &pcfg_pull_none>;
60101816
AY		 754 };
755 };
756
0c2d34aa
AY		 757 pwm0 {
758 pwm0_pin: pwm0-pin {
07f08d9c 759 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
0c2d34aa
AY		 760 };
761 };
762
763 pwm1 {
764 pwm1_pin: pwm1-pin {
07f08d9c 765 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
0c2d34aa
AY		 766 };
767 };
768
769 pwm2 {
770 pwm2_pin: pwm2-pin {
07f08d9c 771 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
0c2d34aa
AY		 772 };
773 };
774
775 pwm3 {
776 pwm3_pin: pwm3-pin {
07f08d9c 777 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
0c2d34aa
AY		 778 };
779 };
780
781 pwm4 {
782 pwm4_pin: pwm4-pin {
07f08d9c 783 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
0c2d34aa
AY		 784 };
785 };
786
787 pwm5 {
788 pwm5_pin: pwm5-pin {
07f08d9c 789 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
0c2d34aa
AY		 790 };
791 };
792
793 pwm6 {
794 pwm6_pin: pwm6-pin {
07f08d9c 795 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
0c2d34aa
AY		 796 };
797 };
798
799 pwm7 {
800 pwm7_pin: pwm7-pin {
07f08d9c 801 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
0c2d34aa
AY		 802 };
803 };
804
c458e1b5
JC		 805 sdmmc {
806 sdmmc_clk: sdmmc-clk {
07f08d9c 807 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
c458e1b5
JC		 808 };
809
810 sdmmc_cmd: sdmmc-cmd {
07f08d9c 811 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
c458e1b5
JC		 812 };
813
814 sdmmc_cd: sdmmc-cd {
07f08d9c 815 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
c458e1b5
JC		 816 };
817
818 sdmmc_bus1: sdmmc-bus1 {
07f08d9c 819 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
c458e1b5
JC		 820 };
821
822 sdmmc_bus4: sdmmc-bus4 {
07f08d9c
HS		 823 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
824 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
825 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
826 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
c458e1b5
JC		 827 };
828 };
829
fa2b56e7
OS		 830 spim0 {
831 spim0_clk: spim0-clk {
07f08d9c 832 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
fa2b56e7
OS		 833 };
834
835 spim0_cs0: spim0-cs0 {
07f08d9c 836 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
fa2b56e7
OS		 837 };
838
839 spim0_tx: spim0-tx {
07f08d9c 840 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
fa2b56e7
OS		 841 };
842
843 spim0_rx: spim0-rx {
07f08d9c 844 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
fa2b56e7
OS		 845 };
846 };
847
848 spim1 {
849 spim1_clk: spim1-clk {
07f08d9c 850 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
fa2b56e7
OS		 851 };
852
853 spim1_cs0: spim1-cs0 {
07f08d9c 854 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
fa2b56e7
OS		 855 };
856
857 spim1_rx: spim1-rx {
07f08d9c 858 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
fa2b56e7
OS		 859 };
860
861 spim1_tx: spim1-tx {
07f08d9c 862 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
fa2b56e7
OS		 863 };
864 };
865
fb03abbc
RH		 866 tsadc {
867 otp_out: otp-out {
07f08d9c 868 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
fb03abbc
RH		 869 };
870
871 otp_gpio: otp-gpio {
872 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
873 };
874 };
875
60101816
AY		 876 uart0 {
877 uart0_xfer: uart0-xfer {
07f08d9c
HS		 878 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
879 <3 RK_PA5 1 &pcfg_pull_none>;
60101816
AY		 880 };
881
882 uart0_cts: uart0-cts {
07f08d9c 883 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
60101816
AY		 884 };
885
886 uart0_rts: uart0-rts {
07f08d9c 887 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
60101816
AY		 888 };
889
890 uart0_rts_gpio: uart0-rts-gpio {
891 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
892 };
893 };
894
895 uart1 {
896 uart1_xfer: uart1-xfer {
07f08d9c
HS		 897 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
898 <1 RK_PD2 1 &pcfg_pull_none>;
60101816
AY		 899 };
900
901 uart1_cts: uart1-cts {
07f08d9c 902 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
60101816
AY		 903 };
904
905 uart1_rts: uart1-rts {
07f08d9c 906 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
60101816
AY		 907 };
908 };
909
910 uart2m0 {
911 uart2m0_xfer: uart2m0-xfer {
07f08d9c
HS		 912 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
913 <2 RK_PD1 1 &pcfg_pull_none>;
60101816
AY		 914 };
915 };
916
917 uart2m1 {
918 uart2m1_xfer: uart2m1-xfer {
07f08d9c
HS		 919 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
920 <3 RK_PC2 2 &pcfg_pull_none>;
60101816
AY		 921 };
922 };
923
924 uart2_5v {
925 uart2_5v_cts: uart2_5v-cts {
07f08d9c 926 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
60101816
AY		 927 };
928
929 uart2_5v_rts: uart2_5v-rts {
07f08d9c 930 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
60101816
AY		 931 };
932 };
933 };
934};
Ubuntu Hirsute Linux kernel mirror