[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / s3c2416.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C2416 SoC device tree source
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 */

#include <dt-bindings/clock/s3c2443.h>
#include "s3c24xx.dtsi"
#include "s3c2416-pinctrl.dtsi"

/ {
	model = "Samsung S3C2416 SoC";
	compatible = "samsung,s3c2416";

	aliases {
		serial3 = &uart_3;
	};

	cpus {
		cpu {
			compatible = "arm,arm926ej-s";
		};
	};

	interrupt-controller@4a000000 {
		compatible = "samsung,s3c2416-irq";
	};

	clocks: clock-controller@4c000000 {
		compatible = "samsung,s3c2416-clock";
		reg = <0x4c000000 0x40>;
		#clock-cells = <1>;
	};

	pinctrl@56000000 {
		compatible = "samsung,s3c2416-pinctrl";
	};

	timer@51000000 {
		clocks = <&clocks PCLK_PWM>;
		clock-names = "timers";
	};

	uart_0: serial@50000000 {
		compatible = "samsung,s3c2440-uart";
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
				<&clocks SCLK_UART>;
	};

	uart_1: serial@50004000 {
		compatible = "samsung,s3c2440-uart";
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
				<&clocks SCLK_UART>;
	};

	uart_2: serial@50008000 {
		compatible = "samsung,s3c2440-uart";
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
				<&clocks SCLK_UART>;
	};

	uart_3: serial@5000c000 {
		compatible = "samsung,s3c2440-uart";
		reg = <0x5000C000 0x4000>;
		interrupts = <1 18 24 4>, <1 18 25 4>;
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
				<&clocks SCLK_UART>;
		status = "disabled";
	};

	sdhci_1: sdhci@4ac00000 {
		compatible = "samsung,s3c6410-sdhci";
		reg = <0x4AC00000 0x100>;
		interrupts = <0 0 21 3>;
		clock-names = "hsmmc", "mmc_busclk.0",
				"mmc_busclk.2";
		clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
				<&clocks MUX_HSMMC0>;
		status = "disabled";
	};

	sdhci_0: sdhci@4a800000 {
		compatible = "samsung,s3c6410-sdhci";
		reg = <0x4A800000 0x100>;
		interrupts = <0 0 20 3>;
		clock-names = "hsmmc", "mmc_busclk.0",
				"mmc_busclk.2";
		clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
				<&clocks MUX_HSMMC1>;
		status = "disabled";
	};

	watchdog: watchdog@53000000 {
		interrupts = <1 9 27 3>;
		clocks = <&clocks PCLK_WDT>;
		clock-names = "watchdog";
	};

	rtc: rtc@57000000 {
		compatible = "samsung,s3c2416-rtc";
		clocks = <&clocks PCLK_RTC>;
		clock-names = "rtc";
	};

	i2c@54000000 {
		compatible = "samsung,s3c2440-i2c";
		clocks = <&clocks PCLK_I2C0>;
		clock-names = "i2c";
	};
};
Commit	Line	Data
8d4893e3	1	// SPDX-License-Identifier: GPL-2.0
35aca364 HS	2	/*
	3	* Samsung's S3C2416 SoC device tree source
	4	*
	5	* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
35aca364 HS	6	*/
35aca364 HS	7
8cb28748	8	#include <dt-bindings/clock/s3c2443.h>
3799279f PV	9	#include "s3c24xx.dtsi"
3799279f PV	10	#include "s3c2416-pinctrl.dtsi"
35aca364 HS	11
	12	/ {
	13	model = "Samsung S3C2416 SoC";
	14	compatible = "samsung,s3c2416";
	15
1e64f48e	16	aliases {
3ae9d92f	17	serial3 = &uart_3;
1e64f48e TF	18	};
1e64f48e TF	19
35aca364	20	cpus {
35aca364	21	cpu {
6716f6c6	22	compatible = "arm,arm926ej-s";
35aca364 HS	23	};
	24	};
	25
	26	interrupt-controller@4a000000 {
	27	compatible = "samsung,s3c2416-irq";
	28	};
	29
edef4285	30	clocks: clock-controller@4c000000 {
8cb28748 HS	31	compatible = "samsung,s3c2416-clock";
	32	reg = <0x4c000000 0x40>;
	33	#clock-cells = <1>;
	34	};
	35
35aca364 HS	36	pinctrl@56000000 {
	37	compatible = "samsung,s3c2416-pinctrl";
	38	};
	39
8cb28748 HS	40	timer@51000000 {
	41	clocks = <&clocks PCLK_PWM>;
	42	clock-names = "timers";
	43	};
	44
3ae9d92f	45	uart_0: serial@50000000 {
35aca364	46	compatible = "samsung,s3c2440-uart";
8cb28748 HS	47	clock-names = "uart", "clk_uart_baud2",
	48	"clk_uart_baud3";
	49	clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
	50	<&clocks SCLK_UART>;
35aca364 HS	51	};
35aca364 HS	52
3ae9d92f	53	uart_1: serial@50004000 {
35aca364	54	compatible = "samsung,s3c2440-uart";
8cb28748 HS	55	clock-names = "uart", "clk_uart_baud2",
	56	"clk_uart_baud3";
	57	clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
	58	<&clocks SCLK_UART>;
35aca364 HS	59	};
35aca364 HS	60
3ae9d92f	61	uart_2: serial@50008000 {
35aca364	62	compatible = "samsung,s3c2440-uart";
8cb28748 HS	63	clock-names = "uart", "clk_uart_baud2",
	64	"clk_uart_baud3";
	65	clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
	66	<&clocks SCLK_UART>;
35aca364 HS	67	};
35aca364 HS	68
edef4285	69	uart_3: serial@5000c000 {
35aca364 HS	70	compatible = "samsung,s3c2440-uart";
	71	reg = <0x5000C000 0x4000>;
	72	interrupts = <1 18 24 4>, <1 18 25 4>;
8cb28748 HS	73	clock-names = "uart", "clk_uart_baud2",
	74	"clk_uart_baud3";
	75	clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
	76	<&clocks SCLK_UART>;
35aca364 HS	77	status = "disabled";
	78	};
	79
edef4285	80	sdhci_1: sdhci@4ac00000 {
35aca364 HS	81	compatible = "samsung,s3c6410-sdhci";
	82	reg = <0x4AC00000 0x100>;
	83	interrupts = <0 0 21 3>;
8cb28748 HS	84	clock-names = "hsmmc", "mmc_busclk.0",
	85	"mmc_busclk.2";
	86	clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
	87	<&clocks MUX_HSMMC0>;
35aca364 HS	88	status = "disabled";
	89	};
	90
edef4285	91	sdhci_0: sdhci@4a800000 {
35aca364 HS	92	compatible = "samsung,s3c6410-sdhci";
	93	reg = <0x4A800000 0x100>;
	94	interrupts = <0 0 20 3>;
8cb28748 HS	95	clock-names = "hsmmc", "mmc_busclk.0",
	96	"mmc_busclk.2";
	97	clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
	98	<&clocks MUX_HSMMC1>;
35aca364 HS	99	status = "disabled";
	100	};
	101
3ae9d92f	102	watchdog: watchdog@53000000 {
35aca364	103	interrupts = <1 9 27 3>;
8cb28748 HS	104	clocks = <&clocks PCLK_WDT>;
8cb28748 HS	105	clock-names = "watchdog";
35aca364 HS	106	};
35aca364 HS	107
3ae9d92f	108	rtc: rtc@57000000 {
35aca364	109	compatible = "samsung,s3c2416-rtc";
8cb28748 HS	110	clocks = <&clocks PCLK_RTC>;
8cb28748 HS	111	clock-names = "rtc";
35aca364 HS	112	};
	113
	114	i2c@54000000 {
	115	compatible = "samsung,s3c2440-i2c";
8cb28748 HS	116	clocks = <&clocks PCLK_I2C0>;
8cb28748 HS	117	clock-names = "i2c";
35aca364 HS	118	};
35aca364 HS	119	};