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e30cf8d3 LD |
1 | /* |
2 | * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
46 | #include "skeleton.dtsi" | |
47 | #include <dt-bindings/dma/at91.h> | |
48 | #include <dt-bindings/interrupt-controller/irq.h> | |
49 | #include <dt-bindings/clock/at91.h> | |
50 | ||
51 | / { | |
52 | model = "Atmel SAMA5D2 family SoC"; | |
53 | compatible = "atmel,sama5d2"; | |
54 | interrupt-parent = <&aic>; | |
55 | ||
56 | aliases { | |
57 | serial0 = &uart1; | |
58 | serial1 = &uart3; | |
59 | tcb0 = &tcb0; | |
60 | tcb1 = &tcb1; | |
61 | }; | |
62 | ||
63 | cpus { | |
64 | #address-cells = <1>; | |
65 | #size-cells = <0>; | |
66 | ||
67 | cpu@0 { | |
68 | device_type = "cpu"; | |
69 | compatible = "arm,cortex-a5"; | |
70 | reg = <0>; | |
71 | next-level-cache = <&L2>; | |
72 | }; | |
73 | }; | |
74 | ||
fcac40c9 OS |
75 | pmu { |
76 | compatible = "arm,cortex-a5-pmu"; | |
77 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; | |
78 | }; | |
79 | ||
e46f48ad OS |
80 | etb { |
81 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
82 | reg = <0x740000 0x1000>; | |
83 | ||
84 | clocks = <&mck>; | |
85 | clock-names = "apb_pclk"; | |
86 | ||
87 | port { | |
88 | etb_in: endpoint { | |
89 | slave-mode; | |
90 | remote-endpoint = <&etm_out>; | |
91 | }; | |
92 | }; | |
93 | }; | |
94 | ||
95 | etm { | |
96 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
97 | reg = <0x73C000 0x1000>; | |
98 | ||
99 | clocks = <&mck>; | |
100 | clock-names = "apb_pclk"; | |
101 | ||
102 | port { | |
103 | etm_out: endpoint { | |
104 | remote-endpoint = <&etb_in>; | |
105 | }; | |
106 | }; | |
107 | }; | |
108 | ||
e30cf8d3 LD |
109 | memory { |
110 | reg = <0x20000000 0x20000000>; | |
111 | }; | |
112 | ||
113 | clocks { | |
114 | slow_xtal: slow_xtal { | |
115 | compatible = "fixed-clock"; | |
116 | #clock-cells = <0>; | |
117 | clock-frequency = <0>; | |
118 | }; | |
119 | ||
120 | main_xtal: main_xtal { | |
121 | compatible = "fixed-clock"; | |
122 | #clock-cells = <0>; | |
123 | clock-frequency = <0>; | |
124 | }; | |
e30cf8d3 LD |
125 | }; |
126 | ||
127 | ns_sram: sram@00200000 { | |
128 | compatible = "mmio-sram"; | |
129 | reg = <0x00200000 0x20000>; | |
130 | }; | |
131 | ||
132 | ahb { | |
133 | compatible = "simple-bus"; | |
134 | #address-cells = <1>; | |
135 | #size-cells = <1>; | |
136 | ranges; | |
137 | ||
138 | usb0: gadget@00300000 { | |
139 | #address-cells = <1>; | |
140 | #size-cells = <0>; | |
141 | compatible = "atmel,sama5d3-udc"; | |
142 | reg = <0x00300000 0x100000 | |
143 | 0xfc02c000 0x400>; | |
144 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; | |
145 | clocks = <&udphs_clk>, <&utmi>; | |
146 | clock-names = "pclk", "hclk"; | |
147 | status = "disabled"; | |
148 | ||
c32b5bcf | 149 | ep@0 { |
e30cf8d3 LD |
150 | reg = <0>; |
151 | atmel,fifo-size = <64>; | |
152 | atmel,nb-banks = <1>; | |
153 | }; | |
154 | ||
c32b5bcf | 155 | ep@1 { |
e30cf8d3 LD |
156 | reg = <1>; |
157 | atmel,fifo-size = <1024>; | |
158 | atmel,nb-banks = <3>; | |
159 | atmel,can-dma; | |
160 | atmel,can-isoc; | |
161 | }; | |
162 | ||
c32b5bcf | 163 | ep@2 { |
e30cf8d3 LD |
164 | reg = <2>; |
165 | atmel,fifo-size = <1024>; | |
166 | atmel,nb-banks = <3>; | |
167 | atmel,can-dma; | |
168 | atmel,can-isoc; | |
169 | }; | |
170 | ||
c32b5bcf | 171 | ep@3 { |
e30cf8d3 LD |
172 | reg = <3>; |
173 | atmel,fifo-size = <1024>; | |
174 | atmel,nb-banks = <2>; | |
175 | atmel,can-dma; | |
176 | atmel,can-isoc; | |
177 | }; | |
178 | ||
c32b5bcf | 179 | ep@4 { |
e30cf8d3 LD |
180 | reg = <4>; |
181 | atmel,fifo-size = <1024>; | |
182 | atmel,nb-banks = <2>; | |
183 | atmel,can-dma; | |
184 | atmel,can-isoc; | |
185 | }; | |
186 | ||
c32b5bcf | 187 | ep@5 { |
e30cf8d3 LD |
188 | reg = <5>; |
189 | atmel,fifo-size = <1024>; | |
190 | atmel,nb-banks = <2>; | |
191 | atmel,can-dma; | |
192 | atmel,can-isoc; | |
193 | }; | |
194 | ||
c32b5bcf | 195 | ep@6 { |
e30cf8d3 LD |
196 | reg = <6>; |
197 | atmel,fifo-size = <1024>; | |
198 | atmel,nb-banks = <2>; | |
199 | atmel,can-dma; | |
200 | atmel,can-isoc; | |
201 | }; | |
202 | ||
c32b5bcf | 203 | ep@7 { |
e30cf8d3 LD |
204 | reg = <7>; |
205 | atmel,fifo-size = <1024>; | |
206 | atmel,nb-banks = <2>; | |
207 | atmel,can-dma; | |
208 | atmel,can-isoc; | |
209 | }; | |
210 | ||
c32b5bcf | 211 | ep@8 { |
e30cf8d3 LD |
212 | reg = <8>; |
213 | atmel,fifo-size = <1024>; | |
214 | atmel,nb-banks = <2>; | |
215 | atmel,can-isoc; | |
216 | }; | |
217 | ||
c32b5bcf | 218 | ep@9 { |
e30cf8d3 LD |
219 | reg = <9>; |
220 | atmel,fifo-size = <1024>; | |
221 | atmel,nb-banks = <2>; | |
222 | atmel,can-isoc; | |
223 | }; | |
224 | ||
c32b5bcf | 225 | ep@10 { |
e30cf8d3 LD |
226 | reg = <10>; |
227 | atmel,fifo-size = <1024>; | |
228 | atmel,nb-banks = <2>; | |
229 | atmel,can-isoc; | |
230 | }; | |
231 | ||
c32b5bcf | 232 | ep@11 { |
e30cf8d3 LD |
233 | reg = <11>; |
234 | atmel,fifo-size = <1024>; | |
235 | atmel,nb-banks = <2>; | |
236 | atmel,can-isoc; | |
237 | }; | |
238 | ||
c32b5bcf | 239 | ep@12 { |
e30cf8d3 LD |
240 | reg = <12>; |
241 | atmel,fifo-size = <1024>; | |
242 | atmel,nb-banks = <2>; | |
243 | atmel,can-isoc; | |
244 | }; | |
245 | ||
c32b5bcf | 246 | ep@13 { |
e30cf8d3 LD |
247 | reg = <13>; |
248 | atmel,fifo-size = <1024>; | |
249 | atmel,nb-banks = <2>; | |
250 | atmel,can-isoc; | |
251 | }; | |
252 | ||
c32b5bcf | 253 | ep@14 { |
e30cf8d3 LD |
254 | reg = <14>; |
255 | atmel,fifo-size = <1024>; | |
256 | atmel,nb-banks = <2>; | |
257 | atmel,can-isoc; | |
258 | }; | |
259 | ||
c32b5bcf | 260 | ep@15 { |
e30cf8d3 LD |
261 | reg = <15>; |
262 | atmel,fifo-size = <1024>; | |
263 | atmel,nb-banks = <2>; | |
264 | atmel,can-isoc; | |
265 | }; | |
266 | }; | |
267 | ||
268 | usb1: ohci@00400000 { | |
9e10889a | 269 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
e30cf8d3 LD |
270 | reg = <0x00400000 0x100000>; |
271 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; | |
272 | clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; | |
273 | clock-names = "ohci_clk", "hclk", "uhpck"; | |
274 | status = "disabled"; | |
275 | }; | |
276 | ||
277 | usb2: ehci@00500000 { | |
278 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
279 | reg = <0x00500000 0x100000>; | |
280 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; | |
281 | clocks = <&utmi>, <&uhphs_clk>; | |
282 | clock-names = "usb_clk", "ehci_clk"; | |
283 | status = "disabled"; | |
284 | }; | |
285 | ||
286 | L2: cache-controller@00a00000 { | |
287 | compatible = "arm,pl310-cache"; | |
288 | reg = <0x00a00000 0x1000>; | |
289 | interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; | |
290 | cache-unified; | |
291 | cache-level = <2>; | |
292 | }; | |
293 | ||
28fe8007 RI |
294 | nand0: nand@80000000 { |
295 | compatible = "atmel,sama5d2-nand"; | |
296 | #address-cells = <1>; | |
297 | #size-cells = <1>; | |
298 | ranges; | |
299 | reg = < /* EBI CS3 */ | |
300 | 0x80000000 0x08000000 | |
301 | /* SMC PMECC regs */ | |
302 | 0xf8014070 0x00000490 | |
303 | /* SMC PMECC Error Location regs */ | |
304 | 0xf8014500 0x00000200 | |
305 | /* ROM Galois tables */ | |
306 | 0x00040000 0x00018000 | |
307 | >; | |
308 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; | |
309 | atmel,nand-addr-offset = <21>; | |
310 | atmel,nand-cmd-offset = <22>; | |
311 | atmel,nand-has-dma; | |
312 | atmel,has-pmecc; | |
313 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; | |
314 | status = "disabled"; | |
315 | ||
316 | nfc@c0000000 { | |
b8453d4e | 317 | compatible = "atmel,sama5d3-nfc"; |
28fe8007 RI |
318 | #address-cells = <1>; |
319 | #size-cells = <1>; | |
320 | reg = < /* NFC Command Registers */ | |
321 | 0xc0000000 0x08000000 | |
322 | /* NFC HSMC regs */ | |
323 | 0xf8014000 0x00000070 | |
324 | /* NFC SRAM banks */ | |
325 | 0x00100000 0x00100000 | |
326 | >; | |
327 | clocks = <&hsmc_clk>; | |
328 | atmel,write-by-sram; | |
329 | }; | |
330 | }; | |
331 | ||
512fc048 LD |
332 | sdmmc0: sdio-host@a0000000 { |
333 | compatible = "atmel,sama5d2-sdhci"; | |
334 | reg = <0xa0000000 0x300>; | |
335 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; | |
336 | clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; | |
337 | clock-names = "hclock", "multclk", "baseclk"; | |
338 | status = "disabled"; | |
339 | }; | |
340 | ||
341 | sdmmc1: sdio-host@b0000000 { | |
342 | compatible = "atmel,sama5d2-sdhci"; | |
343 | reg = <0xb0000000 0x300>; | |
344 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; | |
345 | clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; | |
346 | clock-names = "hclock", "multclk", "baseclk"; | |
347 | status = "disabled"; | |
348 | }; | |
349 | ||
e30cf8d3 LD |
350 | apb { |
351 | compatible = "simple-bus"; | |
352 | #address-cells = <1>; | |
353 | #size-cells = <1>; | |
354 | ranges; | |
355 | ||
fd718627 NF |
356 | hlcdc: hlcdc@f0000000 { |
357 | compatible = "atmel,sama5d2-hlcdc"; | |
358 | reg = <0xf0000000 0x2000>; | |
359 | interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; | |
360 | clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | |
361 | clock-names = "periph_clk","sys_clk", "slow_clk"; | |
362 | status = "disabled"; | |
363 | ||
364 | hlcdc-display-controller { | |
365 | compatible = "atmel,hlcdc-display-controller"; | |
366 | #address-cells = <1>; | |
367 | #size-cells = <0>; | |
368 | ||
369 | port@0 { | |
370 | #address-cells = <1>; | |
371 | #size-cells = <0>; | |
372 | reg = <0>; | |
373 | }; | |
374 | }; | |
375 | ||
376 | hlcdc_pwm: hlcdc-pwm { | |
377 | compatible = "atmel,hlcdc-pwm"; | |
378 | #pwm-cells = <3>; | |
379 | }; | |
380 | }; | |
381 | ||
e30cf8d3 LD |
382 | ramc0: ramc@f000c000 { |
383 | compatible = "atmel,sama5d3-ddramc"; | |
384 | reg = <0xf000c000 0x200>; | |
385 | clocks = <&ddrck>, <&mpddr_clk>; | |
386 | clock-names = "ddrck", "mpddr"; | |
387 | }; | |
388 | ||
389 | dma0: dma-controller@f0010000 { | |
390 | compatible = "atmel,sama5d4-dma"; | |
391 | reg = <0xf0010000 0x1000>; | |
392 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; | |
393 | #dma-cells = <1>; | |
394 | clocks = <&dma0_clk>; | |
395 | clock-names = "dma_clk"; | |
396 | }; | |
397 | ||
22eb6cc2 NF |
398 | /* Place dma1 here despite its address */ |
399 | dma1: dma-controller@f0004000 { | |
400 | compatible = "atmel,sama5d4-dma"; | |
401 | reg = <0xf0004000 0x1000>; | |
402 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; | |
403 | #dma-cells = <1>; | |
404 | clocks = <&dma1_clk>; | |
405 | clock-names = "dma_clk"; | |
406 | }; | |
407 | ||
e30cf8d3 | 408 | pmc: pmc@f0014000 { |
620f5033 | 409 | compatible = "atmel,sama5d2-pmc", "syscon"; |
e30cf8d3 LD |
410 | reg = <0xf0014000 0x160>; |
411 | interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; | |
412 | interrupt-controller; | |
413 | #address-cells = <1>; | |
414 | #size-cells = <0>; | |
415 | #interrupt-cells = <1>; | |
416 | ||
417 | main_rc_osc: main_rc_osc { | |
418 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
419 | #clock-cells = <0>; | |
420 | interrupt-parent = <&pmc>; | |
421 | interrupts = <AT91_PMC_MOSCRCS>; | |
422 | clock-frequency = <12000000>; | |
423 | clock-accuracy = <100000000>; | |
424 | }; | |
425 | ||
426 | main_osc: main_osc { | |
427 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
428 | #clock-cells = <0>; | |
429 | interrupt-parent = <&pmc>; | |
430 | interrupts = <AT91_PMC_MOSCS>; | |
431 | clocks = <&main_xtal>; | |
432 | }; | |
433 | ||
434 | main: mainck { | |
435 | compatible = "atmel,at91sam9x5-clk-main"; | |
436 | #clock-cells = <0>; | |
437 | interrupt-parent = <&pmc>; | |
438 | interrupts = <AT91_PMC_MOSCSELS>; | |
439 | clocks = <&main_rc_osc &main_osc>; | |
440 | }; | |
441 | ||
442 | plla: pllack { | |
443 | compatible = "atmel,sama5d3-clk-pll"; | |
444 | #clock-cells = <0>; | |
445 | interrupt-parent = <&pmc>; | |
446 | interrupts = <AT91_PMC_LOCKA>; | |
447 | clocks = <&main>; | |
448 | reg = <0>; | |
449 | atmel,clk-input-range = <12000000 12000000>; | |
450 | #atmel,pll-clk-output-range-cells = <4>; | |
451 | atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; | |
452 | }; | |
453 | ||
454 | plladiv: plladivck { | |
455 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
456 | #clock-cells = <0>; | |
457 | clocks = <&plla>; | |
458 | }; | |
459 | ||
460 | utmi: utmick { | |
461 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
462 | #clock-cells = <0>; | |
463 | interrupt-parent = <&pmc>; | |
464 | interrupts = <AT91_PMC_LOCKU>; | |
465 | clocks = <&main>; | |
466 | }; | |
467 | ||
468 | mck: masterck { | |
469 | compatible = "atmel,at91sam9x5-clk-master"; | |
470 | #clock-cells = <0>; | |
471 | interrupt-parent = <&pmc>; | |
472 | interrupts = <AT91_PMC_MCKRDY>; | |
473 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | |
474 | atmel,clk-output-range = <124000000 166000000>; | |
475 | atmel,clk-divisors = <1 2 4 3>; | |
476 | }; | |
477 | ||
478 | h32ck: h32mxck { | |
479 | #clock-cells = <0>; | |
480 | compatible = "atmel,sama5d4-clk-h32mx"; | |
481 | clocks = <&mck>; | |
482 | }; | |
483 | ||
484 | usb: usbck { | |
485 | compatible = "atmel,at91sam9x5-clk-usb"; | |
486 | #clock-cells = <0>; | |
487 | clocks = <&plladiv>, <&utmi>; | |
488 | }; | |
489 | ||
490 | prog: progck { | |
491 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
492 | #address-cells = <1>; | |
493 | #size-cells = <0>; | |
494 | interrupt-parent = <&pmc>; | |
495 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
496 | ||
497 | prog0: prog0 { | |
498 | #clock-cells = <0>; | |
499 | reg = <0>; | |
500 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
501 | }; | |
502 | ||
503 | prog1: prog1 { | |
504 | #clock-cells = <0>; | |
505 | reg = <1>; | |
506 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
507 | }; | |
508 | ||
509 | prog2: prog2 { | |
510 | #clock-cells = <0>; | |
511 | reg = <2>; | |
512 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
513 | }; | |
514 | }; | |
515 | ||
516 | systemck { | |
517 | compatible = "atmel,at91rm9200-clk-system"; | |
518 | #address-cells = <1>; | |
519 | #size-cells = <0>; | |
520 | ||
521 | ddrck: ddrck { | |
522 | #clock-cells = <0>; | |
523 | reg = <2>; | |
524 | clocks = <&mck>; | |
525 | }; | |
526 | ||
527 | lcdck: lcdck { | |
528 | #clock-cells = <0>; | |
529 | reg = <3>; | |
530 | clocks = <&mck>; | |
531 | }; | |
532 | ||
533 | uhpck: uhpck { | |
534 | #clock-cells = <0>; | |
535 | reg = <6>; | |
536 | clocks = <&usb>; | |
537 | }; | |
538 | ||
539 | udpck: udpck { | |
540 | #clock-cells = <0>; | |
541 | reg = <7>; | |
542 | clocks = <&usb>; | |
543 | }; | |
544 | ||
545 | pck0: pck0 { | |
546 | #clock-cells = <0>; | |
547 | reg = <8>; | |
548 | clocks = <&prog0>; | |
549 | }; | |
550 | ||
551 | pck1: pck1 { | |
552 | #clock-cells = <0>; | |
553 | reg = <9>; | |
554 | clocks = <&prog1>; | |
555 | }; | |
556 | ||
557 | pck2: pck2 { | |
558 | #clock-cells = <0>; | |
559 | reg = <10>; | |
560 | clocks = <&prog2>; | |
561 | }; | |
562 | ||
563 | iscck: iscck { | |
564 | #clock-cells = <0>; | |
565 | reg = <18>; | |
566 | clocks = <&mck>; | |
567 | }; | |
568 | }; | |
569 | ||
570 | periph32ck { | |
571 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
572 | #address-cells = <1>; | |
573 | #size-cells = <0>; | |
574 | clocks = <&h32ck>; | |
575 | ||
576 | macb0_clk: macb0_clk { | |
577 | #clock-cells = <0>; | |
578 | reg = <5>; | |
579 | atmel,clk-output-range = <0 83000000>; | |
580 | }; | |
581 | ||
582 | tdes_clk: tdes_clk { | |
583 | #clock-cells = <0>; | |
584 | reg = <11>; | |
585 | atmel,clk-output-range = <0 83000000>; | |
586 | }; | |
587 | ||
588 | matrix1_clk: matrix1_clk { | |
589 | #clock-cells = <0>; | |
590 | reg = <14>; | |
591 | }; | |
592 | ||
593 | hsmc_clk: hsmc_clk { | |
594 | #clock-cells = <0>; | |
595 | reg = <17>; | |
596 | }; | |
597 | ||
598 | pioA_clk: pioA_clk { | |
599 | #clock-cells = <0>; | |
600 | reg = <18>; | |
601 | atmel,clk-output-range = <0 83000000>; | |
602 | }; | |
603 | ||
604 | flx0_clk: flx0_clk { | |
605 | #clock-cells = <0>; | |
606 | reg = <19>; | |
607 | atmel,clk-output-range = <0 83000000>; | |
608 | }; | |
609 | ||
610 | flx1_clk: flx1_clk { | |
611 | #clock-cells = <0>; | |
612 | reg = <20>; | |
613 | atmel,clk-output-range = <0 83000000>; | |
614 | }; | |
615 | ||
616 | flx2_clk: flx2_clk { | |
617 | #clock-cells = <0>; | |
618 | reg = <21>; | |
619 | atmel,clk-output-range = <0 83000000>; | |
620 | }; | |
621 | ||
622 | flx3_clk: flx3_clk { | |
623 | #clock-cells = <0>; | |
624 | reg = <22>; | |
625 | atmel,clk-output-range = <0 83000000>; | |
626 | }; | |
627 | ||
628 | flx4_clk: flx4_clk { | |
629 | #clock-cells = <0>; | |
630 | reg = <23>; | |
631 | atmel,clk-output-range = <0 83000000>; | |
632 | }; | |
633 | ||
634 | uart0_clk: uart0_clk { | |
635 | #clock-cells = <0>; | |
636 | reg = <24>; | |
637 | atmel,clk-output-range = <0 83000000>; | |
638 | }; | |
639 | ||
640 | uart1_clk: uart1_clk { | |
641 | #clock-cells = <0>; | |
642 | reg = <25>; | |
643 | atmel,clk-output-range = <0 83000000>; | |
644 | }; | |
645 | ||
646 | uart2_clk: uart2_clk { | |
647 | #clock-cells = <0>; | |
648 | reg = <26>; | |
649 | atmel,clk-output-range = <0 83000000>; | |
650 | }; | |
651 | ||
652 | uart3_clk: uart3_clk { | |
653 | #clock-cells = <0>; | |
654 | reg = <27>; | |
655 | atmel,clk-output-range = <0 83000000>; | |
656 | }; | |
657 | ||
658 | uart4_clk: uart4_clk { | |
659 | #clock-cells = <0>; | |
660 | reg = <28>; | |
661 | atmel,clk-output-range = <0 83000000>; | |
662 | }; | |
663 | ||
664 | twi0_clk: twi0_clk { | |
665 | reg = <29>; | |
666 | #clock-cells = <0>; | |
667 | atmel,clk-output-range = <0 83000000>; | |
668 | }; | |
669 | ||
670 | twi1_clk: twi1_clk { | |
671 | #clock-cells = <0>; | |
672 | reg = <30>; | |
673 | atmel,clk-output-range = <0 83000000>; | |
674 | }; | |
675 | ||
676 | spi0_clk: spi0_clk { | |
677 | #clock-cells = <0>; | |
678 | reg = <33>; | |
679 | atmel,clk-output-range = <0 83000000>; | |
680 | }; | |
681 | ||
682 | spi1_clk: spi1_clk { | |
683 | #clock-cells = <0>; | |
684 | reg = <34>; | |
685 | atmel,clk-output-range = <0 83000000>; | |
686 | }; | |
687 | ||
688 | tcb0_clk: tcb0_clk { | |
689 | #clock-cells = <0>; | |
690 | reg = <35>; | |
691 | atmel,clk-output-range = <0 83000000>; | |
692 | }; | |
693 | ||
694 | tcb1_clk: tcb1_clk { | |
695 | #clock-cells = <0>; | |
696 | reg = <36>; | |
697 | atmel,clk-output-range = <0 83000000>; | |
698 | }; | |
699 | ||
700 | pwm_clk: pwm_clk { | |
701 | #clock-cells = <0>; | |
702 | reg = <38>; | |
703 | atmel,clk-output-range = <0 83000000>; | |
704 | }; | |
705 | ||
706 | adc_clk: adc_clk { | |
707 | #clock-cells = <0>; | |
708 | reg = <40>; | |
709 | atmel,clk-output-range = <0 83000000>; | |
710 | }; | |
711 | ||
712 | uhphs_clk: uhphs_clk { | |
713 | #clock-cells = <0>; | |
714 | reg = <41>; | |
715 | atmel,clk-output-range = <0 83000000>; | |
716 | }; | |
717 | ||
718 | udphs_clk: udphs_clk { | |
719 | #clock-cells = <0>; | |
720 | reg = <42>; | |
721 | atmel,clk-output-range = <0 83000000>; | |
722 | }; | |
723 | ||
724 | ssc0_clk: ssc0_clk { | |
725 | #clock-cells = <0>; | |
726 | reg = <43>; | |
727 | atmel,clk-output-range = <0 83000000>; | |
728 | }; | |
729 | ||
730 | ssc1_clk: ssc1_clk { | |
731 | #clock-cells = <0>; | |
732 | reg = <44>; | |
733 | atmel,clk-output-range = <0 83000000>; | |
734 | }; | |
735 | ||
736 | trng_clk: trng_clk { | |
737 | #clock-cells = <0>; | |
738 | reg = <47>; | |
739 | atmel,clk-output-range = <0 83000000>; | |
740 | }; | |
741 | ||
70450d4d SW |
742 | pdmic_clk: pdmic_clk { |
743 | #clock-cells = <0>; | |
744 | reg = <48>; | |
745 | atmel,clk-output-range = <0 83000000>; | |
746 | }; | |
747 | ||
d4ce5f44 AB |
748 | securam_clk: securam_clk { |
749 | #clock-cells = <0>; | |
750 | reg = <51>; | |
751 | }; | |
752 | ||
512fc048 LD |
753 | i2s0_clk: i2s0_clk { |
754 | #clock-cells = <0>; | |
755 | reg = <54>; | |
756 | atmel,clk-output-range = <0 83000000>; | |
757 | }; | |
758 | ||
759 | i2s1_clk: i2s1_clk { | |
760 | #clock-cells = <0>; | |
761 | reg = <55>; | |
762 | atmel,clk-output-range = <0 83000000>; | |
763 | }; | |
764 | ||
e30cf8d3 LD |
765 | classd_clk: classd_clk { |
766 | #clock-cells = <0>; | |
767 | reg = <59>; | |
768 | atmel,clk-output-range = <0 83000000>; | |
769 | }; | |
770 | }; | |
771 | ||
772 | periph64ck { | |
773 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
774 | #address-cells = <1>; | |
775 | #size-cells = <0>; | |
776 | clocks = <&mck>; | |
777 | ||
778 | dma0_clk: dma0_clk { | |
779 | #clock-cells = <0>; | |
780 | reg = <6>; | |
781 | }; | |
782 | ||
783 | dma1_clk: dma1_clk { | |
784 | #clock-cells = <0>; | |
785 | reg = <7>; | |
786 | }; | |
787 | ||
788 | aes_clk: aes_clk { | |
789 | #clock-cells = <0>; | |
790 | reg = <9>; | |
791 | }; | |
792 | ||
793 | aesb_clk: aesb_clk { | |
794 | #clock-cells = <0>; | |
795 | reg = <10>; | |
796 | }; | |
797 | ||
798 | sha_clk: sha_clk { | |
799 | #clock-cells = <0>; | |
800 | reg = <12>; | |
801 | }; | |
802 | ||
803 | mpddr_clk: mpddr_clk { | |
804 | #clock-cells = <0>; | |
805 | reg = <13>; | |
806 | }; | |
807 | ||
808 | matrix0_clk: matrix0_clk { | |
809 | #clock-cells = <0>; | |
810 | reg = <15>; | |
811 | }; | |
812 | ||
813 | sdmmc0_hclk: sdmmc0_hclk { | |
814 | #clock-cells = <0>; | |
815 | reg = <31>; | |
816 | }; | |
817 | ||
818 | sdmmc1_hclk: sdmmc1_hclk { | |
819 | #clock-cells = <0>; | |
820 | reg = <32>; | |
821 | }; | |
822 | ||
823 | lcdc_clk: lcdc_clk { | |
824 | #clock-cells = <0>; | |
825 | reg = <45>; | |
826 | }; | |
827 | ||
828 | isc_clk: isc_clk { | |
829 | #clock-cells = <0>; | |
830 | reg = <46>; | |
831 | }; | |
832 | ||
833 | qspi0_clk: qspi0_clk { | |
834 | #clock-cells = <0>; | |
835 | reg = <52>; | |
836 | }; | |
837 | ||
838 | qspi1_clk: qspi1_clk { | |
839 | #clock-cells = <0>; | |
840 | reg = <53>; | |
841 | }; | |
842 | }; | |
512fc048 LD |
843 | |
844 | gck { | |
845 | compatible = "atmel,sama5d2-clk-generated"; | |
846 | #address-cells = <1>; | |
847 | #size-cells = <0>; | |
848 | interrupt-parent = <&pmc>; | |
849 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
850 | ||
851 | sdmmc0_gclk: sdmmc0_gclk { | |
852 | #clock-cells = <0>; | |
853 | reg = <31>; | |
854 | }; | |
855 | ||
856 | sdmmc1_gclk: sdmmc1_gclk { | |
857 | #clock-cells = <0>; | |
858 | reg = <32>; | |
859 | }; | |
860 | ||
861 | tcb0_gclk: tcb0_gclk { | |
862 | #clock-cells = <0>; | |
863 | reg = <35>; | |
864 | atmel,clk-output-range = <0 83000000>; | |
865 | }; | |
866 | ||
867 | tcb1_gclk: tcb1_gclk { | |
868 | #clock-cells = <0>; | |
869 | reg = <36>; | |
870 | atmel,clk-output-range = <0 83000000>; | |
871 | }; | |
872 | ||
873 | pwm_gclk: pwm_gclk { | |
874 | #clock-cells = <0>; | |
875 | reg = <38>; | |
876 | atmel,clk-output-range = <0 83000000>; | |
877 | }; | |
878 | ||
70450d4d SW |
879 | pdmic_gclk: pdmic_gclk { |
880 | #clock-cells = <0>; | |
881 | reg = <48>; | |
882 | }; | |
883 | ||
512fc048 LD |
884 | i2s0_gclk: i2s0_gclk { |
885 | #clock-cells = <0>; | |
886 | reg = <54>; | |
887 | }; | |
888 | ||
889 | i2s1_gclk: i2s1_gclk { | |
890 | #clock-cells = <0>; | |
891 | reg = <55>; | |
892 | }; | |
893 | }; | |
e30cf8d3 LD |
894 | }; |
895 | ||
896 | sha@f0028000 { | |
897 | compatible = "atmel,at91sam9g46-sha"; | |
898 | reg = <0xf0028000 0x100>; | |
899 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | |
900 | dmas = <&dma0 | |
901 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
902 | AT91_XDMAC_DT_PERID(30))>; | |
903 | dma-names = "tx"; | |
904 | clocks = <&sha_clk>; | |
905 | clock-names = "sha_clk"; | |
512fc048 | 906 | status = "okay"; |
e30cf8d3 LD |
907 | }; |
908 | ||
909 | aes@f002c000 { | |
910 | compatible = "atmel,at91sam9g46-aes"; | |
911 | reg = <0xf002c000 0x100>; | |
912 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; | |
913 | dmas = <&dma0 | |
914 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
915 | AT91_XDMAC_DT_PERID(26))>, | |
916 | <&dma0 | |
917 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
918 | AT91_XDMAC_DT_PERID(27))>; | |
919 | dma-names = "tx", "rx"; | |
920 | clocks = <&aes_clk>; | |
921 | clock-names = "aes_clk"; | |
512fc048 | 922 | status = "okay"; |
e30cf8d3 LD |
923 | }; |
924 | ||
925 | spi0: spi@f8000000 { | |
926 | compatible = "atmel,at91rm9200-spi"; | |
927 | reg = <0xf8000000 0x100>; | |
928 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; | |
929 | dmas = <&dma0 | |
930 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
931 | AT91_XDMAC_DT_PERID(6))>, | |
932 | <&dma0 | |
933 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
934 | AT91_XDMAC_DT_PERID(7))>; | |
935 | dma-names = "tx", "rx"; | |
936 | clocks = <&spi0_clk>; | |
937 | clock-names = "spi_clk"; | |
938 | atmel,fifo-size = <16>; | |
939 | #address-cells = <1>; | |
940 | #size-cells = <0>; | |
941 | status = "disabled"; | |
942 | }; | |
943 | ||
6c1652af A |
944 | ssc0: ssc@f8004000 { |
945 | compatible = "atmel,at91sam9g45-ssc"; | |
946 | reg = <0xf8004000 0x4000>; | |
947 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; | |
948 | dmas = <&dma0 | |
949 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
950 | AT91_XDMAC_DT_PERID(21))>, | |
951 | <&dma0 | |
952 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
953 | AT91_XDMAC_DT_PERID(22))>; | |
954 | dma-names = "tx", "rx"; | |
955 | clocks = <&ssc0_clk>; | |
956 | clock-names = "pclk"; | |
957 | status = "disabled"; | |
958 | }; | |
959 | ||
e30cf8d3 LD |
960 | macb0: ethernet@f8008000 { |
961 | compatible = "atmel,sama5d2-gem"; | |
962 | reg = <0xf8008000 0x1000>; | |
963 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ | |
964 | 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ | |
965 | 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ | |
966 | #address-cells = <1>; | |
967 | #size-cells = <0>; | |
968 | clocks = <&macb0_clk>, <&macb0_clk>; | |
969 | clock-names = "hclk", "pclk"; | |
970 | status = "disabled"; | |
971 | }; | |
972 | ||
973 | tcb0: timer@f800c000 { | |
974 | compatible = "atmel,at91sam9x5-tcb"; | |
975 | reg = <0xf800c000 0x100>; | |
976 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; | |
761c5867 AB |
977 | clocks = <&tcb0_clk>, <&clk32k>; |
978 | clock-names = "t0_clk", "slow_clk"; | |
e30cf8d3 LD |
979 | }; |
980 | ||
981 | tcb1: timer@f8010000 { | |
982 | compatible = "atmel,at91sam9x5-tcb"; | |
983 | reg = <0xf8010000 0x100>; | |
984 | interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
761c5867 AB |
985 | clocks = <&tcb1_clk>, <&clk32k>; |
986 | clock-names = "t0_clk", "slow_clk"; | |
e30cf8d3 LD |
987 | }; |
988 | ||
70450d4d SW |
989 | pdmic: pdmic@f8018000 { |
990 | compatible = "atmel,sama5d2-pdmic"; | |
991 | reg = <0xf8018000 0x124>; | |
992 | interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; | |
993 | dmas = <&dma0 | |
994 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
995 | | AT91_XDMAC_DT_PERID(50))>; | |
996 | dma-names = "rx"; | |
997 | clocks = <&pdmic_clk>, <&pdmic_gclk>; | |
998 | clock-names = "pclk", "gclk"; | |
999 | status = "disabled"; | |
1000 | }; | |
1001 | ||
e30cf8d3 LD |
1002 | uart0: serial@f801c000 { |
1003 | compatible = "atmel,at91sam9260-usart"; | |
1004 | reg = <0xf801c000 0x100>; | |
1005 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
1006 | dmas = <&dma0 |
1007 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1008 | AT91_XDMAC_DT_PERID(35))>, | |
1009 | <&dma0 | |
1010 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1011 | AT91_XDMAC_DT_PERID(36))>; | |
1012 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1013 | clocks = <&uart0_clk>; |
1014 | clock-names = "usart"; | |
1015 | status = "disabled"; | |
1016 | }; | |
1017 | ||
1018 | uart1: serial@f8020000 { | |
1019 | compatible = "atmel,at91sam9260-usart"; | |
1020 | reg = <0xf8020000 0x100>; | |
1021 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
1022 | dmas = <&dma0 |
1023 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1024 | AT91_XDMAC_DT_PERID(37))>, | |
1025 | <&dma0 | |
1026 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1027 | AT91_XDMAC_DT_PERID(38))>; | |
1028 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1029 | clocks = <&uart1_clk>; |
1030 | clock-names = "usart"; | |
1031 | status = "disabled"; | |
1032 | }; | |
1033 | ||
1034 | uart2: serial@f8024000 { | |
1035 | compatible = "atmel,at91sam9260-usart"; | |
1036 | reg = <0xf8024000 0x100>; | |
1037 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
1038 | dmas = <&dma0 |
1039 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1040 | AT91_XDMAC_DT_PERID(39))>, | |
1041 | <&dma0 | |
1042 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1043 | AT91_XDMAC_DT_PERID(40))>; | |
1044 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1045 | clocks = <&uart2_clk>; |
1046 | clock-names = "usart"; | |
1047 | status = "disabled"; | |
1048 | }; | |
1049 | ||
1050 | i2c0: i2c@f8028000 { | |
1051 | compatible = "atmel,sama5d2-i2c"; | |
1052 | reg = <0xf8028000 0x100>; | |
1053 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; | |
1054 | dmas = <&dma0 | |
1055 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1056 | AT91_XDMAC_DT_PERID(0))>, | |
1057 | <&dma0 | |
1058 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1059 | AT91_XDMAC_DT_PERID(1))>; | |
1060 | dma-names = "tx", "rx"; | |
1061 | #address-cells = <1>; | |
1062 | #size-cells = <0>; | |
1063 | clocks = <&twi0_clk>; | |
54475c8d | 1064 | atmel,fifo-size = <16>; |
e30cf8d3 LD |
1065 | status = "disabled"; |
1066 | }; | |
1067 | ||
c8f26c26 CP |
1068 | sfr: sfr@f8030000 { |
1069 | compatible = "atmel,sama5d2-sfr", "syscon"; | |
1070 | reg = <0xf8030000 0x98>; | |
1071 | }; | |
1072 | ||
512fc048 LD |
1073 | flx0: flexcom@f8034000 { |
1074 | compatible = "atmel,sama5d2-flexcom"; | |
1075 | reg = <0xf8034000 0x200>; | |
1076 | clocks = <&flx0_clk>; | |
1077 | #address-cells = <1>; | |
1078 | #size-cells = <1>; | |
1079 | ranges = <0x0 0xf8034000 0x800>; | |
1080 | status = "disabled"; | |
1081 | }; | |
1082 | ||
1083 | flx1: flexcom@f8038000 { | |
1084 | compatible = "atmel,sama5d2-flexcom"; | |
1085 | reg = <0xf8038000 0x200>; | |
1086 | clocks = <&flx1_clk>; | |
1087 | #address-cells = <1>; | |
1088 | #size-cells = <1>; | |
1089 | ranges = <0x0 0xf8038000 0x800>; | |
1090 | status = "disabled"; | |
1091 | }; | |
1092 | ||
d4ce5f44 AB |
1093 | securam: sram@f8044000 { |
1094 | compatible = "atmel,sama5d2-securam", "mmio-sram"; | |
1095 | reg = <0xf8044000 0x1420>; | |
1096 | clocks = <&securam_clk>; | |
1097 | #address-cells = <1>; | |
1098 | #size-cells = <1>; | |
1099 | ranges = <0 0xf8044000 0x1420>; | |
1100 | }; | |
1101 | ||
512fc048 LD |
1102 | rstc@f8048000 { |
1103 | compatible = "atmel,sama5d3-rstc"; | |
1104 | reg = <0xf8048000 0x10>; | |
1105 | clocks = <&clk32k>; | |
1106 | }; | |
1107 | ||
e4b9a21b NF |
1108 | shdwc@f8048010 { |
1109 | compatible = "atmel,sama5d2-shdwc"; | |
1110 | reg = <0xf8048010 0x10>; | |
1111 | clocks = <&clk32k>; | |
1112 | #address-cells = <1>; | |
1113 | #size-cells = <0>; | |
1114 | atmel,wakeup-rtc-timer; | |
1115 | }; | |
1116 | ||
e30cf8d3 LD |
1117 | pit: timer@f8048030 { |
1118 | compatible = "atmel,at91sam9260-pit"; | |
1119 | reg = <0xf8048030 0x10>; | |
1120 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; | |
1121 | clocks = <&h32ck>; | |
1122 | }; | |
1123 | ||
92bd7aa4 WY |
1124 | watchdog@f8048040 { |
1125 | compatible = "atmel,sama5d4-wdt"; | |
1126 | reg = <0xf8048040 0x10>; | |
1127 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; | |
51755007 | 1128 | clocks = <&clk32k>; |
92bd7aa4 WY |
1129 | status = "disabled"; |
1130 | }; | |
1131 | ||
58c016e0 AB |
1132 | clk32k: sckc@f8048050 { |
1133 | compatible = "atmel,sama5d4-sckc"; | |
e30cf8d3 LD |
1134 | reg = <0xf8048050 0x4>; |
1135 | ||
58c016e0 AB |
1136 | clocks = <&slow_xtal>; |
1137 | #clock-cells = <0>; | |
e30cf8d3 LD |
1138 | }; |
1139 | ||
1140 | rtc@f80480b0 { | |
1141 | compatible = "atmel,at91rm9200-rtc"; | |
1142 | reg = <0xf80480b0 0x30>; | |
1143 | interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; | |
761c5867 | 1144 | clocks = <&clk32k>; |
e30cf8d3 LD |
1145 | }; |
1146 | ||
1147 | spi1: spi@fc000000 { | |
1148 | compatible = "atmel,at91rm9200-spi"; | |
1149 | reg = <0xfc000000 0x100>; | |
1150 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; | |
1151 | dmas = <&dma0 | |
1152 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1153 | AT91_XDMAC_DT_PERID(8))>, | |
1154 | <&dma0 | |
1155 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1156 | AT91_XDMAC_DT_PERID(9))>; | |
1157 | dma-names = "tx", "rx"; | |
1158 | clocks = <&spi1_clk>; | |
1159 | clock-names = "spi_clk"; | |
1160 | atmel,fifo-size = <16>; | |
1161 | #address-cells = <1>; | |
1162 | #size-cells = <0>; | |
1163 | status = "disabled"; | |
1164 | }; | |
1165 | ||
1166 | uart3: serial@fc008000 { | |
1167 | compatible = "atmel,at91sam9260-usart"; | |
1168 | reg = <0xfc008000 0x100>; | |
1169 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; | |
f72d20fe | 1170 | dmas = <&dma1 |
b1708b72 NF |
1171 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
1172 | AT91_XDMAC_DT_PERID(41))>, | |
f72d20fe | 1173 | <&dma1 |
b1708b72 NF |
1174 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
1175 | AT91_XDMAC_DT_PERID(42))>; | |
1176 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1177 | clocks = <&uart3_clk>; |
1178 | clock-names = "usart"; | |
1179 | status = "disabled"; | |
1180 | }; | |
1181 | ||
1182 | uart4: serial@fc00c000 { | |
1183 | compatible = "atmel,at91sam9260-usart"; | |
1184 | reg = <0xfc00c000 0x100>; | |
b1708b72 NF |
1185 | dmas = <&dma0 |
1186 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1187 | AT91_XDMAC_DT_PERID(43))>, | |
1188 | <&dma0 | |
1189 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1190 | AT91_XDMAC_DT_PERID(44))>; | |
1191 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1192 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; |
1193 | clocks = <&uart4_clk>; | |
1194 | clock-names = "usart"; | |
1195 | status = "disabled"; | |
1196 | }; | |
1197 | ||
512fc048 LD |
1198 | flx2: flexcom@fc010000 { |
1199 | compatible = "atmel,sama5d2-flexcom"; | |
1200 | reg = <0xfc010000 0x200>; | |
1201 | clocks = <&flx2_clk>; | |
1202 | #address-cells = <1>; | |
1203 | #size-cells = <1>; | |
1204 | ranges = <0x0 0xfc010000 0x800>; | |
1205 | status = "disabled"; | |
1206 | }; | |
1207 | ||
1208 | flx3: flexcom@fc014000 { | |
1209 | compatible = "atmel,sama5d2-flexcom"; | |
1210 | reg = <0xfc014000 0x200>; | |
1211 | clocks = <&flx3_clk>; | |
1212 | #address-cells = <1>; | |
1213 | #size-cells = <1>; | |
1214 | ranges = <0x0 0xfc014000 0x800>; | |
1215 | status = "disabled"; | |
1216 | }; | |
1217 | ||
1218 | flx4: flexcom@fc018000 { | |
1219 | compatible = "atmel,sama5d2-flexcom"; | |
1220 | reg = <0xfc018000 0x200>; | |
1221 | clocks = <&flx4_clk>; | |
1222 | #address-cells = <1>; | |
1223 | #size-cells = <1>; | |
1224 | ranges = <0x0 0xfc018000 0x800>; | |
1225 | status = "disabled"; | |
1226 | }; | |
1227 | ||
02eb8d68 MW |
1228 | trng@fc01c000 { |
1229 | compatible = "atmel,at91sam9g45-trng"; | |
1230 | reg = <0xfc01c000 0x100>; | |
1231 | interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; | |
1232 | clocks = <&trng_clk>; | |
1233 | }; | |
1234 | ||
e30cf8d3 LD |
1235 | aic: interrupt-controller@fc020000 { |
1236 | #interrupt-cells = <3>; | |
1237 | compatible = "atmel,sama5d2-aic"; | |
1238 | interrupt-controller; | |
1239 | reg = <0xfc020000 0x200>; | |
1240 | atmel,external-irqs = <49>; | |
1241 | }; | |
1242 | ||
1243 | i2c1: i2c@fc028000 { | |
1244 | compatible = "atmel,sama5d2-i2c"; | |
1245 | reg = <0xfc028000 0x100>; | |
1246 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; | |
1247 | dmas = <&dma0 | |
1248 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1249 | AT91_XDMAC_DT_PERID(2))>, | |
1250 | <&dma0 | |
1251 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1252 | AT91_XDMAC_DT_PERID(3))>; | |
1253 | dma-names = "tx", "rx"; | |
1254 | #address-cells = <1>; | |
1255 | #size-cells = <0>; | |
1256 | clocks = <&twi1_clk>; | |
54475c8d | 1257 | atmel,fifo-size = <16>; |
e30cf8d3 LD |
1258 | status = "disabled"; |
1259 | }; | |
f6c804b0 | 1260 | |
aea14e14 LD |
1261 | adc: adc@fc030000 { |
1262 | compatible = "atmel,sama5d2-adc"; | |
1263 | reg = <0xfc030000 0x100>; | |
1264 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; | |
1265 | clocks = <&adc_clk>; | |
1266 | clock-names = "adc_clk"; | |
1267 | atmel,min-sample-rate-hz = <200000>; | |
1268 | atmel,max-sample-rate-hz = <20000000>; | |
1269 | atmel,startup-time-ms = <4>; | |
1270 | status = "disabled"; | |
1271 | }; | |
1272 | ||
f6c804b0 LD |
1273 | pioA: pinctrl@fc038000 { |
1274 | compatible = "atmel,sama5d2-pinctrl"; | |
1275 | reg = <0xfc038000 0x600>; | |
1276 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, | |
1277 | <68 IRQ_TYPE_LEVEL_HIGH 7>, | |
1278 | <69 IRQ_TYPE_LEVEL_HIGH 7>, | |
1279 | <70 IRQ_TYPE_LEVEL_HIGH 7>; | |
1280 | interrupt-controller; | |
1281 | #interrupt-cells = <2>; | |
1282 | gpio-controller; | |
1283 | #gpio-cells = <2>; | |
1284 | clocks = <&pioA_clk>; | |
1285 | }; | |
c0d6fe2f | 1286 | |
d44432df AB |
1287 | secumod@fc040000 { |
1288 | compatible = "atmel,sama5d2-secumod", "syscon"; | |
1289 | reg = <0xfc040000 0x100>; | |
1290 | }; | |
1291 | ||
512fc048 LD |
1292 | tdes@fc044000 { |
1293 | compatible = "atmel,at91sam9g46-tdes"; | |
1294 | reg = <0xfc044000 0x100>; | |
1295 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; | |
1296 | dmas = <&dma0 | |
1297 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1298 | AT91_XDMAC_DT_PERID(28))>, | |
1299 | <&dma0 | |
1300 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1301 | AT91_XDMAC_DT_PERID(29))>; | |
1302 | dma-names = "tx", "rx"; | |
1303 | clocks = <&tdes_clk>; | |
1304 | clock-names = "tdes_clk"; | |
1305 | status = "okay"; | |
1306 | }; | |
d77c2387 LD |
1307 | |
1308 | chipid@fc069000 { | |
1309 | compatible = "atmel,sama5d2-chipid"; | |
1310 | reg = <0xfc069000 0x8>; | |
1311 | }; | |
e30cf8d3 LD |
1312 | }; |
1313 | }; | |
1314 | }; |