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ARM: at91/dt: trivial: fix USB udc compatible string
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
35d35aae 16#include <dt-bindings/clock/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
f1ea096c 29 serial5 = &uart0;
655ff266
LD		 30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
655ff266
LD		 36 i2c0 = &i2c0;
37 i2c1 = &i2c1;
38 i2c2 = &i2c2;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
f3ab0527 41 pwm0 = &pwm0;
655ff266
LD		 42 };
43 cpus {
8b2efa89
AB		 44 #address-cells = <1>;
45 #size-cells = <0>;
655ff266 46 cpu@0 {
e757a6ee 47 device_type = "cpu";
655ff266 48 compatible = "arm,cortex-a5";
e757a6ee 49 reg = <0x0>;
655ff266
LD		 50 };
51 };
52
d9da9778
AB		 53 pmu {
54 compatible = "arm,cortex-a5-pmu";
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
56 };
57
655ff266
LD		 58 memory {
59 reg = <0x20000000 0x8000000>;
60 };
61
334394c0
AB		 62 clocks {
63 slow_xtal: slow_xtal {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
4753219d 68
334394c0
AB		 69 main_xtal: main_xtal {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <0>;
73 };
4753219d 74
d2e8190b
BB		 75 adc_op_clk: adc_op_clk{
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <20000000>;
79 };
80 };
81
f04660e4
AB		 82 sram: sram@00300000 {
83 compatible = "mmio-sram";
84 reg = <0x00300000 0x20000>;
85 };
86
655ff266
LD		 87 ahb {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 apb {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98
99 mmc0: mmc@f0000000 {
100 compatible = "atmel,hsmci";
101 reg = <0xf0000000 0x600>;
5e8b3bc3 102 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 103 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 104 dma-names = "rxtx";
655ff266
LD		 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
107 status = "disabled";
108 #address-cells = <1>;
109 #size-cells = <0>;
d2e8190b
BB		 110 clocks = <&mci0_clk>;
111 clock-names = "mci_clk";
655ff266
LD		 112 };
113
114 spi0: spi@f0004000 {
115 #address-cells = <1>;
116 #size-cells = <0>;
b7ef678e 117 compatible = "atmel,at91rm9200-spi";
655ff266 118 reg = <0xf0004000 0x100>;
5e8b3bc3 119 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 120 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
121 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
122 dma-names = "tx", "rx";
655ff266
LD		 123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 125 clocks = <&spi0_clk>;
126 clock-names = "spi_clk";
655ff266
LD		 127 status = "disabled";
128 };
129
130 ssc0: ssc@f0008000 {
131 compatible = "atmel,at91sam9g45-ssc";
132 reg = <0xf0008000 0x4000>;
5e8b3bc3 133 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 134 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
135 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
136 dma-names = "tx", "rx";
655ff266
LD		 137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 139 clocks = <&ssc0_clk>;
140 clock-names = "pclk";
655ff266
LD		 141 status = "disabled";
142 };
143
655ff266
LD		 144 tcb0: timer@f0010000 {
145 compatible = "atmel,at91sam9x5-tcb";
146 reg = <0xf0010000 0x100>;
5e8b3bc3 147 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 148 clocks = <&tcb0_clk>;
149 clock-names = "t0_clk";
655ff266
LD		 150 };
151
152 i2c0: i2c@f0014000 {
153 compatible = "atmel,at91sam9x5-i2c";
154 reg = <0xf0014000 0x4000>;
5e8b3bc3 155 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 156 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
157 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 158 dma-names = "tx", "rx";
655ff266
LD		 159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c0>;
161 #address-cells = <1>;
162 #size-cells = <0>;
d2e8190b 163 clocks = <&twi0_clk>;
655ff266
LD		 164 status = "disabled";
165 };
166
167 i2c1: i2c@f0018000 {
168 compatible = "atmel,at91sam9x5-i2c";
169 reg = <0xf0018000 0x4000>;
5e8b3bc3 170 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 171 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
172 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 173 dma-names = "tx", "rx";
655ff266
LD		 174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c1>;
176 #address-cells = <1>;
177 #size-cells = <0>;
d2e8190b 178 clocks = <&twi1_clk>;
655ff266
LD		 179 status = "disabled";
180 };
181
182 usart0: serial@f001c000 {
183 compatible = "atmel,at91sam9260-usart";
184 reg = <0xf001c000 0x100>;
5e8b3bc3 185 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 186 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
187 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
188 dma-names = "tx", "rx";
655ff266
LD		 189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 191 clocks = <&usart0_clk>;
192 clock-names = "usart";
655ff266
LD		 193 status = "disabled";
194 };
195
196 usart1: serial@f0020000 {
197 compatible = "atmel,at91sam9260-usart";
198 reg = <0xf0020000 0x100>;
5e8b3bc3 199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 200 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
201 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
202 dma-names = "tx", "rx";
655ff266
LD		 203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 205 clocks = <&usart1_clk>;
206 clock-names = "usart";
655ff266
LD		 207 status = "disabled";
208 };
209
f1ea096c
NF		 210 uart0: serial@f0024000 {
211 compatible = "atmel,at91sam9260-usart";
212 reg = <0xf0024000 0x100>;
213 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart0>;
216 clocks = <&uart0_clk>;
217 clock-names = "usart";
218 status = "disabled";
219 };
220
f3ab0527
BS		 221 pwm0: pwm@f002c000 {
222 compatible = "atmel,sama5d3-pwm";
223 reg = <0xf002c000 0x300>;
224 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
225 #pwm-cells = <3>;
226 clocks = <&pwm_clk>;
227 status = "disabled";
228 };
655ff266 229
655ff266
LD		 230 isi: isi@f0034000 {
231 compatible = "atmel,at91sam9g45-isi";
232 reg = <0xf0034000 0x4000>;
5e8b3bc3 233 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
4dd32e6d
JW		 234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_isi_data_0_7>;
b00122f6
JW		 236 clocks = <&isi_clk>;
237 clock-names = "isi_clk";
655ff266 238 status = "disabled";
4dd32e6d
JW		 239 port {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 };
655ff266
LD		 243 };
244
6ced9f4a
AB		 245 sfr: sfr@f0038000 {
246 compatible = "atmel,sama5d3-sfr", "syscon";
247 reg = <0xf0038000 0x60>;
248 };
249
655ff266
LD		 250 mmc1: mmc@f8000000 {
251 compatible = "atmel,hsmci";
252 reg = <0xf8000000 0x600>;
5e8b3bc3 253 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 254 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 255 dma-names = "rxtx";
655ff266
LD		 256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
258 status = "disabled";
259 #address-cells = <1>;
260 #size-cells = <0>;
d2e8190b
BB		 261 clocks = <&mci1_clk>;
262 clock-names = "mci_clk";
655ff266
LD		 263 };
264
655ff266
LD		 265 spi1: spi@f8008000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
b7ef678e 268 compatible = "atmel,at91rm9200-spi";
655ff266 269 reg = <0xf8008000 0x100>;
5e8b3bc3 270 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 271 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
272 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
273 dma-names = "tx", "rx";
655ff266
LD		 274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 276 clocks = <&spi1_clk>;
277 clock-names = "spi_clk";
655ff266
LD		 278 status = "disabled";
279 };
280
281 ssc1: ssc@f800c000 {
282 compatible = "atmel,at91sam9g45-ssc";
283 reg = <0xf800c000 0x4000>;
5e8b3bc3 284 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 285 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
286 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
287 dma-names = "tx", "rx";
655ff266
LD		 288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 290 clocks = <&ssc1_clk>;
291 clock-names = "pclk";
655ff266
LD		 292 status = "disabled";
293 };
294
655ff266 295 adc0: adc@f8018000 {
b3b84dec
AB		 296 #address-cells = <1>;
297 #size-cells = <0>;
9879b96d 298 compatible = "atmel,at91sam9x5-adc";
655ff266 299 reg = <0xf8018000 0x100>;
5e8b3bc3 300 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 301 pinctrl-names = "default";
302 pinctrl-0 = <
303 &pinctrl_adc0_adtrg
304 &pinctrl_adc0_ad0
305 &pinctrl_adc0_ad1
306 &pinctrl_adc0_ad2
307 &pinctrl_adc0_ad3
308 &pinctrl_adc0_ad4
309 &pinctrl_adc0_ad5
310 &pinctrl_adc0_ad6
311 &pinctrl_adc0_ad7
312 &pinctrl_adc0_ad8
313 &pinctrl_adc0_ad9
314 &pinctrl_adc0_ad10
315 &pinctrl_adc0_ad11
316 >;
d2e8190b
BB		 317 clocks = <&adc_clk>,
318 <&adc_op_clk>;
319 clock-names = "adc_clk", "adc_op_clk";
655ff266 320 atmel,adc-channels-used = <0xfff>;
655ff266 321 atmel,adc-startup-time = <40>;
b3b84dec 322 atmel,adc-use-external-triggers;
655ff266
LD		 323 atmel,adc-vref = <3000>;
324 atmel,adc-res = <10 12>;
325 atmel,adc-res-names = "lowres", "highres";
326 status = "disabled";
327
328 trigger@0 {
b3b84dec 329 reg = <0>;
655ff266
LD		 330 trigger-name = "external-rising";
331 trigger-value = <0x1>;
332 trigger-external;
333 };
334 trigger@1 {
b3b84dec 335 reg = <1>;
655ff266
LD		 336 trigger-name = "external-falling";
337 trigger-value = <0x2>;
338 trigger-external;
339 };
340 trigger@2 {
b3b84dec 341 reg = <2>;
655ff266
LD		 342 trigger-name = "external-any";
343 trigger-value = <0x3>;
344 trigger-external;
345 };
346 trigger@3 {
b3b84dec 347 reg = <3>;
655ff266
LD		 348 trigger-name = "continuous";
349 trigger-value = <0x6>;
350 };
351 };
352
655ff266
LD		 353 i2c2: i2c@f801c000 {
354 compatible = "atmel,at91sam9x5-i2c";
355 reg = <0xf801c000 0x4000>;
5e8b3bc3 356 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 357 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
358 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 359 dma-names = "tx", "rx";
557844ec
NF		 360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 362 #address-cells = <1>;
363 #size-cells = <0>;
d2e8190b 364 clocks = <&twi2_clk>;
655ff266
LD		 365 status = "disabled";
366 };
367
368 usart2: serial@f8020000 {
369 compatible = "atmel,at91sam9260-usart";
370 reg = <0xf8020000 0x100>;
5e8b3bc3 371 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 372 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
373 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
374 dma-names = "tx", "rx";
655ff266
LD		 375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 377 clocks = <&usart2_clk>;
378 clock-names = "usart";
655ff266
LD		 379 status = "disabled";
380 };
381
382 usart3: serial@f8024000 {
383 compatible = "atmel,at91sam9260-usart";
384 reg = <0xf8024000 0x100>;
5e8b3bc3 385 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 386 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
387 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
388 dma-names = "tx", "rx";
655ff266
LD		 389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 391 clocks = <&usart3_clk>;
392 clock-names = "usart";
655ff266
LD		 393 status = "disabled";
394 };
395
655ff266 396 sha@f8034000 {
c76f266d 397 compatible = "atmel,at91sam9g46-sha";
655ff266 398 reg = <0xf8034000 0x100>;
5e8b3bc3 399 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 400 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
401 dma-names = "tx";
4df4f446
BB		 402 clocks = <&sha_clk>;
403 clock-names = "sha_clk";
655ff266
LD		 404 };
405
406 aes@f8038000 {
c76f266d 407 compatible = "atmel,at91sam9g46-aes";
655ff266 408 reg = <0xf8038000 0x100>;
07f7d503 409 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 410 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
411 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
412 dma-names = "tx", "rx";
f68cd356
BB		 413 clocks = <&aes_clk>;
414 clock-names = "aes_clk";
655ff266
LD		 415 };
416
417 tdes@f803c000 {
c76f266d 418 compatible = "atmel,at91sam9g46-tdes";
655ff266 419 reg = <0xf803c000 0x100>;
5e8b3bc3 420 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 421 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
422 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
423 dma-names = "tx", "rx";
45e5c2cb
BB		 424 clocks = <&tdes_clk>;
425 clock-names = "tdes_clk";
655ff266
LD		 426 };
427
428 dma0: dma-controller@ffffe600 {
429 compatible = "atmel,at91sam9g45-dma";
430 reg = <0xffffe600 0x200>;
5e8b3bc3 431 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 432 #dma-cells = <2>;
d2e8190b
BB		 433 clocks = <&dma0_clk>;
434 clock-names = "dma_clk";
655ff266
LD		 435 };
436
437 dma1: dma-controller@ffffe800 {
438 compatible = "atmel,at91sam9g45-dma";
439 reg = <0xffffe800 0x200>;
5e8b3bc3 440 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 441 #dma-cells = <2>;
d2e8190b
BB		 442 clocks = <&dma1_clk>;
443 clock-names = "dma_clk";
655ff266
LD		 444 };
445
446 ramc0: ramc@ffffea00 {
063de897 447 compatible = "atmel,sama5d3-ddramc";
655ff266 448 reg = <0xffffea00 0x200>;
063de897
AB		 449 clocks = <&ddrck>, <&mpddr_clk>;
450 clock-names = "ddrck", "mpddr";
655ff266
LD		 451 };
452
453 dbgu: serial@ffffee00 {
8c07f664 454 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
655ff266 455 reg = <0xffffee00 0x200>;
5e8b3bc3 456 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
d24cd783
LD		 457 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
458 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
459 dma-names = "tx", "rx";
655ff266
LD		 460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 462 clocks = <&dbgu_clk>;
463 clock-names = "usart";
655ff266
LD		 464 status = "disabled";
465 };
466
467 aic: interrupt-controller@fffff000 {
468 #interrupt-cells = <3>;
469 compatible = "atmel,sama5d3-aic";
470 interrupt-controller;
471 reg = <0xfffff000 0x200>;
472 atmel,external-irqs = <47>;
473 };
474
475 pinctrl@fffff200 {
476 #address-cells = <1>;
477 #size-cells = <1>;
e0065cf7 478 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
655ff266
LD		 479 ranges = <0xfffff200 0xfffff200 0xa00>;
480 atmel,mux-mask = <
481 /* A B C */
482 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
483 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
484 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
485 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
486 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
487 >;
488
489 /* shared pinctrl settings */
490 adc0 {
491 pinctrl_adc0_adtrg: adc0_adtrg {
492 atmel,pins =
c9d0f317 493 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 494 };
495 pinctrl_adc0_ad0: adc0_ad0 {
496 atmel,pins =
c9d0f317 497 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 498 };
499 pinctrl_adc0_ad1: adc0_ad1 {
500 atmel,pins =
c9d0f317 501 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 502 };
503 pinctrl_adc0_ad2: adc0_ad2 {
504 atmel,pins =
c9d0f317 505 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 506 };
507 pinctrl_adc0_ad3: adc0_ad3 {
508 atmel,pins =
c9d0f317 509 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 510 };
511 pinctrl_adc0_ad4: adc0_ad4 {
512 atmel,pins =
c9d0f317 513 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 514 };
515 pinctrl_adc0_ad5: adc0_ad5 {
516 atmel,pins =
c9d0f317 517 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 518 };
519 pinctrl_adc0_ad6: adc0_ad6 {
520 atmel,pins =
c9d0f317 521 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 522 };
523 pinctrl_adc0_ad7: adc0_ad7 {
524 atmel,pins =
c9d0f317 525 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 526 };
527 pinctrl_adc0_ad8: adc0_ad8 {
528 atmel,pins =
c9d0f317 529 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 530 };
531 pinctrl_adc0_ad9: adc0_ad9 {
532 atmel,pins =
c9d0f317 533 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 534 };
535 pinctrl_adc0_ad10: adc0_ad10 {
536 atmel,pins =
c9d0f317 537 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 538 };
539 pinctrl_adc0_ad11: adc0_ad11 {
540 atmel,pins =
c9d0f317 541 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 542 };
543 };
544
655ff266
LD		 545 dbgu {
546 pinctrl_dbgu: dbgu-0 {
547 atmel,pins =
c9d0f317
JCPV		 548 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
549 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 550 };
551 };
552
553 i2c0 {
554 pinctrl_i2c0: i2c0-0 {
555 atmel,pins =
c9d0f317
JCPV		 556 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
557 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 558 };
559 };
560
561 i2c1 {
562 pinctrl_i2c1: i2c1-0 {
563 atmel,pins =
c9d0f317
JCPV		 564 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
565 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 566 };
567 };
568
557844ec
NF		 569 i2c2 {
570 pinctrl_i2c2: i2c2-0 {
571 atmel,pins =
572 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
573 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
574 };
575 };
576
655ff266 577 isi {
cbaa29c4 578 pinctrl_isi_data_0_7: isi-0-data-0-7 {
655ff266 579 atmel,pins =
c9d0f317
JCPV		 580 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
581 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
582 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
583 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
584 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
585 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
586 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
587 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
588 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
589 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
cbaa29c4
BS		 590 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
591 };
592
593 pinctrl_isi_data_8_9: isi-0-data-8-9 {
594 atmel,pins =
595 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
c9d0f317 596 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266 597 };
cbaa29c4 598
3d755488
BS		 599 pinctrl_isi_data_10_11: isi-0-data-10-11 {
600 atmel,pins =
601 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
602 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
603 };
655ff266
LD		 604 };
605
655ff266
LD		 606 mmc0 {
607 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
608 atmel,pins =
c9d0f317
JCPV		 609 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
610 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
611 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 612 };
613 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
614 atmel,pins =
c9d0f317
JCPV		 615 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
616 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
617 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 618 };
619 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
620 atmel,pins =
c9d0f317
JCPV		 621 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
622 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
623 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
624 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 625 };
626 };
627
628 mmc1 {
629 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
630 atmel,pins =
c9d0f317
JCPV		 631 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
632 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
633 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 634 };
635 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
636 atmel,pins =
c9d0f317
JCPV		 637 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
638 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
639 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 640 };
641 };
642
655ff266
LD		 643 nand0 {
644 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
645 atmel,pins =
c9d0f317
JCPV		 646 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
647 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 648 };
649 };
650
5eefd5f4
NF		 651 pwm0 {
652 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
653 atmel,pins =
654 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
655 };
656 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
657 atmel,pins =
658 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
659 };
660 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
661 atmel,pins =
662 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
663 };
664 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
665 atmel,pins =
666 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
667 };
668
669 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
670 atmel,pins =
671 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
672 };
673 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
674 atmel,pins =
675 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
676 };
677 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
678 atmel,pins =
679 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
680 };
681 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
682 atmel,pins =
683 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
684 };
685 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
686 atmel,pins =
687 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
688 };
689 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
690 atmel,pins =
691 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
692 };
693
694 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
695 atmel,pins =
696 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
697 };
698 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
699 atmel,pins =
700 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
701 };
702 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
703 atmel,pins =
704 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
705 };
706 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
707 atmel,pins =
708 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
709 };
710
711 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
712 atmel,pins =
713 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
714 };
715 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
716 atmel,pins =
717 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
718 };
719 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
720 atmel,pins =
721 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
722 };
723 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
724 atmel,pins =
725 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
726 };
727 };
728
655ff266
LD		 729 spi0 {
730 pinctrl_spi0: spi0-0 {
731 atmel,pins =
c9d0f317
JCPV		 732 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
733 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
734 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 735 };
736 };
737
738 spi1 {
739 pinctrl_spi1: spi1-0 {
740 atmel,pins =
c9d0f317
JCPV		 741 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
742 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
743 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 744 };
745 };
746
747 ssc0 {
748 pinctrl_ssc0_tx: ssc0_tx {
749 atmel,pins =
c9d0f317
JCPV		 750 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
751 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
752 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 753 };
754
755 pinctrl_ssc0_rx: ssc0_rx {
756 atmel,pins =
c9d0f317
JCPV		 757 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
758 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
759 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 760 };
761 };
762
763 ssc1 {
764 pinctrl_ssc1_tx: ssc1_tx {
765 atmel,pins =
c9d0f317
JCPV		 766 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
767 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
768 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 769 };
770
771 pinctrl_ssc1_rx: ssc1_rx {
772 atmel,pins =
c9d0f317
JCPV		 773 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
774 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
775 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 776 };
777 };
778
f1ea096c
NF		 779 uart0 {
780 pinctrl_uart0: uart0-0 {
781 atmel,pins =
782 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */
783 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */
784 };
785 };
786
3c309ab8
NF		 787 uart1 {
788 pinctrl_uart1: uart1-0 {
789 atmel,pins =
790 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */
791 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */
792 };
793 };
794
655ff266
LD		 795 usart0 {
796 pinctrl_usart0: usart0-0 {
797 atmel,pins =
c9d0f317
JCPV		 798 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
799 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 800 };
801
802 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
803 atmel,pins =
c9d0f317
JCPV		 804 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
805 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 806 };
807 };
808
809 usart1 {
810 pinctrl_usart1: usart1-0 {
811 atmel,pins =
c9d0f317
JCPV		 812 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
813 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 814 };
815
816 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
817 atmel,pins =
c9d0f317
JCPV		 818 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
819 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 820 };
821 };
822
823 usart2 {
824 pinctrl_usart2: usart2-0 {
825 atmel,pins =
c9d0f317
JCPV		 826 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
827 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 828 };
829
830 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
831 atmel,pins =
c9d0f317
JCPV		 832 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
833 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 834 };
835 };
836
837 usart3 {
838 pinctrl_usart3: usart3-0 {
839 atmel,pins =
c9d0f317
JCPV		 840 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
841 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 842 };
843
844 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
845 atmel,pins =
c9d0f317
JCPV		 846 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
847 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 848 };
849 };
c9d0f317
JCPV		 850
851
852 pioA: gpio@fffff200 {
853 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
854 reg = <0xfffff200 0x100>;
5e8b3bc3 855 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 856 #gpio-cells = <2>;
857 gpio-controller;
858 interrupt-controller;
859 #interrupt-cells = <2>;
d2e8190b 860 clocks = <&pioA_clk>;
c9d0f317
JCPV		 861 };
862
863 pioB: gpio@fffff400 {
864 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
865 reg = <0xfffff400 0x100>;
5e8b3bc3 866 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 867 #gpio-cells = <2>;
868 gpio-controller;
869 interrupt-controller;
870 #interrupt-cells = <2>;
d2e8190b 871 clocks = <&pioB_clk>;
c9d0f317
JCPV		 872 };
873
874 pioC: gpio@fffff600 {
875 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
876 reg = <0xfffff600 0x100>;
5e8b3bc3 877 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 878 #gpio-cells = <2>;
879 gpio-controller;
880 interrupt-controller;
881 #interrupt-cells = <2>;
d2e8190b 882 clocks = <&pioC_clk>;
c9d0f317
JCPV		 883 };
884
885 pioD: gpio@fffff800 {
886 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
887 reg = <0xfffff800 0x100>;
5e8b3bc3 888 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 889 #gpio-cells = <2>;
890 gpio-controller;
891 interrupt-controller;
892 #interrupt-cells = <2>;
d2e8190b 893 clocks = <&pioD_clk>;
c9d0f317
JCPV		 894 };
895
896 pioE: gpio@fffffa00 {
897 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
898 reg = <0xfffffa00 0x100>;
5e8b3bc3 899 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 900 #gpio-cells = <2>;
901 gpio-controller;
902 interrupt-controller;
903 #interrupt-cells = <2>;
d2e8190b 904 clocks = <&pioE_clk>;
c9d0f317 905 };
655ff266
LD		 906 };
907
908 pmc: pmc@fffffc00 {
d2e8190b 909 compatible = "atmel,sama5d3-pmc";
655ff266 910 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 911 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
912 interrupt-controller;
913 #address-cells = <1>;
914 #size-cells = <0>;
915 #interrupt-cells = <1>;
916
4753219d
BB		 917 main_rc_osc: main_rc_osc {
918 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
d2e8190b 919 #clock-cells = <0>;
4753219d
BB		 920 interrupt-parent = <&pmc>;
921 interrupts = <AT91_PMC_MOSCRCS>;
922 clock-frequency = <12000000>;
923 clock-accuracy = <50000000>;
d2e8190b
BB		 924 };
925
4753219d
BB		 926 main_osc: main_osc {
927 compatible = "atmel,at91rm9200-clk-main-osc";
d2e8190b
BB		 928 #clock-cells = <0>;
929 interrupt-parent = <&pmc>;
930 interrupts = <AT91_PMC_MOSCS>;
4753219d
BB		 931 clocks = <&main_xtal>;
932 };
933
934 main: mainck {
935 compatible = "atmel,at91sam9x5-clk-main";
936 #clock-cells = <0>;
937 interrupt-parent = <&pmc>;
938 interrupts = <AT91_PMC_MOSCSELS>;
939 clocks = <&main_rc_osc &main_osc>;
d2e8190b
BB		 940 };
941
942 plla: pllack {
943 compatible = "atmel,sama5d3-clk-pll";
944 #clock-cells = <0>;
945 interrupt-parent = <&pmc>;
946 interrupts = <AT91_PMC_LOCKA>;
947 clocks = <&main>;
948 reg = <0>;
949 atmel,clk-input-range = <8000000 50000000>;
950 #atmel,pll-clk-output-range-cells = <4>;
951 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
952 };
953
954 plladiv: plladivck {
955 compatible = "atmel,at91sam9x5-clk-plldiv";
956 #clock-cells = <0>;
957 clocks = <&plla>;
958 };
959
960 utmi: utmick {
961 compatible = "atmel,at91sam9x5-clk-utmi";
962 #clock-cells = <0>;
963 interrupt-parent = <&pmc>;
964 interrupts = <AT91_PMC_LOCKU>;
965 clocks = <&main>;
966 };
967
968 mck: masterck {
969 compatible = "atmel,at91sam9x5-clk-master";
970 #clock-cells = <0>;
971 interrupt-parent = <&pmc>;
972 interrupts = <AT91_PMC_MCKRDY>;
973 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
974 atmel,clk-output-range = <0 166000000>;
975 atmel,clk-divisors = <1 2 4 3>;
976 };
977
978 usb: usbck {
979 compatible = "atmel,at91sam9x5-clk-usb";
980 #clock-cells = <0>;
981 clocks = <&plladiv>, <&utmi>;
982 };
983
984 prog: progck {
985 compatible = "atmel,at91sam9x5-clk-programmable";
986 #address-cells = <1>;
987 #size-cells = <0>;
988 interrupt-parent = <&pmc>;
989 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
990
991 prog0: prog0 {
992 #clock-cells = <0>;
993 reg = <0>;
994 interrupts = <AT91_PMC_PCKRDY(0)>;
995 };
996
997 prog1: prog1 {
998 #clock-cells = <0>;
999 reg = <1>;
1000 interrupts = <AT91_PMC_PCKRDY(1)>;
1001 };
1002
1003 prog2: prog2 {
1004 #clock-cells = <0>;
1005 reg = <2>;
1006 interrupts = <AT91_PMC_PCKRDY(2)>;
1007 };
1008 };
1009
1010 smd: smdclk {
1011 compatible = "atmel,at91sam9x5-clk-smd";
1012 #clock-cells = <0>;
1013 clocks = <&plladiv>, <&utmi>;
1014 };
1015
1016 systemck {
1017 compatible = "atmel,at91rm9200-clk-system";
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020
1021 ddrck: ddrck {
1022 #clock-cells = <0>;
1023 reg = <2>;
1024 clocks = <&mck>;
1025 };
1026
1027 smdck: smdck {
1028 #clock-cells = <0>;
1029 reg = <4>;
1030 clocks = <&smd>;
1031 };
1032
1033 uhpck: uhpck {
1034 #clock-cells = <0>;
1035 reg = <6>;
1036 clocks = <&usb>;
1037 };
1038
1039 udpck: udpck {
1040 #clock-cells = <0>;
1041 reg = <7>;
1042 clocks = <&usb>;
1043 };
1044
1045 pck0: pck0 {
1046 #clock-cells = <0>;
1047 reg = <8>;
1048 clocks = <&prog0>;
1049 };
1050
1051 pck1: pck1 {
1052 #clock-cells = <0>;
1053 reg = <9>;
1054 clocks = <&prog1>;
1055 };
1056
1057 pck2: pck2 {
1058 #clock-cells = <0>;
1059 reg = <10>;
1060 clocks = <&prog2>;
1061 };
1062 };
1063
1064 periphck {
1065 compatible = "atmel,at91sam9x5-clk-peripheral";
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 clocks = <&mck>;
1069
1070 dbgu_clk: dbgu_clk {
1071 #clock-cells = <0>;
1072 reg = <2>;
1073 };
1074
8a85ba20
AB		 1075 hsmc_clk: hsmc_clk {
1076 #clock-cells = <0>;
1077 reg = <5>;
1078 };
1079
d2e8190b
BB		 1080 pioA_clk: pioA_clk {
1081 #clock-cells = <0>;
1082 reg = <6>;
1083 };
1084
1085 pioB_clk: pioB_clk {
1086 #clock-cells = <0>;
1087 reg = <7>;
1088 };
1089
1090 pioC_clk: pioC_clk {
1091 #clock-cells = <0>;
1092 reg = <8>;
1093 };
1094
1095 pioD_clk: pioD_clk {
1096 #clock-cells = <0>;
1097 reg = <9>;
1098 };
1099
1100 pioE_clk: pioE_clk {
1101 #clock-cells = <0>;
1102 reg = <10>;
1103 };
1104
1105 usart0_clk: usart0_clk {
1106 #clock-cells = <0>;
1107 reg = <12>;
1108 atmel,clk-output-range = <0 66000000>;
1109 };
1110
1111 usart1_clk: usart1_clk {
1112 #clock-cells = <0>;
1113 reg = <13>;
1114 atmel,clk-output-range = <0 66000000>;
1115 };
1116
1117 usart2_clk: usart2_clk {
1118 #clock-cells = <0>;
1119 reg = <14>;
1120 atmel,clk-output-range = <0 66000000>;
1121 };
1122
1123 usart3_clk: usart3_clk {
1124 #clock-cells = <0>;
1125 reg = <15>;
1126 atmel,clk-output-range = <0 66000000>;
1127 };
1128
f1ea096c
NF		 1129 uart0_clk: uart0_clk {
1130 #clock-cells = <0>;
1131 reg = <16>;
1132 atmel,clk-output-range = <0 66000000>;
1133 };
1134
d2e8190b
BB		 1135 twi0_clk: twi0_clk {
1136 reg = <18>;
1137 #clock-cells = <0>;
1138 atmel,clk-output-range = <0 16625000>;
1139 };
1140
1141 twi1_clk: twi1_clk {
1142 #clock-cells = <0>;
1143 reg = <19>;
1144 atmel,clk-output-range = <0 16625000>;
1145 };
1146
1147 twi2_clk: twi2_clk {
1148 #clock-cells = <0>;
1149 reg = <20>;
1150 atmel,clk-output-range = <0 16625000>;
1151 };
1152
1153 mci0_clk: mci0_clk {
1154 #clock-cells = <0>;
1155 reg = <21>;
1156 };
1157
1158 mci1_clk: mci1_clk {
1159 #clock-cells = <0>;
1160 reg = <22>;
1161 };
1162
1163 spi0_clk: spi0_clk {
1164 #clock-cells = <0>;
1165 reg = <24>;
1166 atmel,clk-output-range = <0 133000000>;
1167 };
1168
1169 spi1_clk: spi1_clk {
1170 #clock-cells = <0>;
1171 reg = <25>;
1172 atmel,clk-output-range = <0 133000000>;
1173 };
1174
1175 tcb0_clk: tcb0_clk {
1176 #clock-cells = <0>;
1177 reg = <26>;
1178 atmel,clk-output-range = <0 133000000>;
1179 };
1180
1181 pwm_clk: pwm_clk {
1182 #clock-cells = <0>;
1183 reg = <28>;
1184 };
1185
1186 adc_clk: adc_clk {
1187 #clock-cells = <0>;
1188 reg = <29>;
1189 atmel,clk-output-range = <0 66000000>;
1190 };
1191
1192 dma0_clk: dma0_clk {
1193 #clock-cells = <0>;
1194 reg = <30>;
1195 };
1196
1197 dma1_clk: dma1_clk {
1198 #clock-cells = <0>;
1199 reg = <31>;
1200 };
1201
1202 uhphs_clk: uhphs_clk {
1203 #clock-cells = <0>;
1204 reg = <32>;
1205 };
1206
1207 udphs_clk: udphs_clk {
1208 #clock-cells = <0>;
1209 reg = <33>;
1210 };
1211
1212 isi_clk: isi_clk {
1213 #clock-cells = <0>;
1214 reg = <37>;
1215 };
1216
1217 ssc0_clk: ssc0_clk {
1218 #clock-cells = <0>;
1219 reg = <38>;
1220 atmel,clk-output-range = <0 66000000>;
1221 };
1222
1223 ssc1_clk: ssc1_clk {
1224 #clock-cells = <0>;
1225 reg = <39>;
1226 atmel,clk-output-range = <0 66000000>;
1227 };
1228
1229 sha_clk: sha_clk {
1230 #clock-cells = <0>;
1231 reg = <42>;
1232 };
1233
1234 aes_clk: aes_clk {
1235 #clock-cells = <0>;
1236 reg = <43>;
1237 };
1238
1239 tdes_clk: tdes_clk {
1240 #clock-cells = <0>;
1241 reg = <44>;
1242 };
1243
1244 trng_clk: trng_clk {
1245 #clock-cells = <0>;
1246 reg = <45>;
1247 };
1248
1249 fuse_clk: fuse_clk {
1250 #clock-cells = <0>;
1251 reg = <48>;
1252 };
063de897
AB		 1253
1254 mpddr_clk: mpddr_clk {
1255 #clock-cells = <0>;
1256 reg = <49>;
1257 };
d2e8190b 1258 };
655ff266
LD		 1259 };
1260
1261 rstc@fffffe00 {
1262 compatible = "atmel,at91sam9g45-rstc";
1263 reg = <0xfffffe00 0x10>;
1264 };
1265
16aa7f1f
MR		 1266 shutdown-controller@fffffe10 {
1267 compatible = "atmel,at91sam9x5-shdwc";
1268 reg = <0xfffffe10 0x10>;
1269 };
1270
655ff266
LD		 1271 pit: timer@fffffe30 {
1272 compatible = "atmel,at91sam9260-pit";
1273 reg = <0xfffffe30 0xf>;
5e8b3bc3 1274 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1275 clocks = <&mck>;
655ff266
LD		 1276 };
1277
1278 watchdog@fffffe40 {
1279 compatible = "atmel,at91sam9260-wdt";
1280 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1281 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1282 atmel,watchdog-type = "hardware";
1283 atmel,reset-type = "all";
1284 atmel,dbg-halt;
655ff266
LD		 1285 status = "disabled";
1286 };
1287
4753219d
BB		 1288 sckc@fffffe50 {
1289 compatible = "atmel,at91sam9x5-sckc";
1290 reg = <0xfffffe50 0x4>;
1291
1292 slow_rc_osc: slow_rc_osc {
1293 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1294 #clock-cells = <0>;
1295 clock-frequency = <32768>;
1296 clock-accuracy = <50000000>;
1297 atmel,startup-time-usec = <75>;
1298 };
1299
1300 slow_osc: slow_osc {
1301 compatible = "atmel,at91sam9x5-clk-slow-osc";
1302 #clock-cells = <0>;
1303 clocks = <&slow_xtal>;
1304 atmel,startup-time-usec = <1200000>;
1305 };
1306
1307 clk32k: slowck {
1308 compatible = "atmel,at91sam9x5-clk-slow";
1309 #clock-cells = <0>;
1310 clocks = <&slow_rc_osc &slow_osc>;
1311 };
1312 };
1313
655ff266
LD		 1314 rtc@fffffeb0 {
1315 compatible = "atmel,at91rm9200-rtc";
1316 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1317 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1318 };
1319 };
1320
1321 usb0: gadget@00500000 {
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1324 compatible = "atmel,at91sam9rl-udc";
1325 reg = <0x00500000 0x100000
1326 0xf8030000 0x4000>;
5e8b3bc3 1327 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1328 clocks = <&udphs_clk>, <&utmi>;
1329 clock-names = "pclk", "hclk";
655ff266
LD		 1330 status = "disabled";
1331
1332 ep0 {
1333 reg = <0>;
1334 atmel,fifo-size = <64>;
1335 atmel,nb-banks = <1>;
1336 };
1337
1338 ep1 {
1339 reg = <1>;
1340 atmel,fifo-size = <1024>;
1341 atmel,nb-banks = <3>;
1342 atmel,can-dma;
1343 atmel,can-isoc;
1344 };
1345
1346 ep2 {
1347 reg = <2>;
1348 atmel,fifo-size = <1024>;
1349 atmel,nb-banks = <3>;
1350 atmel,can-dma;
1351 atmel,can-isoc;
1352 };
1353
1354 ep3 {
1355 reg = <3>;
1356 atmel,fifo-size = <1024>;
1357 atmel,nb-banks = <2>;
1358 atmel,can-dma;
1359 };
1360
1361 ep4 {
1362 reg = <4>;
1363 atmel,fifo-size = <1024>;
1364 atmel,nb-banks = <2>;
1365 atmel,can-dma;
1366 };
1367
1368 ep5 {
1369 reg = <5>;
1370 atmel,fifo-size = <1024>;
1371 atmel,nb-banks = <2>;
1372 atmel,can-dma;
1373 };
1374
1375 ep6 {
1376 reg = <6>;
1377 atmel,fifo-size = <1024>;
1378 atmel,nb-banks = <2>;
1379 atmel,can-dma;
1380 };
1381
1382 ep7 {
1383 reg = <7>;
1384 atmel,fifo-size = <1024>;
1385 atmel,nb-banks = <2>;
1386 atmel,can-dma;
1387 };
1388
1389 ep8 {
1390 reg = <8>;
1391 atmel,fifo-size = <1024>;
1392 atmel,nb-banks = <2>;
1393 };
1394
1395 ep9 {
1396 reg = <9>;
1397 atmel,fifo-size = <1024>;
1398 atmel,nb-banks = <2>;
1399 };
1400
1401 ep10 {
1402 reg = <10>;
1403 atmel,fifo-size = <1024>;
1404 atmel,nb-banks = <2>;
1405 };
1406
1407 ep11 {
1408 reg = <11>;
1409 atmel,fifo-size = <1024>;
1410 atmel,nb-banks = <2>;
1411 };
1412
1413 ep12 {
1414 reg = <12>;
1415 atmel,fifo-size = <1024>;
1416 atmel,nb-banks = <2>;
1417 };
1418
1419 ep13 {
1420 reg = <13>;
1421 atmel,fifo-size = <1024>;
1422 atmel,nb-banks = <2>;
1423 };
1424
1425 ep14 {
1426 reg = <14>;
1427 atmel,fifo-size = <1024>;
1428 atmel,nb-banks = <2>;
1429 };
1430
1431 ep15 {
1432 reg = <15>;
1433 atmel,fifo-size = <1024>;
1434 atmel,nb-banks = <2>;
1435 };
1436 };
1437
1438 usb1: ohci@00600000 {
1439 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1440 reg = <0x00600000 0x100000>;
5e8b3bc3 1441 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
f8073708
BB		 1442 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1443 clock-names = "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1444 status = "disabled";
1445 };
1446
1447 usb2: ehci@00700000 {
1448 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1449 reg = <0x00700000 0x100000>;
5e8b3bc3 1450 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
855868a5
BB		 1451 clocks = <&utmi>, <&uhphs_clk>;
1452 clock-names = "usb_clk", "ehci_clk";
655ff266
LD		 1453 status = "disabled";
1454 };
1455
1456 nand0: nand@60000000 {
1457 compatible = "atmel,at91rm9200-nand";
1458 #address-cells = <1>;
1459 #size-cells = <1>;
8ae599ef 1460 ranges;
655ff266
LD		 1461 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1462 0xffffc070 0x00000490 /* SMC PMECC regs */
1463 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1464 0x00110000 0x00018000 /* ROM code */
655ff266 1465 >;
5e8b3bc3 1466 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1467 atmel,nand-addr-offset = <21>;
1468 atmel,nand-cmd-offset = <22>;
e8b2da6e 1469 atmel,nand-has-dma;
655ff266
LD		 1470 pinctrl-names = "default";
1471 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1472 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1473 status = "disabled";
8ae599ef
JW		 1474
1475 nfc@70000000 {
1476 compatible = "atmel,sama5d3-nfc";
1477 #address-cells = <1>;
1478 #size-cells = <1>;
1479 reg = <
55d6cbaa 1480 0x70000000 0x08000000 /* NFC Command Registers */
8ae599ef
JW		 1481 0xffffc000 0x00000070 /* NFC HSMC regs */
1482 0x00200000 0x00100000 /* NFC SRAM banks */
1483 >;
8a85ba20 1484 clocks = <&hsmc_clk>;
8ae599ef 1485 };
655ff266
LD		 1486 };
1487 };
1488};
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