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ARM: at91: sam9263ek: add dt lcd support
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
d2e8190b 16#include <dt-bindings/clk/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
40 };
41 cpus {
8b2efa89
AB		 42 #address-cells = <1>;
43 #size-cells = <0>;
655ff266 44 cpu@0 {
e757a6ee 45 device_type = "cpu";
655ff266 46 compatible = "arm,cortex-a5";
e757a6ee 47 reg = <0x0>;
655ff266
LD		 48 };
49 };
50
d9da9778
AB		 51 pmu {
52 compatible = "arm,cortex-a5-pmu";
53 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
54 };
55
655ff266
LD		 56 memory {
57 reg = <0x20000000 0x8000000>;
58 };
59
d2e8190b
BB		 60 clocks {
61 adc_op_clk: adc_op_clk{
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <20000000>;
65 };
66 };
67
655ff266
LD		 68 ahb {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges;
73
74 apb {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79
80 mmc0: mmc@f0000000 {
81 compatible = "atmel,hsmci";
82 reg = <0xf0000000 0x600>;
5e8b3bc3 83 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 84 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 85 dma-names = "rxtx";
655ff266
LD		 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
88 status = "disabled";
89 #address-cells = <1>;
90 #size-cells = <0>;
d2e8190b
BB		 91 clocks = <&mci0_clk>;
92 clock-names = "mci_clk";
655ff266
LD		 93 };
94
95 spi0: spi@f0004000 {
96 #address-cells = <1>;
97 #size-cells = <0>;
b7ef678e 98 compatible = "atmel,at91rm9200-spi";
655ff266 99 reg = <0xf0004000 0x100>;
5e8b3bc3 100 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 101 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
102 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
103 dma-names = "tx", "rx";
655ff266
LD		 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 106 clocks = <&spi0_clk>;
107 clock-names = "spi_clk";
655ff266
LD		 108 status = "disabled";
109 };
110
111 ssc0: ssc@f0008000 {
112 compatible = "atmel,at91sam9g45-ssc";
113 reg = <0xf0008000 0x4000>;
5e8b3bc3 114 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 117 clocks = <&ssc0_clk>;
118 clock-names = "pclk";
655ff266
LD		 119 status = "disabled";
120 };
121
655ff266
LD		 122 tcb0: timer@f0010000 {
123 compatible = "atmel,at91sam9x5-tcb";
124 reg = <0xf0010000 0x100>;
5e8b3bc3 125 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 126 clocks = <&tcb0_clk>;
127 clock-names = "t0_clk";
655ff266
LD		 128 };
129
130 i2c0: i2c@f0014000 {
131 compatible = "atmel,at91sam9x5-i2c";
132 reg = <0xf0014000 0x4000>;
5e8b3bc3 133 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 134 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
135 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 136 dma-names = "tx", "rx";
655ff266
LD		 137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c0>;
139 #address-cells = <1>;
140 #size-cells = <0>;
d2e8190b 141 clocks = <&twi0_clk>;
655ff266
LD		 142 status = "disabled";
143 };
144
145 i2c1: i2c@f0018000 {
146 compatible = "atmel,at91sam9x5-i2c";
147 reg = <0xf0018000 0x4000>;
5e8b3bc3 148 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 149 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
150 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 151 dma-names = "tx", "rx";
655ff266
LD		 152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c1>;
154 #address-cells = <1>;
155 #size-cells = <0>;
d2e8190b 156 clocks = <&twi1_clk>;
655ff266
LD		 157 status = "disabled";
158 };
159
160 usart0: serial@f001c000 {
161 compatible = "atmel,at91sam9260-usart";
162 reg = <0xf001c000 0x100>;
5e8b3bc3 163 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 166 clocks = <&usart0_clk>;
167 clock-names = "usart";
655ff266
LD		 168 status = "disabled";
169 };
170
171 usart1: serial@f0020000 {
172 compatible = "atmel,at91sam9260-usart";
173 reg = <0xf0020000 0x100>;
5e8b3bc3 174 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 177 clocks = <&usart1_clk>;
178 clock-names = "usart";
655ff266
LD		 179 status = "disabled";
180 };
181
655ff266
LD		 182 isi: isi@f0034000 {
183 compatible = "atmel,at91sam9g45-isi";
184 reg = <0xf0034000 0x4000>;
5e8b3bc3 185 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 186 status = "disabled";
187 };
188
189 mmc1: mmc@f8000000 {
190 compatible = "atmel,hsmci";
191 reg = <0xf8000000 0x600>;
5e8b3bc3 192 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 193 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 194 dma-names = "rxtx";
655ff266
LD		 195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
197 status = "disabled";
198 #address-cells = <1>;
199 #size-cells = <0>;
d2e8190b
BB		 200 clocks = <&mci1_clk>;
201 clock-names = "mci_clk";
655ff266
LD		 202 };
203
655ff266
LD		 204 spi1: spi@f8008000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
b7ef678e 207 compatible = "atmel,at91rm9200-spi";
655ff266 208 reg = <0xf8008000 0x100>;
5e8b3bc3 209 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 210 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
211 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
212 dma-names = "tx", "rx";
655ff266
LD		 213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 215 clocks = <&spi1_clk>;
216 clock-names = "spi_clk";
655ff266
LD		 217 status = "disabled";
218 };
219
220 ssc1: ssc@f800c000 {
221 compatible = "atmel,at91sam9g45-ssc";
222 reg = <0xf800c000 0x4000>;
5e8b3bc3 223 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 226 clocks = <&ssc1_clk>;
227 clock-names = "pclk";
655ff266
LD		 228 status = "disabled";
229 };
230
655ff266
LD		 231 adc0: adc@f8018000 {
232 compatible = "atmel,at91sam9260-adc";
233 reg = <0xf8018000 0x100>;
5e8b3bc3 234 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 235 pinctrl-names = "default";
236 pinctrl-0 = <
237 &pinctrl_adc0_adtrg
238 &pinctrl_adc0_ad0
239 &pinctrl_adc0_ad1
240 &pinctrl_adc0_ad2
241 &pinctrl_adc0_ad3
242 &pinctrl_adc0_ad4
243 &pinctrl_adc0_ad5
244 &pinctrl_adc0_ad6
245 &pinctrl_adc0_ad7
246 &pinctrl_adc0_ad8
247 &pinctrl_adc0_ad9
248 &pinctrl_adc0_ad10
249 &pinctrl_adc0_ad11
250 >;
d2e8190b
BB		 251 clocks = <&adc_clk>,
252 <&adc_op_clk>;
253 clock-names = "adc_clk", "adc_op_clk";
655ff266
LD		 254 atmel,adc-channel-base = <0x50>;
255 atmel,adc-channels-used = <0xfff>;
256 atmel,adc-drdy-mask = <0x1000000>;
257 atmel,adc-num-channels = <12>;
258 atmel,adc-startup-time = <40>;
259 atmel,adc-status-register = <0x30>;
260 atmel,adc-trigger-register = <0xc0>;
261 atmel,adc-use-external;
262 atmel,adc-vref = <3000>;
263 atmel,adc-res = <10 12>;
264 atmel,adc-res-names = "lowres", "highres";
265 status = "disabled";
266
267 trigger@0 {
268 trigger-name = "external-rising";
269 trigger-value = <0x1>;
270 trigger-external;
271 };
272 trigger@1 {
273 trigger-name = "external-falling";
274 trigger-value = <0x2>;
275 trigger-external;
276 };
277 trigger@2 {
278 trigger-name = "external-any";
279 trigger-value = <0x3>;
280 trigger-external;
281 };
282 trigger@3 {
283 trigger-name = "continuous";
284 trigger-value = <0x6>;
285 };
286 };
287
288 tsadcc: tsadcc@f8018000 {
289 compatible = "atmel,at91sam9x5-tsadcc";
290 reg = <0xf8018000 0x4000>;
5e8b3bc3 291 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 292 atmel,tsadcc_clock = <300000>;
293 atmel,filtering_average = <0x03>;
294 atmel,pendet_debounce = <0x08>;
295 atmel,pendet_sensitivity = <0x02>;
296 atmel,ts_sample_hold_time = <0x0a>;
297 status = "disabled";
298 };
299
300 i2c2: i2c@f801c000 {
301 compatible = "atmel,at91sam9x5-i2c";
302 reg = <0xf801c000 0x4000>;
5e8b3bc3 303 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 304 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
305 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 306 dma-names = "tx", "rx";
655ff266
LD		 307 #address-cells = <1>;
308 #size-cells = <0>;
d2e8190b 309 clocks = <&twi2_clk>;
655ff266
LD		 310 status = "disabled";
311 };
312
313 usart2: serial@f8020000 {
314 compatible = "atmel,at91sam9260-usart";
315 reg = <0xf8020000 0x100>;
5e8b3bc3 316 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 319 clocks = <&usart2_clk>;
320 clock-names = "usart";
655ff266
LD		 321 status = "disabled";
322 };
323
324 usart3: serial@f8024000 {
325 compatible = "atmel,at91sam9260-usart";
326 reg = <0xf8024000 0x100>;
5e8b3bc3 327 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 330 clocks = <&usart3_clk>;
331 clock-names = "usart";
655ff266
LD		 332 status = "disabled";
333 };
334
655ff266
LD		 335 sha@f8034000 {
336 compatible = "atmel,sam9g46-sha";
337 reg = <0xf8034000 0x100>;
5e8b3bc3 338 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
655ff266
LD		 339 };
340
341 aes@f8038000 {
342 compatible = "atmel,sam9g46-aes";
343 reg = <0xf8038000 0x100>;
344 interrupts = <43 4 0>;
345 };
346
347 tdes@f803c000 {
348 compatible = "atmel,sam9g46-tdes";
349 reg = <0xf803c000 0x100>;
5e8b3bc3 350 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
655ff266
LD		 351 };
352
353 dma0: dma-controller@ffffe600 {
354 compatible = "atmel,at91sam9g45-dma";
355 reg = <0xffffe600 0x200>;
5e8b3bc3 356 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 357 #dma-cells = <2>;
d2e8190b
BB		 358 clocks = <&dma0_clk>;
359 clock-names = "dma_clk";
655ff266
LD		 360 };
361
362 dma1: dma-controller@ffffe800 {
363 compatible = "atmel,at91sam9g45-dma";
364 reg = <0xffffe800 0x200>;
5e8b3bc3 365 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 366 #dma-cells = <2>;
d2e8190b
BB		 367 clocks = <&dma1_clk>;
368 clock-names = "dma_clk";
655ff266
LD		 369 };
370
371 ramc0: ramc@ffffea00 {
372 compatible = "atmel,at91sam9g45-ddramc";
373 reg = <0xffffea00 0x200>;
374 };
375
376 dbgu: serial@ffffee00 {
377 compatible = "atmel,at91sam9260-usart";
378 reg = <0xffffee00 0x200>;
5e8b3bc3 379 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 382 clocks = <&dbgu_clk>;
383 clock-names = "usart";
655ff266
LD		 384 status = "disabled";
385 };
386
387 aic: interrupt-controller@fffff000 {
388 #interrupt-cells = <3>;
389 compatible = "atmel,sama5d3-aic";
390 interrupt-controller;
391 reg = <0xfffff000 0x200>;
392 atmel,external-irqs = <47>;
393 };
394
395 pinctrl@fffff200 {
396 #address-cells = <1>;
397 #size-cells = <1>;
398 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
399 ranges = <0xfffff200 0xfffff200 0xa00>;
400 atmel,mux-mask = <
401 /* A B C */
402 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
403 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
404 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
405 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
406 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
407 >;
408
409 /* shared pinctrl settings */
410 adc0 {
411 pinctrl_adc0_adtrg: adc0_adtrg {
412 atmel,pins =
c9d0f317 413 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 414 };
415 pinctrl_adc0_ad0: adc0_ad0 {
416 atmel,pins =
c9d0f317 417 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 418 };
419 pinctrl_adc0_ad1: adc0_ad1 {
420 atmel,pins =
c9d0f317 421 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 422 };
423 pinctrl_adc0_ad2: adc0_ad2 {
424 atmel,pins =
c9d0f317 425 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 426 };
427 pinctrl_adc0_ad3: adc0_ad3 {
428 atmel,pins =
c9d0f317 429 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 430 };
431 pinctrl_adc0_ad4: adc0_ad4 {
432 atmel,pins =
c9d0f317 433 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 434 };
435 pinctrl_adc0_ad5: adc0_ad5 {
436 atmel,pins =
c9d0f317 437 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 438 };
439 pinctrl_adc0_ad6: adc0_ad6 {
440 atmel,pins =
c9d0f317 441 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 442 };
443 pinctrl_adc0_ad7: adc0_ad7 {
444 atmel,pins =
c9d0f317 445 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 446 };
447 pinctrl_adc0_ad8: adc0_ad8 {
448 atmel,pins =
c9d0f317 449 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 450 };
451 pinctrl_adc0_ad9: adc0_ad9 {
452 atmel,pins =
c9d0f317 453 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 454 };
455 pinctrl_adc0_ad10: adc0_ad10 {
456 atmel,pins =
c9d0f317 457 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 458 };
459 pinctrl_adc0_ad11: adc0_ad11 {
460 atmel,pins =
c9d0f317 461 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 462 };
463 };
464
655ff266
LD		 465 dbgu {
466 pinctrl_dbgu: dbgu-0 {
467 atmel,pins =
c9d0f317
JCPV		 468 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
469 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 470 };
471 };
472
473 i2c0 {
474 pinctrl_i2c0: i2c0-0 {
475 atmel,pins =
c9d0f317
JCPV		 476 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
477 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 478 };
479 };
480
481 i2c1 {
482 pinctrl_i2c1: i2c1-0 {
483 atmel,pins =
c9d0f317
JCPV		 484 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
485 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 486 };
487 };
488
489 isi {
490 pinctrl_isi: isi-0 {
491 atmel,pins =
c9d0f317
JCPV		 492 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
493 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
494 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
495 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
496 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
497 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
498 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
499 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
500 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
501 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
502 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
503 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
504 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 505 };
506 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
507 atmel,pins =
c9d0f317 508 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 509 };
510 };
511
655ff266
LD		 512 mmc0 {
513 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
514 atmel,pins =
c9d0f317
JCPV		 515 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
516 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
517 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 518 };
519 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
520 atmel,pins =
c9d0f317
JCPV		 521 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
522 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
523 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 524 };
525 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
526 atmel,pins =
c9d0f317
JCPV		 527 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
528 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
529 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
530 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 531 };
532 };
533
534 mmc1 {
535 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
536 atmel,pins =
c9d0f317
JCPV		 537 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
538 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
539 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 540 };
541 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
542 atmel,pins =
c9d0f317
JCPV		 543 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
544 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
545 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 546 };
547 };
548
655ff266
LD		 549 nand0 {
550 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
551 atmel,pins =
c9d0f317
JCPV		 552 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
553 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 554 };
555 };
556
655ff266
LD		 557 spi0 {
558 pinctrl_spi0: spi0-0 {
559 atmel,pins =
c9d0f317
JCPV		 560 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
561 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
562 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 563 };
564 };
565
566 spi1 {
567 pinctrl_spi1: spi1-0 {
568 atmel,pins =
c9d0f317
JCPV		 569 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
570 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
571 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 572 };
573 };
574
575 ssc0 {
576 pinctrl_ssc0_tx: ssc0_tx {
577 atmel,pins =
c9d0f317
JCPV		 578 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
579 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
580 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 581 };
582
583 pinctrl_ssc0_rx: ssc0_rx {
584 atmel,pins =
c9d0f317
JCPV		 585 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
586 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
587 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 588 };
589 };
590
591 ssc1 {
592 pinctrl_ssc1_tx: ssc1_tx {
593 atmel,pins =
c9d0f317
JCPV		 594 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
595 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
596 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 597 };
598
599 pinctrl_ssc1_rx: ssc1_rx {
600 atmel,pins =
c9d0f317
JCPV		 601 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
602 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
603 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 604 };
605 };
606
655ff266
LD		 607 usart0 {
608 pinctrl_usart0: usart0-0 {
609 atmel,pins =
c9d0f317
JCPV		 610 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
611 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 612 };
613
614 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
615 atmel,pins =
c9d0f317
JCPV		 616 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
617 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 618 };
619 };
620
621 usart1 {
622 pinctrl_usart1: usart1-0 {
623 atmel,pins =
c9d0f317
JCPV		 624 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
625 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 626 };
627
628 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
629 atmel,pins =
c9d0f317
JCPV		 630 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
631 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 632 };
633 };
634
635 usart2 {
636 pinctrl_usart2: usart2-0 {
637 atmel,pins =
c9d0f317
JCPV		 638 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
639 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 640 };
641
642 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
643 atmel,pins =
c9d0f317
JCPV		 644 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
645 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 646 };
647 };
648
649 usart3 {
650 pinctrl_usart3: usart3-0 {
651 atmel,pins =
c9d0f317
JCPV		 652 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
653 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 654 };
655
656 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
657 atmel,pins =
c9d0f317
JCPV		 658 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
659 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 660 };
661 };
c9d0f317
JCPV		 662
663
664 pioA: gpio@fffff200 {
665 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
666 reg = <0xfffff200 0x100>;
5e8b3bc3 667 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 668 #gpio-cells = <2>;
669 gpio-controller;
670 interrupt-controller;
671 #interrupt-cells = <2>;
d2e8190b 672 clocks = <&pioA_clk>;
c9d0f317
JCPV		 673 };
674
675 pioB: gpio@fffff400 {
676 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
677 reg = <0xfffff400 0x100>;
5e8b3bc3 678 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 679 #gpio-cells = <2>;
680 gpio-controller;
681 interrupt-controller;
682 #interrupt-cells = <2>;
d2e8190b 683 clocks = <&pioB_clk>;
c9d0f317
JCPV		 684 };
685
686 pioC: gpio@fffff600 {
687 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
688 reg = <0xfffff600 0x100>;
5e8b3bc3 689 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 690 #gpio-cells = <2>;
691 gpio-controller;
692 interrupt-controller;
693 #interrupt-cells = <2>;
d2e8190b 694 clocks = <&pioC_clk>;
c9d0f317
JCPV		 695 };
696
697 pioD: gpio@fffff800 {
698 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
699 reg = <0xfffff800 0x100>;
5e8b3bc3 700 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 701 #gpio-cells = <2>;
702 gpio-controller;
703 interrupt-controller;
704 #interrupt-cells = <2>;
d2e8190b 705 clocks = <&pioD_clk>;
c9d0f317
JCPV		 706 };
707
708 pioE: gpio@fffffa00 {
709 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
710 reg = <0xfffffa00 0x100>;
5e8b3bc3 711 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 712 #gpio-cells = <2>;
713 gpio-controller;
714 interrupt-controller;
715 #interrupt-cells = <2>;
d2e8190b 716 clocks = <&pioE_clk>;
c9d0f317 717 };
655ff266
LD		 718 };
719
720 pmc: pmc@fffffc00 {
d2e8190b 721 compatible = "atmel,sama5d3-pmc";
655ff266 722 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 723 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
724 interrupt-controller;
725 #address-cells = <1>;
726 #size-cells = <0>;
727 #interrupt-cells = <1>;
728
729 clk32k: slck {
730 compatible = "fixed-clock";
731 #clock-cells = <0>;
732 clock-frequency = <32768>;
733 };
734
735 main: mainck {
736 compatible = "atmel,at91rm9200-clk-main";
737 #clock-cells = <0>;
738 interrupt-parent = <&pmc>;
739 interrupts = <AT91_PMC_MOSCS>;
740 clocks = <&clk32k>;
741 };
742
743 plla: pllack {
744 compatible = "atmel,sama5d3-clk-pll";
745 #clock-cells = <0>;
746 interrupt-parent = <&pmc>;
747 interrupts = <AT91_PMC_LOCKA>;
748 clocks = <&main>;
749 reg = <0>;
750 atmel,clk-input-range = <8000000 50000000>;
751 #atmel,pll-clk-output-range-cells = <4>;
752 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
753 };
754
755 plladiv: plladivck {
756 compatible = "atmel,at91sam9x5-clk-plldiv";
757 #clock-cells = <0>;
758 clocks = <&plla>;
759 };
760
761 utmi: utmick {
762 compatible = "atmel,at91sam9x5-clk-utmi";
763 #clock-cells = <0>;
764 interrupt-parent = <&pmc>;
765 interrupts = <AT91_PMC_LOCKU>;
766 clocks = <&main>;
767 };
768
769 mck: masterck {
770 compatible = "atmel,at91sam9x5-clk-master";
771 #clock-cells = <0>;
772 interrupt-parent = <&pmc>;
773 interrupts = <AT91_PMC_MCKRDY>;
774 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
775 atmel,clk-output-range = <0 166000000>;
776 atmel,clk-divisors = <1 2 4 3>;
777 };
778
779 usb: usbck {
780 compatible = "atmel,at91sam9x5-clk-usb";
781 #clock-cells = <0>;
782 clocks = <&plladiv>, <&utmi>;
783 };
784
785 prog: progck {
786 compatible = "atmel,at91sam9x5-clk-programmable";
787 #address-cells = <1>;
788 #size-cells = <0>;
789 interrupt-parent = <&pmc>;
790 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
791
792 prog0: prog0 {
793 #clock-cells = <0>;
794 reg = <0>;
795 interrupts = <AT91_PMC_PCKRDY(0)>;
796 };
797
798 prog1: prog1 {
799 #clock-cells = <0>;
800 reg = <1>;
801 interrupts = <AT91_PMC_PCKRDY(1)>;
802 };
803
804 prog2: prog2 {
805 #clock-cells = <0>;
806 reg = <2>;
807 interrupts = <AT91_PMC_PCKRDY(2)>;
808 };
809 };
810
811 smd: smdclk {
812 compatible = "atmel,at91sam9x5-clk-smd";
813 #clock-cells = <0>;
814 clocks = <&plladiv>, <&utmi>;
815 };
816
817 systemck {
818 compatible = "atmel,at91rm9200-clk-system";
819 #address-cells = <1>;
820 #size-cells = <0>;
821
822 ddrck: ddrck {
823 #clock-cells = <0>;
824 reg = <2>;
825 clocks = <&mck>;
826 };
827
828 smdck: smdck {
829 #clock-cells = <0>;
830 reg = <4>;
831 clocks = <&smd>;
832 };
833
834 uhpck: uhpck {
835 #clock-cells = <0>;
836 reg = <6>;
837 clocks = <&usb>;
838 };
839
840 udpck: udpck {
841 #clock-cells = <0>;
842 reg = <7>;
843 clocks = <&usb>;
844 };
845
846 pck0: pck0 {
847 #clock-cells = <0>;
848 reg = <8>;
849 clocks = <&prog0>;
850 };
851
852 pck1: pck1 {
853 #clock-cells = <0>;
854 reg = <9>;
855 clocks = <&prog1>;
856 };
857
858 pck2: pck2 {
859 #clock-cells = <0>;
860 reg = <10>;
861 clocks = <&prog2>;
862 };
863 };
864
865 periphck {
866 compatible = "atmel,at91sam9x5-clk-peripheral";
867 #address-cells = <1>;
868 #size-cells = <0>;
869 clocks = <&mck>;
870
871 dbgu_clk: dbgu_clk {
872 #clock-cells = <0>;
873 reg = <2>;
874 };
875
876 pioA_clk: pioA_clk {
877 #clock-cells = <0>;
878 reg = <6>;
879 };
880
881 pioB_clk: pioB_clk {
882 #clock-cells = <0>;
883 reg = <7>;
884 };
885
886 pioC_clk: pioC_clk {
887 #clock-cells = <0>;
888 reg = <8>;
889 };
890
891 pioD_clk: pioD_clk {
892 #clock-cells = <0>;
893 reg = <9>;
894 };
895
896 pioE_clk: pioE_clk {
897 #clock-cells = <0>;
898 reg = <10>;
899 };
900
901 usart0_clk: usart0_clk {
902 #clock-cells = <0>;
903 reg = <12>;
904 atmel,clk-output-range = <0 66000000>;
905 };
906
907 usart1_clk: usart1_clk {
908 #clock-cells = <0>;
909 reg = <13>;
910 atmel,clk-output-range = <0 66000000>;
911 };
912
913 usart2_clk: usart2_clk {
914 #clock-cells = <0>;
915 reg = <14>;
916 atmel,clk-output-range = <0 66000000>;
917 };
918
919 usart3_clk: usart3_clk {
920 #clock-cells = <0>;
921 reg = <15>;
922 atmel,clk-output-range = <0 66000000>;
923 };
924
925 twi0_clk: twi0_clk {
926 reg = <18>;
927 #clock-cells = <0>;
928 atmel,clk-output-range = <0 16625000>;
929 };
930
931 twi1_clk: twi1_clk {
932 #clock-cells = <0>;
933 reg = <19>;
934 atmel,clk-output-range = <0 16625000>;
935 };
936
937 twi2_clk: twi2_clk {
938 #clock-cells = <0>;
939 reg = <20>;
940 atmel,clk-output-range = <0 16625000>;
941 };
942
943 mci0_clk: mci0_clk {
944 #clock-cells = <0>;
945 reg = <21>;
946 };
947
948 mci1_clk: mci1_clk {
949 #clock-cells = <0>;
950 reg = <22>;
951 };
952
953 spi0_clk: spi0_clk {
954 #clock-cells = <0>;
955 reg = <24>;
956 atmel,clk-output-range = <0 133000000>;
957 };
958
959 spi1_clk: spi1_clk {
960 #clock-cells = <0>;
961 reg = <25>;
962 atmel,clk-output-range = <0 133000000>;
963 };
964
965 tcb0_clk: tcb0_clk {
966 #clock-cells = <0>;
967 reg = <26>;
968 atmel,clk-output-range = <0 133000000>;
969 };
970
971 pwm_clk: pwm_clk {
972 #clock-cells = <0>;
973 reg = <28>;
974 };
975
976 adc_clk: adc_clk {
977 #clock-cells = <0>;
978 reg = <29>;
979 atmel,clk-output-range = <0 66000000>;
980 };
981
982 dma0_clk: dma0_clk {
983 #clock-cells = <0>;
984 reg = <30>;
985 };
986
987 dma1_clk: dma1_clk {
988 #clock-cells = <0>;
989 reg = <31>;
990 };
991
992 uhphs_clk: uhphs_clk {
993 #clock-cells = <0>;
994 reg = <32>;
995 };
996
997 udphs_clk: udphs_clk {
998 #clock-cells = <0>;
999 reg = <33>;
1000 };
1001
1002 isi_clk: isi_clk {
1003 #clock-cells = <0>;
1004 reg = <37>;
1005 };
1006
1007 ssc0_clk: ssc0_clk {
1008 #clock-cells = <0>;
1009 reg = <38>;
1010 atmel,clk-output-range = <0 66000000>;
1011 };
1012
1013 ssc1_clk: ssc1_clk {
1014 #clock-cells = <0>;
1015 reg = <39>;
1016 atmel,clk-output-range = <0 66000000>;
1017 };
1018
1019 sha_clk: sha_clk {
1020 #clock-cells = <0>;
1021 reg = <42>;
1022 };
1023
1024 aes_clk: aes_clk {
1025 #clock-cells = <0>;
1026 reg = <43>;
1027 };
1028
1029 tdes_clk: tdes_clk {
1030 #clock-cells = <0>;
1031 reg = <44>;
1032 };
1033
1034 trng_clk: trng_clk {
1035 #clock-cells = <0>;
1036 reg = <45>;
1037 };
1038
1039 fuse_clk: fuse_clk {
1040 #clock-cells = <0>;
1041 reg = <48>;
1042 };
1043 };
655ff266
LD		 1044 };
1045
1046 rstc@fffffe00 {
1047 compatible = "atmel,at91sam9g45-rstc";
1048 reg = <0xfffffe00 0x10>;
1049 };
1050
1051 pit: timer@fffffe30 {
1052 compatible = "atmel,at91sam9260-pit";
1053 reg = <0xfffffe30 0xf>;
5e8b3bc3 1054 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1055 clocks = <&mck>;
655ff266
LD		 1056 };
1057
1058 watchdog@fffffe40 {
1059 compatible = "atmel,at91sam9260-wdt";
1060 reg = <0xfffffe40 0x10>;
1061 status = "disabled";
1062 };
1063
1064 rtc@fffffeb0 {
1065 compatible = "atmel,at91rm9200-rtc";
1066 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1067 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1068 };
1069 };
1070
1071 usb0: gadget@00500000 {
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074 compatible = "atmel,at91sam9rl-udc";
1075 reg = <0x00500000 0x100000
1076 0xf8030000 0x4000>;
5e8b3bc3 1077 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1078 clocks = <&udphs_clk>, <&utmi>;
1079 clock-names = "pclk", "hclk";
655ff266
LD		 1080 status = "disabled";
1081
1082 ep0 {
1083 reg = <0>;
1084 atmel,fifo-size = <64>;
1085 atmel,nb-banks = <1>;
1086 };
1087
1088 ep1 {
1089 reg = <1>;
1090 atmel,fifo-size = <1024>;
1091 atmel,nb-banks = <3>;
1092 atmel,can-dma;
1093 atmel,can-isoc;
1094 };
1095
1096 ep2 {
1097 reg = <2>;
1098 atmel,fifo-size = <1024>;
1099 atmel,nb-banks = <3>;
1100 atmel,can-dma;
1101 atmel,can-isoc;
1102 };
1103
1104 ep3 {
1105 reg = <3>;
1106 atmel,fifo-size = <1024>;
1107 atmel,nb-banks = <2>;
1108 atmel,can-dma;
1109 };
1110
1111 ep4 {
1112 reg = <4>;
1113 atmel,fifo-size = <1024>;
1114 atmel,nb-banks = <2>;
1115 atmel,can-dma;
1116 };
1117
1118 ep5 {
1119 reg = <5>;
1120 atmel,fifo-size = <1024>;
1121 atmel,nb-banks = <2>;
1122 atmel,can-dma;
1123 };
1124
1125 ep6 {
1126 reg = <6>;
1127 atmel,fifo-size = <1024>;
1128 atmel,nb-banks = <2>;
1129 atmel,can-dma;
1130 };
1131
1132 ep7 {
1133 reg = <7>;
1134 atmel,fifo-size = <1024>;
1135 atmel,nb-banks = <2>;
1136 atmel,can-dma;
1137 };
1138
1139 ep8 {
1140 reg = <8>;
1141 atmel,fifo-size = <1024>;
1142 atmel,nb-banks = <2>;
1143 };
1144
1145 ep9 {
1146 reg = <9>;
1147 atmel,fifo-size = <1024>;
1148 atmel,nb-banks = <2>;
1149 };
1150
1151 ep10 {
1152 reg = <10>;
1153 atmel,fifo-size = <1024>;
1154 atmel,nb-banks = <2>;
1155 };
1156
1157 ep11 {
1158 reg = <11>;
1159 atmel,fifo-size = <1024>;
1160 atmel,nb-banks = <2>;
1161 };
1162
1163 ep12 {
1164 reg = <12>;
1165 atmel,fifo-size = <1024>;
1166 atmel,nb-banks = <2>;
1167 };
1168
1169 ep13 {
1170 reg = <13>;
1171 atmel,fifo-size = <1024>;
1172 atmel,nb-banks = <2>;
1173 };
1174
1175 ep14 {
1176 reg = <14>;
1177 atmel,fifo-size = <1024>;
1178 atmel,nb-banks = <2>;
1179 };
1180
1181 ep15 {
1182 reg = <15>;
1183 atmel,fifo-size = <1024>;
1184 atmel,nb-banks = <2>;
1185 };
1186 };
1187
1188 usb1: ohci@00600000 {
1189 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1190 reg = <0x00600000 0x100000>;
5e8b3bc3 1191 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1192 clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1193 <&uhpck>;
1194 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1195 status = "disabled";
1196 };
1197
1198 usb2: ehci@00700000 {
1199 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1200 reg = <0x00700000 0x100000>;
5e8b3bc3 1201 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1202 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1203 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1204 status = "disabled";
1205 };
1206
1207 nand0: nand@60000000 {
1208 compatible = "atmel,at91rm9200-nand";
1209 #address-cells = <1>;
1210 #size-cells = <1>;
8ae599ef 1211 ranges;
655ff266
LD		 1212 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1213 0xffffc070 0x00000490 /* SMC PMECC regs */
1214 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1215 0x00110000 0x00018000 /* ROM code */
655ff266 1216 >;
5e8b3bc3 1217 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1218 atmel,nand-addr-offset = <21>;
1219 atmel,nand-cmd-offset = <22>;
1220 pinctrl-names = "default";
1221 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1222 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1223 status = "disabled";
8ae599ef
JW		 1224
1225 nfc@70000000 {
1226 compatible = "atmel,sama5d3-nfc";
1227 #address-cells = <1>;
1228 #size-cells = <1>;
1229 reg = <
1230 0x70000000 0x10000000 /* NFC Command Registers */
1231 0xffffc000 0x00000070 /* NFC HSMC regs */
1232 0x00200000 0x00100000 /* NFC SRAM banks */
1233 >;
1234 };
655ff266
LD		 1235 };
1236 };
1237};
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