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ARM: at91/dt: at91rm9200ek: enable RTC
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
35d35aae 16#include <dt-bindings/clock/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
334394c0
AB		 61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
4753219d 67
334394c0
AB		 68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
4753219d 73
d2e8190b
BB		 74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <20000000>;
78 };
79 };
80
655ff266
LD		 81 ahb {
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges;
86
87 apb {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 mmc0: mmc@f0000000 {
94 compatible = "atmel,hsmci";
95 reg = <0xf0000000 0x600>;
5e8b3bc3 96 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 97 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 98 dma-names = "rxtx";
655ff266
LD		 99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
101 status = "disabled";
102 #address-cells = <1>;
103 #size-cells = <0>;
d2e8190b
BB		 104 clocks = <&mci0_clk>;
105 clock-names = "mci_clk";
655ff266
LD		 106 };
107
108 spi0: spi@f0004000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
b7ef678e 111 compatible = "atmel,at91rm9200-spi";
655ff266 112 reg = <0xf0004000 0x100>;
5e8b3bc3 113 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 114 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
115 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
116 dma-names = "tx", "rx";
655ff266
LD		 117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 119 clocks = <&spi0_clk>;
120 clock-names = "spi_clk";
655ff266
LD		 121 status = "disabled";
122 };
123
124 ssc0: ssc@f0008000 {
125 compatible = "atmel,at91sam9g45-ssc";
126 reg = <0xf0008000 0x4000>;
5e8b3bc3 127 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 128 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
129 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
130 dma-names = "tx", "rx";
655ff266
LD		 131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 133 clocks = <&ssc0_clk>;
134 clock-names = "pclk";
655ff266
LD		 135 status = "disabled";
136 };
137
655ff266
LD		 138 tcb0: timer@f0010000 {
139 compatible = "atmel,at91sam9x5-tcb";
140 reg = <0xf0010000 0x100>;
5e8b3bc3 141 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 142 clocks = <&tcb0_clk>;
143 clock-names = "t0_clk";
655ff266
LD		 144 };
145
146 i2c0: i2c@f0014000 {
147 compatible = "atmel,at91sam9x5-i2c";
148 reg = <0xf0014000 0x4000>;
5e8b3bc3 149 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
151 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 152 dma-names = "tx", "rx";
655ff266
LD		 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c0>;
155 #address-cells = <1>;
156 #size-cells = <0>;
d2e8190b 157 clocks = <&twi0_clk>;
655ff266
LD		 158 status = "disabled";
159 };
160
161 i2c1: i2c@f0018000 {
162 compatible = "atmel,at91sam9x5-i2c";
163 reg = <0xf0018000 0x4000>;
5e8b3bc3 164 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 165 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
166 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 167 dma-names = "tx", "rx";
655ff266
LD		 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 #address-cells = <1>;
171 #size-cells = <0>;
d2e8190b 172 clocks = <&twi1_clk>;
655ff266
LD		 173 status = "disabled";
174 };
175
176 usart0: serial@f001c000 {
177 compatible = "atmel,at91sam9260-usart";
178 reg = <0xf001c000 0x100>;
5e8b3bc3 179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 180 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
181 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
182 dma-names = "tx", "rx";
655ff266
LD		 183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 185 clocks = <&usart0_clk>;
186 clock-names = "usart";
655ff266
LD		 187 status = "disabled";
188 };
189
190 usart1: serial@f0020000 {
191 compatible = "atmel,at91sam9260-usart";
192 reg = <0xf0020000 0x100>;
5e8b3bc3 193 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 194 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
195 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
196 dma-names = "tx", "rx";
655ff266
LD		 197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 199 clocks = <&usart1_clk>;
200 clock-names = "usart";
655ff266
LD		 201 status = "disabled";
202 };
203
f3ab0527
BS		 204 pwm0: pwm@f002c000 {
205 compatible = "atmel,sama5d3-pwm";
206 reg = <0xf002c000 0x300>;
207 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
208 #pwm-cells = <3>;
209 clocks = <&pwm_clk>;
210 status = "disabled";
211 };
655ff266 212
655ff266
LD		 213 isi: isi@f0034000 {
214 compatible = "atmel,at91sam9g45-isi";
215 reg = <0xf0034000 0x4000>;
5e8b3bc3 216 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 217 status = "disabled";
218 };
219
6ced9f4a
AB		 220 sfr: sfr@f0038000 {
221 compatible = "atmel,sama5d3-sfr", "syscon";
222 reg = <0xf0038000 0x60>;
223 };
224
655ff266
LD		 225 mmc1: mmc@f8000000 {
226 compatible = "atmel,hsmci";
227 reg = <0xf8000000 0x600>;
5e8b3bc3 228 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 229 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 230 dma-names = "rxtx";
655ff266
LD		 231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
233 status = "disabled";
234 #address-cells = <1>;
235 #size-cells = <0>;
d2e8190b
BB		 236 clocks = <&mci1_clk>;
237 clock-names = "mci_clk";
655ff266
LD		 238 };
239
655ff266
LD		 240 spi1: spi@f8008000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
b7ef678e 243 compatible = "atmel,at91rm9200-spi";
655ff266 244 reg = <0xf8008000 0x100>;
5e8b3bc3 245 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 246 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
247 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
248 dma-names = "tx", "rx";
655ff266
LD		 249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 251 clocks = <&spi1_clk>;
252 clock-names = "spi_clk";
655ff266
LD		 253 status = "disabled";
254 };
255
256 ssc1: ssc@f800c000 {
257 compatible = "atmel,at91sam9g45-ssc";
258 reg = <0xf800c000 0x4000>;
5e8b3bc3 259 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 260 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
261 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
262 dma-names = "tx", "rx";
655ff266
LD		 263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 265 clocks = <&ssc1_clk>;
266 clock-names = "pclk";
655ff266
LD		 267 status = "disabled";
268 };
269
655ff266 270 adc0: adc@f8018000 {
b3b84dec
AB		 271 #address-cells = <1>;
272 #size-cells = <0>;
9879b96d 273 compatible = "atmel,at91sam9x5-adc";
655ff266 274 reg = <0xf8018000 0x100>;
5e8b3bc3 275 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 276 pinctrl-names = "default";
277 pinctrl-0 = <
278 &pinctrl_adc0_adtrg
279 &pinctrl_adc0_ad0
280 &pinctrl_adc0_ad1
281 &pinctrl_adc0_ad2
282 &pinctrl_adc0_ad3
283 &pinctrl_adc0_ad4
284 &pinctrl_adc0_ad5
285 &pinctrl_adc0_ad6
286 &pinctrl_adc0_ad7
287 &pinctrl_adc0_ad8
288 &pinctrl_adc0_ad9
289 &pinctrl_adc0_ad10
290 &pinctrl_adc0_ad11
291 >;
d2e8190b
BB		 292 clocks = <&adc_clk>,
293 <&adc_op_clk>;
294 clock-names = "adc_clk", "adc_op_clk";
655ff266 295 atmel,adc-channels-used = <0xfff>;
655ff266 296 atmel,adc-startup-time = <40>;
b3b84dec 297 atmel,adc-use-external-triggers;
655ff266
LD		 298 atmel,adc-vref = <3000>;
299 atmel,adc-res = <10 12>;
300 atmel,adc-res-names = "lowres", "highres";
301 status = "disabled";
302
303 trigger@0 {
b3b84dec 304 reg = <0>;
655ff266
LD		 305 trigger-name = "external-rising";
306 trigger-value = <0x1>;
307 trigger-external;
308 };
309 trigger@1 {
b3b84dec 310 reg = <1>;
655ff266
LD		 311 trigger-name = "external-falling";
312 trigger-value = <0x2>;
313 trigger-external;
314 };
315 trigger@2 {
b3b84dec 316 reg = <2>;
655ff266
LD		 317 trigger-name = "external-any";
318 trigger-value = <0x3>;
319 trigger-external;
320 };
321 trigger@3 {
b3b84dec 322 reg = <3>;
655ff266
LD		 323 trigger-name = "continuous";
324 trigger-value = <0x6>;
325 };
326 };
327
655ff266
LD		 328 i2c2: i2c@f801c000 {
329 compatible = "atmel,at91sam9x5-i2c";
330 reg = <0xf801c000 0x4000>;
5e8b3bc3 331 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 332 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
333 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 334 dma-names = "tx", "rx";
557844ec
NF		 335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 337 #address-cells = <1>;
338 #size-cells = <0>;
d2e8190b 339 clocks = <&twi2_clk>;
655ff266
LD		 340 status = "disabled";
341 };
342
343 usart2: serial@f8020000 {
344 compatible = "atmel,at91sam9260-usart";
345 reg = <0xf8020000 0x100>;
5e8b3bc3 346 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 347 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
348 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
349 dma-names = "tx", "rx";
655ff266
LD		 350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 352 clocks = <&usart2_clk>;
353 clock-names = "usart";
655ff266
LD		 354 status = "disabled";
355 };
356
357 usart3: serial@f8024000 {
358 compatible = "atmel,at91sam9260-usart";
359 reg = <0xf8024000 0x100>;
5e8b3bc3 360 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 361 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
362 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
363 dma-names = "tx", "rx";
655ff266
LD		 364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 366 clocks = <&usart3_clk>;
367 clock-names = "usart";
655ff266
LD		 368 status = "disabled";
369 };
370
655ff266 371 sha@f8034000 {
c76f266d 372 compatible = "atmel,at91sam9g46-sha";
655ff266 373 reg = <0xf8034000 0x100>;
5e8b3bc3 374 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 375 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
376 dma-names = "tx";
4df4f446
BB		 377 clocks = <&sha_clk>;
378 clock-names = "sha_clk";
655ff266
LD		 379 };
380
381 aes@f8038000 {
c76f266d 382 compatible = "atmel,at91sam9g46-aes";
655ff266 383 reg = <0xf8038000 0x100>;
07f7d503 384 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 385 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
386 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
387 dma-names = "tx", "rx";
f68cd356
BB		 388 clocks = <&aes_clk>;
389 clock-names = "aes_clk";
655ff266
LD		 390 };
391
392 tdes@f803c000 {
c76f266d 393 compatible = "atmel,at91sam9g46-tdes";
655ff266 394 reg = <0xf803c000 0x100>;
5e8b3bc3 395 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 396 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
397 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
398 dma-names = "tx", "rx";
45e5c2cb
BB		 399 clocks = <&tdes_clk>;
400 clock-names = "tdes_clk";
655ff266
LD		 401 };
402
403 dma0: dma-controller@ffffe600 {
404 compatible = "atmel,at91sam9g45-dma";
405 reg = <0xffffe600 0x200>;
5e8b3bc3 406 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 407 #dma-cells = <2>;
d2e8190b
BB		 408 clocks = <&dma0_clk>;
409 clock-names = "dma_clk";
655ff266
LD		 410 };
411
412 dma1: dma-controller@ffffe800 {
413 compatible = "atmel,at91sam9g45-dma";
414 reg = <0xffffe800 0x200>;
5e8b3bc3 415 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 416 #dma-cells = <2>;
d2e8190b
BB		 417 clocks = <&dma1_clk>;
418 clock-names = "dma_clk";
655ff266
LD		 419 };
420
421 ramc0: ramc@ffffea00 {
063de897 422 compatible = "atmel,sama5d3-ddramc";
655ff266 423 reg = <0xffffea00 0x200>;
063de897
AB		 424 clocks = <&ddrck>, <&mpddr_clk>;
425 clock-names = "ddrck", "mpddr";
655ff266
LD		 426 };
427
428 dbgu: serial@ffffee00 {
429 compatible = "atmel,at91sam9260-usart";
430 reg = <0xffffee00 0x200>;
5e8b3bc3 431 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
d24cd783
LD		 432 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
433 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
434 dma-names = "tx", "rx";
655ff266
LD		 435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 437 clocks = <&dbgu_clk>;
438 clock-names = "usart";
655ff266
LD		 439 status = "disabled";
440 };
441
442 aic: interrupt-controller@fffff000 {
443 #interrupt-cells = <3>;
444 compatible = "atmel,sama5d3-aic";
445 interrupt-controller;
446 reg = <0xfffff000 0x200>;
447 atmel,external-irqs = <47>;
448 };
449
450 pinctrl@fffff200 {
451 #address-cells = <1>;
452 #size-cells = <1>;
e0065cf7 453 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
655ff266
LD		 454 ranges = <0xfffff200 0xfffff200 0xa00>;
455 atmel,mux-mask = <
456 /* A B C */
457 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
458 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
459 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
460 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
461 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
462 >;
463
464 /* shared pinctrl settings */
465 adc0 {
466 pinctrl_adc0_adtrg: adc0_adtrg {
467 atmel,pins =
c9d0f317 468 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 469 };
470 pinctrl_adc0_ad0: adc0_ad0 {
471 atmel,pins =
c9d0f317 472 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 473 };
474 pinctrl_adc0_ad1: adc0_ad1 {
475 atmel,pins =
c9d0f317 476 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 477 };
478 pinctrl_adc0_ad2: adc0_ad2 {
479 atmel,pins =
c9d0f317 480 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 481 };
482 pinctrl_adc0_ad3: adc0_ad3 {
483 atmel,pins =
c9d0f317 484 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 485 };
486 pinctrl_adc0_ad4: adc0_ad4 {
487 atmel,pins =
c9d0f317 488 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 489 };
490 pinctrl_adc0_ad5: adc0_ad5 {
491 atmel,pins =
c9d0f317 492 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 493 };
494 pinctrl_adc0_ad6: adc0_ad6 {
495 atmel,pins =
c9d0f317 496 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 497 };
498 pinctrl_adc0_ad7: adc0_ad7 {
499 atmel,pins =
c9d0f317 500 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 501 };
502 pinctrl_adc0_ad8: adc0_ad8 {
503 atmel,pins =
c9d0f317 504 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 505 };
506 pinctrl_adc0_ad9: adc0_ad9 {
507 atmel,pins =
c9d0f317 508 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 509 };
510 pinctrl_adc0_ad10: adc0_ad10 {
511 atmel,pins =
c9d0f317 512 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 513 };
514 pinctrl_adc0_ad11: adc0_ad11 {
515 atmel,pins =
c9d0f317 516 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 517 };
518 };
519
655ff266
LD		 520 dbgu {
521 pinctrl_dbgu: dbgu-0 {
522 atmel,pins =
c9d0f317
JCPV		 523 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
524 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 525 };
526 };
527
528 i2c0 {
529 pinctrl_i2c0: i2c0-0 {
530 atmel,pins =
c9d0f317
JCPV		 531 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
532 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 533 };
534 };
535
536 i2c1 {
537 pinctrl_i2c1: i2c1-0 {
538 atmel,pins =
c9d0f317
JCPV		 539 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
540 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 541 };
542 };
543
557844ec
NF		 544 i2c2 {
545 pinctrl_i2c2: i2c2-0 {
546 atmel,pins =
547 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
548 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
549 };
550 };
551
655ff266
LD		 552 isi {
553 pinctrl_isi: isi-0 {
554 atmel,pins =
c9d0f317
JCPV		 555 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
556 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
557 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
558 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
559 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
560 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
561 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
562 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
563 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
564 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
565 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
566 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
567 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 568 };
569 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
570 atmel,pins =
c9d0f317 571 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 572 };
573 };
574
655ff266
LD		 575 mmc0 {
576 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
577 atmel,pins =
c9d0f317
JCPV		 578 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
579 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
580 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 581 };
582 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
583 atmel,pins =
c9d0f317
JCPV		 584 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
585 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
586 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 587 };
588 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
589 atmel,pins =
c9d0f317
JCPV		 590 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
591 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
592 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
593 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 594 };
595 };
596
597 mmc1 {
598 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
599 atmel,pins =
c9d0f317
JCPV		 600 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
601 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
602 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 603 };
604 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
605 atmel,pins =
c9d0f317
JCPV		 606 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
607 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
608 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 609 };
610 };
611
655ff266
LD		 612 nand0 {
613 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
614 atmel,pins =
c9d0f317
JCPV		 615 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
616 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 617 };
618 };
619
5eefd5f4
NF		 620 pwm0 {
621 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
622 atmel,pins =
623 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
624 };
625 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
626 atmel,pins =
627 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
628 };
629 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
630 atmel,pins =
631 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
632 };
633 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
634 atmel,pins =
635 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
636 };
637
638 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
639 atmel,pins =
640 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
641 };
642 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
643 atmel,pins =
644 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
645 };
646 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
647 atmel,pins =
648 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
649 };
650 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
651 atmel,pins =
652 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
653 };
654 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
655 atmel,pins =
656 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
657 };
658 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
659 atmel,pins =
660 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
661 };
662
663 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
664 atmel,pins =
665 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
666 };
667 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
668 atmel,pins =
669 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
670 };
671 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
672 atmel,pins =
673 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
674 };
675 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
676 atmel,pins =
677 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
678 };
679
680 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
681 atmel,pins =
682 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
683 };
684 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
685 atmel,pins =
686 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
687 };
688 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
689 atmel,pins =
690 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
691 };
692 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
693 atmel,pins =
694 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
695 };
696 };
697
655ff266
LD		 698 spi0 {
699 pinctrl_spi0: spi0-0 {
700 atmel,pins =
c9d0f317
JCPV		 701 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
702 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
703 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 704 };
705 };
706
707 spi1 {
708 pinctrl_spi1: spi1-0 {
709 atmel,pins =
c9d0f317
JCPV		 710 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
711 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
712 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 713 };
714 };
715
716 ssc0 {
717 pinctrl_ssc0_tx: ssc0_tx {
718 atmel,pins =
c9d0f317
JCPV		 719 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
720 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
721 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 722 };
723
724 pinctrl_ssc0_rx: ssc0_rx {
725 atmel,pins =
c9d0f317
JCPV		 726 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
727 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
728 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 729 };
730 };
731
732 ssc1 {
733 pinctrl_ssc1_tx: ssc1_tx {
734 atmel,pins =
c9d0f317
JCPV		 735 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
736 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
737 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 738 };
739
740 pinctrl_ssc1_rx: ssc1_rx {
741 atmel,pins =
c9d0f317
JCPV		 742 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
743 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
744 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 745 };
746 };
747
655ff266
LD		 748 usart0 {
749 pinctrl_usart0: usart0-0 {
750 atmel,pins =
c9d0f317
JCPV		 751 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
752 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 753 };
754
755 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
756 atmel,pins =
c9d0f317
JCPV		 757 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
758 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 759 };
760 };
761
762 usart1 {
763 pinctrl_usart1: usart1-0 {
764 atmel,pins =
c9d0f317
JCPV		 765 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
766 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 767 };
768
769 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
770 atmel,pins =
c9d0f317
JCPV		 771 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
772 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 773 };
774 };
775
776 usart2 {
777 pinctrl_usart2: usart2-0 {
778 atmel,pins =
c9d0f317
JCPV		 779 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
780 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 781 };
782
783 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
784 atmel,pins =
c9d0f317
JCPV		 785 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
786 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 787 };
788 };
789
790 usart3 {
791 pinctrl_usart3: usart3-0 {
792 atmel,pins =
c9d0f317
JCPV		 793 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
794 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 795 };
796
797 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
798 atmel,pins =
c9d0f317
JCPV		 799 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
800 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 801 };
802 };
c9d0f317
JCPV		 803
804
805 pioA: gpio@fffff200 {
806 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
807 reg = <0xfffff200 0x100>;
5e8b3bc3 808 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 809 #gpio-cells = <2>;
810 gpio-controller;
811 interrupt-controller;
812 #interrupt-cells = <2>;
d2e8190b 813 clocks = <&pioA_clk>;
c9d0f317
JCPV		 814 };
815
816 pioB: gpio@fffff400 {
817 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
818 reg = <0xfffff400 0x100>;
5e8b3bc3 819 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 820 #gpio-cells = <2>;
821 gpio-controller;
822 interrupt-controller;
823 #interrupt-cells = <2>;
d2e8190b 824 clocks = <&pioB_clk>;
c9d0f317
JCPV		 825 };
826
827 pioC: gpio@fffff600 {
828 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
829 reg = <0xfffff600 0x100>;
5e8b3bc3 830 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 831 #gpio-cells = <2>;
832 gpio-controller;
833 interrupt-controller;
834 #interrupt-cells = <2>;
d2e8190b 835 clocks = <&pioC_clk>;
c9d0f317
JCPV		 836 };
837
838 pioD: gpio@fffff800 {
839 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
840 reg = <0xfffff800 0x100>;
5e8b3bc3 841 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 842 #gpio-cells = <2>;
843 gpio-controller;
844 interrupt-controller;
845 #interrupt-cells = <2>;
d2e8190b 846 clocks = <&pioD_clk>;
c9d0f317
JCPV		 847 };
848
849 pioE: gpio@fffffa00 {
850 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
851 reg = <0xfffffa00 0x100>;
5e8b3bc3 852 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 853 #gpio-cells = <2>;
854 gpio-controller;
855 interrupt-controller;
856 #interrupt-cells = <2>;
d2e8190b 857 clocks = <&pioE_clk>;
c9d0f317 858 };
655ff266
LD		 859 };
860
861 pmc: pmc@fffffc00 {
d2e8190b 862 compatible = "atmel,sama5d3-pmc";
655ff266 863 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 864 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
865 interrupt-controller;
866 #address-cells = <1>;
867 #size-cells = <0>;
868 #interrupt-cells = <1>;
869
4753219d
BB		 870 main_rc_osc: main_rc_osc {
871 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
d2e8190b 872 #clock-cells = <0>;
4753219d
BB		 873 interrupt-parent = <&pmc>;
874 interrupts = <AT91_PMC_MOSCRCS>;
875 clock-frequency = <12000000>;
876 clock-accuracy = <50000000>;
d2e8190b
BB		 877 };
878
4753219d
BB		 879 main_osc: main_osc {
880 compatible = "atmel,at91rm9200-clk-main-osc";
d2e8190b
BB		 881 #clock-cells = <0>;
882 interrupt-parent = <&pmc>;
883 interrupts = <AT91_PMC_MOSCS>;
4753219d
BB		 884 clocks = <&main_xtal>;
885 };
886
887 main: mainck {
888 compatible = "atmel,at91sam9x5-clk-main";
889 #clock-cells = <0>;
890 interrupt-parent = <&pmc>;
891 interrupts = <AT91_PMC_MOSCSELS>;
892 clocks = <&main_rc_osc &main_osc>;
d2e8190b
BB		 893 };
894
895 plla: pllack {
896 compatible = "atmel,sama5d3-clk-pll";
897 #clock-cells = <0>;
898 interrupt-parent = <&pmc>;
899 interrupts = <AT91_PMC_LOCKA>;
900 clocks = <&main>;
901 reg = <0>;
902 atmel,clk-input-range = <8000000 50000000>;
903 #atmel,pll-clk-output-range-cells = <4>;
904 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
905 };
906
907 plladiv: plladivck {
908 compatible = "atmel,at91sam9x5-clk-plldiv";
909 #clock-cells = <0>;
910 clocks = <&plla>;
911 };
912
913 utmi: utmick {
914 compatible = "atmel,at91sam9x5-clk-utmi";
915 #clock-cells = <0>;
916 interrupt-parent = <&pmc>;
917 interrupts = <AT91_PMC_LOCKU>;
918 clocks = <&main>;
919 };
920
921 mck: masterck {
922 compatible = "atmel,at91sam9x5-clk-master";
923 #clock-cells = <0>;
924 interrupt-parent = <&pmc>;
925 interrupts = <AT91_PMC_MCKRDY>;
926 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
927 atmel,clk-output-range = <0 166000000>;
928 atmel,clk-divisors = <1 2 4 3>;
929 };
930
931 usb: usbck {
932 compatible = "atmel,at91sam9x5-clk-usb";
933 #clock-cells = <0>;
934 clocks = <&plladiv>, <&utmi>;
935 };
936
937 prog: progck {
938 compatible = "atmel,at91sam9x5-clk-programmable";
939 #address-cells = <1>;
940 #size-cells = <0>;
941 interrupt-parent = <&pmc>;
942 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
943
944 prog0: prog0 {
945 #clock-cells = <0>;
946 reg = <0>;
947 interrupts = <AT91_PMC_PCKRDY(0)>;
948 };
949
950 prog1: prog1 {
951 #clock-cells = <0>;
952 reg = <1>;
953 interrupts = <AT91_PMC_PCKRDY(1)>;
954 };
955
956 prog2: prog2 {
957 #clock-cells = <0>;
958 reg = <2>;
959 interrupts = <AT91_PMC_PCKRDY(2)>;
960 };
961 };
962
963 smd: smdclk {
964 compatible = "atmel,at91sam9x5-clk-smd";
965 #clock-cells = <0>;
966 clocks = <&plladiv>, <&utmi>;
967 };
968
969 systemck {
970 compatible = "atmel,at91rm9200-clk-system";
971 #address-cells = <1>;
972 #size-cells = <0>;
973
974 ddrck: ddrck {
975 #clock-cells = <0>;
976 reg = <2>;
977 clocks = <&mck>;
978 };
979
980 smdck: smdck {
981 #clock-cells = <0>;
982 reg = <4>;
983 clocks = <&smd>;
984 };
985
986 uhpck: uhpck {
987 #clock-cells = <0>;
988 reg = <6>;
989 clocks = <&usb>;
990 };
991
992 udpck: udpck {
993 #clock-cells = <0>;
994 reg = <7>;
995 clocks = <&usb>;
996 };
997
998 pck0: pck0 {
999 #clock-cells = <0>;
1000 reg = <8>;
1001 clocks = <&prog0>;
1002 };
1003
1004 pck1: pck1 {
1005 #clock-cells = <0>;
1006 reg = <9>;
1007 clocks = <&prog1>;
1008 };
1009
1010 pck2: pck2 {
1011 #clock-cells = <0>;
1012 reg = <10>;
1013 clocks = <&prog2>;
1014 };
1015 };
1016
1017 periphck {
1018 compatible = "atmel,at91sam9x5-clk-peripheral";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 clocks = <&mck>;
1022
1023 dbgu_clk: dbgu_clk {
1024 #clock-cells = <0>;
1025 reg = <2>;
1026 };
1027
8a85ba20
AB		 1028 hsmc_clk: hsmc_clk {
1029 #clock-cells = <0>;
1030 reg = <5>;
1031 };
1032
d2e8190b
BB		 1033 pioA_clk: pioA_clk {
1034 #clock-cells = <0>;
1035 reg = <6>;
1036 };
1037
1038 pioB_clk: pioB_clk {
1039 #clock-cells = <0>;
1040 reg = <7>;
1041 };
1042
1043 pioC_clk: pioC_clk {
1044 #clock-cells = <0>;
1045 reg = <8>;
1046 };
1047
1048 pioD_clk: pioD_clk {
1049 #clock-cells = <0>;
1050 reg = <9>;
1051 };
1052
1053 pioE_clk: pioE_clk {
1054 #clock-cells = <0>;
1055 reg = <10>;
1056 };
1057
1058 usart0_clk: usart0_clk {
1059 #clock-cells = <0>;
1060 reg = <12>;
1061 atmel,clk-output-range = <0 66000000>;
1062 };
1063
1064 usart1_clk: usart1_clk {
1065 #clock-cells = <0>;
1066 reg = <13>;
1067 atmel,clk-output-range = <0 66000000>;
1068 };
1069
1070 usart2_clk: usart2_clk {
1071 #clock-cells = <0>;
1072 reg = <14>;
1073 atmel,clk-output-range = <0 66000000>;
1074 };
1075
1076 usart3_clk: usart3_clk {
1077 #clock-cells = <0>;
1078 reg = <15>;
1079 atmel,clk-output-range = <0 66000000>;
1080 };
1081
1082 twi0_clk: twi0_clk {
1083 reg = <18>;
1084 #clock-cells = <0>;
1085 atmel,clk-output-range = <0 16625000>;
1086 };
1087
1088 twi1_clk: twi1_clk {
1089 #clock-cells = <0>;
1090 reg = <19>;
1091 atmel,clk-output-range = <0 16625000>;
1092 };
1093
1094 twi2_clk: twi2_clk {
1095 #clock-cells = <0>;
1096 reg = <20>;
1097 atmel,clk-output-range = <0 16625000>;
1098 };
1099
1100 mci0_clk: mci0_clk {
1101 #clock-cells = <0>;
1102 reg = <21>;
1103 };
1104
1105 mci1_clk: mci1_clk {
1106 #clock-cells = <0>;
1107 reg = <22>;
1108 };
1109
1110 spi0_clk: spi0_clk {
1111 #clock-cells = <0>;
1112 reg = <24>;
1113 atmel,clk-output-range = <0 133000000>;
1114 };
1115
1116 spi1_clk: spi1_clk {
1117 #clock-cells = <0>;
1118 reg = <25>;
1119 atmel,clk-output-range = <0 133000000>;
1120 };
1121
1122 tcb0_clk: tcb0_clk {
1123 #clock-cells = <0>;
1124 reg = <26>;
1125 atmel,clk-output-range = <0 133000000>;
1126 };
1127
1128 pwm_clk: pwm_clk {
1129 #clock-cells = <0>;
1130 reg = <28>;
1131 };
1132
1133 adc_clk: adc_clk {
1134 #clock-cells = <0>;
1135 reg = <29>;
1136 atmel,clk-output-range = <0 66000000>;
1137 };
1138
1139 dma0_clk: dma0_clk {
1140 #clock-cells = <0>;
1141 reg = <30>;
1142 };
1143
1144 dma1_clk: dma1_clk {
1145 #clock-cells = <0>;
1146 reg = <31>;
1147 };
1148
1149 uhphs_clk: uhphs_clk {
1150 #clock-cells = <0>;
1151 reg = <32>;
1152 };
1153
1154 udphs_clk: udphs_clk {
1155 #clock-cells = <0>;
1156 reg = <33>;
1157 };
1158
1159 isi_clk: isi_clk {
1160 #clock-cells = <0>;
1161 reg = <37>;
1162 };
1163
1164 ssc0_clk: ssc0_clk {
1165 #clock-cells = <0>;
1166 reg = <38>;
1167 atmel,clk-output-range = <0 66000000>;
1168 };
1169
1170 ssc1_clk: ssc1_clk {
1171 #clock-cells = <0>;
1172 reg = <39>;
1173 atmel,clk-output-range = <0 66000000>;
1174 };
1175
1176 sha_clk: sha_clk {
1177 #clock-cells = <0>;
1178 reg = <42>;
1179 };
1180
1181 aes_clk: aes_clk {
1182 #clock-cells = <0>;
1183 reg = <43>;
1184 };
1185
1186 tdes_clk: tdes_clk {
1187 #clock-cells = <0>;
1188 reg = <44>;
1189 };
1190
1191 trng_clk: trng_clk {
1192 #clock-cells = <0>;
1193 reg = <45>;
1194 };
1195
1196 fuse_clk: fuse_clk {
1197 #clock-cells = <0>;
1198 reg = <48>;
1199 };
063de897
AB		 1200
1201 mpddr_clk: mpddr_clk {
1202 #clock-cells = <0>;
1203 reg = <49>;
1204 };
d2e8190b 1205 };
655ff266
LD		 1206 };
1207
1208 rstc@fffffe00 {
1209 compatible = "atmel,at91sam9g45-rstc";
1210 reg = <0xfffffe00 0x10>;
1211 };
1212
16aa7f1f
MR		 1213 shutdown-controller@fffffe10 {
1214 compatible = "atmel,at91sam9x5-shdwc";
1215 reg = <0xfffffe10 0x10>;
1216 };
1217
655ff266
LD		 1218 pit: timer@fffffe30 {
1219 compatible = "atmel,at91sam9260-pit";
1220 reg = <0xfffffe30 0xf>;
5e8b3bc3 1221 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1222 clocks = <&mck>;
655ff266
LD		 1223 };
1224
1225 watchdog@fffffe40 {
1226 compatible = "atmel,at91sam9260-wdt";
1227 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1228 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1229 atmel,watchdog-type = "hardware";
1230 atmel,reset-type = "all";
1231 atmel,dbg-halt;
1232 atmel,idle-halt;
655ff266
LD		 1233 status = "disabled";
1234 };
1235
4753219d
BB		 1236 sckc@fffffe50 {
1237 compatible = "atmel,at91sam9x5-sckc";
1238 reg = <0xfffffe50 0x4>;
1239
1240 slow_rc_osc: slow_rc_osc {
1241 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1242 #clock-cells = <0>;
1243 clock-frequency = <32768>;
1244 clock-accuracy = <50000000>;
1245 atmel,startup-time-usec = <75>;
1246 };
1247
1248 slow_osc: slow_osc {
1249 compatible = "atmel,at91sam9x5-clk-slow-osc";
1250 #clock-cells = <0>;
1251 clocks = <&slow_xtal>;
1252 atmel,startup-time-usec = <1200000>;
1253 };
1254
1255 clk32k: slowck {
1256 compatible = "atmel,at91sam9x5-clk-slow";
1257 #clock-cells = <0>;
1258 clocks = <&slow_rc_osc &slow_osc>;
1259 };
1260 };
1261
655ff266
LD		 1262 rtc@fffffeb0 {
1263 compatible = "atmel,at91rm9200-rtc";
1264 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1265 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1266 };
1267 };
1268
1269 usb0: gadget@00500000 {
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1272 compatible = "atmel,at91sam9rl-udc";
1273 reg = <0x00500000 0x100000
1274 0xf8030000 0x4000>;
5e8b3bc3 1275 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1276 clocks = <&udphs_clk>, <&utmi>;
1277 clock-names = "pclk", "hclk";
655ff266
LD		 1278 status = "disabled";
1279
1280 ep0 {
1281 reg = <0>;
1282 atmel,fifo-size = <64>;
1283 atmel,nb-banks = <1>;
1284 };
1285
1286 ep1 {
1287 reg = <1>;
1288 atmel,fifo-size = <1024>;
1289 atmel,nb-banks = <3>;
1290 atmel,can-dma;
1291 atmel,can-isoc;
1292 };
1293
1294 ep2 {
1295 reg = <2>;
1296 atmel,fifo-size = <1024>;
1297 atmel,nb-banks = <3>;
1298 atmel,can-dma;
1299 atmel,can-isoc;
1300 };
1301
1302 ep3 {
1303 reg = <3>;
1304 atmel,fifo-size = <1024>;
1305 atmel,nb-banks = <2>;
1306 atmel,can-dma;
1307 };
1308
1309 ep4 {
1310 reg = <4>;
1311 atmel,fifo-size = <1024>;
1312 atmel,nb-banks = <2>;
1313 atmel,can-dma;
1314 };
1315
1316 ep5 {
1317 reg = <5>;
1318 atmel,fifo-size = <1024>;
1319 atmel,nb-banks = <2>;
1320 atmel,can-dma;
1321 };
1322
1323 ep6 {
1324 reg = <6>;
1325 atmel,fifo-size = <1024>;
1326 atmel,nb-banks = <2>;
1327 atmel,can-dma;
1328 };
1329
1330 ep7 {
1331 reg = <7>;
1332 atmel,fifo-size = <1024>;
1333 atmel,nb-banks = <2>;
1334 atmel,can-dma;
1335 };
1336
1337 ep8 {
1338 reg = <8>;
1339 atmel,fifo-size = <1024>;
1340 atmel,nb-banks = <2>;
1341 };
1342
1343 ep9 {
1344 reg = <9>;
1345 atmel,fifo-size = <1024>;
1346 atmel,nb-banks = <2>;
1347 };
1348
1349 ep10 {
1350 reg = <10>;
1351 atmel,fifo-size = <1024>;
1352 atmel,nb-banks = <2>;
1353 };
1354
1355 ep11 {
1356 reg = <11>;
1357 atmel,fifo-size = <1024>;
1358 atmel,nb-banks = <2>;
1359 };
1360
1361 ep12 {
1362 reg = <12>;
1363 atmel,fifo-size = <1024>;
1364 atmel,nb-banks = <2>;
1365 };
1366
1367 ep13 {
1368 reg = <13>;
1369 atmel,fifo-size = <1024>;
1370 atmel,nb-banks = <2>;
1371 };
1372
1373 ep14 {
1374 reg = <14>;
1375 atmel,fifo-size = <1024>;
1376 atmel,nb-banks = <2>;
1377 };
1378
1379 ep15 {
1380 reg = <15>;
1381 atmel,fifo-size = <1024>;
1382 atmel,nb-banks = <2>;
1383 };
1384 };
1385
1386 usb1: ohci@00600000 {
1387 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1388 reg = <0x00600000 0x100000>;
5e8b3bc3 1389 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1390 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1391 <&uhpck>;
1392 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1393 status = "disabled";
1394 };
1395
1396 usb2: ehci@00700000 {
1397 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1398 reg = <0x00700000 0x100000>;
5e8b3bc3 1399 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1400 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1401 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1402 status = "disabled";
1403 };
1404
1405 nand0: nand@60000000 {
1406 compatible = "atmel,at91rm9200-nand";
1407 #address-cells = <1>;
1408 #size-cells = <1>;
8ae599ef 1409 ranges;
655ff266
LD		 1410 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1411 0xffffc070 0x00000490 /* SMC PMECC regs */
1412 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1413 0x00110000 0x00018000 /* ROM code */
655ff266 1414 >;
5e8b3bc3 1415 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1416 atmel,nand-addr-offset = <21>;
1417 atmel,nand-cmd-offset = <22>;
e8b2da6e 1418 atmel,nand-has-dma;
655ff266
LD		 1419 pinctrl-names = "default";
1420 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1421 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1422 status = "disabled";
8ae599ef
JW		 1423
1424 nfc@70000000 {
1425 compatible = "atmel,sama5d3-nfc";
1426 #address-cells = <1>;
1427 #size-cells = <1>;
1428 reg = <
1429 0x70000000 0x10000000 /* NFC Command Registers */
1430 0xffffc000 0x00000070 /* NFC HSMC regs */
1431 0x00200000 0x00100000 /* NFC SRAM banks */
1432 >;
8a85ba20 1433 clocks = <&hsmc_clk>;
8ae599ef 1434 };
655ff266
LD		 1435 };
1436 };
1437};
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