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655ff266 LD |
1 | /* |
2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | |
3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | |
4 | * | |
5 | * Copyright (C) 2013 Atmel, | |
6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | |
7 | * | |
8 | * Licensed under GPLv2 or later. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
13 | / { | |
14 | model = "Atmel SAMA5D3 family SoC"; | |
15 | compatible = "atmel,sama5d3", "atmel,sama5"; | |
16 | interrupt-parent = <&aic>; | |
17 | ||
18 | aliases { | |
19 | serial0 = &dbgu; | |
20 | serial1 = &usart0; | |
21 | serial2 = &usart1; | |
22 | serial3 = &usart2; | |
23 | serial4 = &usart3; | |
24 | gpio0 = &pioA; | |
25 | gpio1 = &pioB; | |
26 | gpio2 = &pioC; | |
27 | gpio3 = &pioD; | |
28 | gpio4 = &pioE; | |
29 | tcb0 = &tcb0; | |
30 | tcb1 = &tcb1; | |
31 | i2c0 = &i2c0; | |
32 | i2c1 = &i2c1; | |
33 | i2c2 = &i2c2; | |
34 | ssc0 = &ssc0; | |
35 | ssc1 = &ssc1; | |
36 | }; | |
37 | cpus { | |
38 | cpu@0 { | |
39 | compatible = "arm,cortex-a5"; | |
40 | }; | |
41 | }; | |
42 | ||
43 | memory { | |
44 | reg = <0x20000000 0x8000000>; | |
45 | }; | |
46 | ||
47 | ahb { | |
48 | compatible = "simple-bus"; | |
49 | #address-cells = <1>; | |
50 | #size-cells = <1>; | |
51 | ranges; | |
52 | ||
53 | apb { | |
54 | compatible = "simple-bus"; | |
55 | #address-cells = <1>; | |
56 | #size-cells = <1>; | |
57 | ranges; | |
58 | ||
59 | mmc0: mmc@f0000000 { | |
60 | compatible = "atmel,hsmci"; | |
61 | reg = <0xf0000000 0x600>; | |
62 | interrupts = <21 4 0>; | |
05c1bc97 LD |
63 | dmas = <&dma0 2 0>; |
64 | dma-names = "rxtx"; | |
655ff266 LD |
65 | pinctrl-names = "default"; |
66 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | |
67 | status = "disabled"; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <0>; | |
70 | }; | |
71 | ||
72 | spi0: spi@f0004000 { | |
73 | #address-cells = <1>; | |
74 | #size-cells = <0>; | |
75 | compatible = "atmel,at91sam9x5-spi"; | |
76 | reg = <0xf0004000 0x100>; | |
77 | interrupts = <24 4 3>; | |
78 | cs-gpios = <&pioD 13 0 | |
79 | &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ | |
80 | &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ | |
81 | &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ | |
82 | >; | |
83 | pinctrl-names = "default"; | |
84 | pinctrl-0 = <&pinctrl_spi0>; | |
85 | status = "disabled"; | |
86 | }; | |
87 | ||
88 | ssc0: ssc@f0008000 { | |
89 | compatible = "atmel,at91sam9g45-ssc"; | |
90 | reg = <0xf0008000 0x4000>; | |
91 | interrupts = <38 4 4>; | |
92 | pinctrl-names = "default"; | |
93 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
94 | status = "disabled"; | |
95 | }; | |
96 | ||
97 | can0: can@f000c000 { | |
98 | compatible = "atmel,at91sam9x5-can"; | |
99 | reg = <0xf000c000 0x300>; | |
100 | interrupts = <40 4 3>; | |
101 | pinctrl-names = "default"; | |
102 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | |
103 | status = "disabled"; | |
104 | }; | |
105 | ||
106 | tcb0: timer@f0010000 { | |
107 | compatible = "atmel,at91sam9x5-tcb"; | |
108 | reg = <0xf0010000 0x100>; | |
109 | interrupts = <26 4 0>; | |
110 | }; | |
111 | ||
112 | i2c0: i2c@f0014000 { | |
113 | compatible = "atmel,at91sam9x5-i2c"; | |
114 | reg = <0xf0014000 0x4000>; | |
115 | interrupts = <18 4 6>; | |
d9a63a45 LD |
116 | dmas = <&dma0 2 7>, |
117 | <&dma0 2 8>; | |
118 | dma-names = "tx", "rx"; | |
655ff266 LD |
119 | pinctrl-names = "default"; |
120 | pinctrl-0 = <&pinctrl_i2c0>; | |
121 | #address-cells = <1>; | |
122 | #size-cells = <0>; | |
123 | status = "disabled"; | |
124 | }; | |
125 | ||
126 | i2c1: i2c@f0018000 { | |
127 | compatible = "atmel,at91sam9x5-i2c"; | |
128 | reg = <0xf0018000 0x4000>; | |
129 | interrupts = <19 4 6>; | |
d9a63a45 LD |
130 | dmas = <&dma0 2 9>, |
131 | <&dma0 2 10>; | |
132 | dma-names = "tx", "rx"; | |
655ff266 LD |
133 | pinctrl-names = "default"; |
134 | pinctrl-0 = <&pinctrl_i2c1>; | |
135 | #address-cells = <1>; | |
136 | #size-cells = <0>; | |
137 | status = "disabled"; | |
138 | }; | |
139 | ||
140 | usart0: serial@f001c000 { | |
141 | compatible = "atmel,at91sam9260-usart"; | |
142 | reg = <0xf001c000 0x100>; | |
143 | interrupts = <12 4 5>; | |
144 | pinctrl-names = "default"; | |
145 | pinctrl-0 = <&pinctrl_usart0>; | |
146 | status = "disabled"; | |
147 | }; | |
148 | ||
149 | usart1: serial@f0020000 { | |
150 | compatible = "atmel,at91sam9260-usart"; | |
151 | reg = <0xf0020000 0x100>; | |
152 | interrupts = <13 4 5>; | |
153 | pinctrl-names = "default"; | |
154 | pinctrl-0 = <&pinctrl_usart1>; | |
155 | status = "disabled"; | |
156 | }; | |
157 | ||
158 | macb0: ethernet@f0028000 { | |
159 | compatible = "cnds,pc302-gem", "cdns,gem"; | |
160 | reg = <0xf0028000 0x100>; | |
161 | interrupts = <34 4 3>; | |
162 | pinctrl-names = "default"; | |
163 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | |
164 | status = "disabled"; | |
165 | }; | |
166 | ||
167 | isi: isi@f0034000 { | |
168 | compatible = "atmel,at91sam9g45-isi"; | |
169 | reg = <0xf0034000 0x4000>; | |
170 | interrupts = <37 4 5>; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | mmc1: mmc@f8000000 { | |
175 | compatible = "atmel,hsmci"; | |
176 | reg = <0xf8000000 0x600>; | |
177 | interrupts = <22 4 0>; | |
05c1bc97 LD |
178 | dmas = <&dma1 2 0>; |
179 | dma-names = "rxtx"; | |
655ff266 LD |
180 | pinctrl-names = "default"; |
181 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | |
182 | status = "disabled"; | |
183 | #address-cells = <1>; | |
184 | #size-cells = <0>; | |
185 | }; | |
186 | ||
187 | mmc2: mmc@f8004000 { | |
188 | compatible = "atmel,hsmci"; | |
189 | reg = <0xf8004000 0x600>; | |
190 | interrupts = <23 4 0>; | |
05c1bc97 LD |
191 | dmas = <&dma1 2 1>; |
192 | dma-names = "rxtx"; | |
655ff266 LD |
193 | pinctrl-names = "default"; |
194 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | |
195 | status = "disabled"; | |
196 | #address-cells = <1>; | |
197 | #size-cells = <0>; | |
198 | }; | |
199 | ||
200 | spi1: spi@f8008000 { | |
201 | #address-cells = <1>; | |
202 | #size-cells = <0>; | |
203 | compatible = "atmel,at91sam9x5-spi"; | |
204 | reg = <0xf8008000 0x100>; | |
205 | interrupts = <25 4 3>; | |
206 | cs-gpios = <&pioC 25 0 | |
207 | &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ | |
208 | &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ | |
209 | &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ | |
210 | >; | |
211 | pinctrl-names = "default"; | |
212 | pinctrl-0 = <&pinctrl_spi1>; | |
213 | status = "disabled"; | |
214 | }; | |
215 | ||
216 | ssc1: ssc@f800c000 { | |
217 | compatible = "atmel,at91sam9g45-ssc"; | |
218 | reg = <0xf800c000 0x4000>; | |
219 | interrupts = <39 4 4>; | |
220 | pinctrl-names = "default"; | |
221 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
225 | can1: can@f8010000 { | |
226 | compatible = "atmel,at91sam9x5-can"; | |
227 | reg = <0xf8010000 0x300>; | |
228 | interrupts = <41 4 3>; | |
229 | pinctrl-names = "default"; | |
230 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | |
231 | }; | |
232 | ||
233 | tcb1: timer@f8014000 { | |
234 | compatible = "atmel,at91sam9x5-tcb"; | |
235 | reg = <0xf8014000 0x100>; | |
236 | interrupts = <27 4 0>; | |
237 | }; | |
238 | ||
239 | adc0: adc@f8018000 { | |
240 | compatible = "atmel,at91sam9260-adc"; | |
241 | reg = <0xf8018000 0x100>; | |
242 | interrupts = <29 4 5>; | |
243 | pinctrl-names = "default"; | |
244 | pinctrl-0 = < | |
245 | &pinctrl_adc0_adtrg | |
246 | &pinctrl_adc0_ad0 | |
247 | &pinctrl_adc0_ad1 | |
248 | &pinctrl_adc0_ad2 | |
249 | &pinctrl_adc0_ad3 | |
250 | &pinctrl_adc0_ad4 | |
251 | &pinctrl_adc0_ad5 | |
252 | &pinctrl_adc0_ad6 | |
253 | &pinctrl_adc0_ad7 | |
254 | &pinctrl_adc0_ad8 | |
255 | &pinctrl_adc0_ad9 | |
256 | &pinctrl_adc0_ad10 | |
257 | &pinctrl_adc0_ad11 | |
258 | >; | |
259 | atmel,adc-channel-base = <0x50>; | |
260 | atmel,adc-channels-used = <0xfff>; | |
261 | atmel,adc-drdy-mask = <0x1000000>; | |
262 | atmel,adc-num-channels = <12>; | |
263 | atmel,adc-startup-time = <40>; | |
264 | atmel,adc-status-register = <0x30>; | |
265 | atmel,adc-trigger-register = <0xc0>; | |
266 | atmel,adc-use-external; | |
267 | atmel,adc-vref = <3000>; | |
268 | atmel,adc-res = <10 12>; | |
269 | atmel,adc-res-names = "lowres", "highres"; | |
270 | status = "disabled"; | |
271 | ||
272 | trigger@0 { | |
273 | trigger-name = "external-rising"; | |
274 | trigger-value = <0x1>; | |
275 | trigger-external; | |
276 | }; | |
277 | trigger@1 { | |
278 | trigger-name = "external-falling"; | |
279 | trigger-value = <0x2>; | |
280 | trigger-external; | |
281 | }; | |
282 | trigger@2 { | |
283 | trigger-name = "external-any"; | |
284 | trigger-value = <0x3>; | |
285 | trigger-external; | |
286 | }; | |
287 | trigger@3 { | |
288 | trigger-name = "continuous"; | |
289 | trigger-value = <0x6>; | |
290 | }; | |
291 | }; | |
292 | ||
293 | tsadcc: tsadcc@f8018000 { | |
294 | compatible = "atmel,at91sam9x5-tsadcc"; | |
295 | reg = <0xf8018000 0x4000>; | |
296 | interrupts = <29 4 5>; | |
297 | atmel,tsadcc_clock = <300000>; | |
298 | atmel,filtering_average = <0x03>; | |
299 | atmel,pendet_debounce = <0x08>; | |
300 | atmel,pendet_sensitivity = <0x02>; | |
301 | atmel,ts_sample_hold_time = <0x0a>; | |
302 | status = "disabled"; | |
303 | }; | |
304 | ||
305 | i2c2: i2c@f801c000 { | |
306 | compatible = "atmel,at91sam9x5-i2c"; | |
307 | reg = <0xf801c000 0x4000>; | |
308 | interrupts = <20 4 6>; | |
d9a63a45 LD |
309 | dmas = <&dma1 2 11>, |
310 | <&dma1 2 12>; | |
311 | dma-names = "tx", "rx"; | |
655ff266 LD |
312 | #address-cells = <1>; |
313 | #size-cells = <0>; | |
314 | status = "disabled"; | |
315 | }; | |
316 | ||
317 | usart2: serial@f8020000 { | |
318 | compatible = "atmel,at91sam9260-usart"; | |
319 | reg = <0xf8020000 0x100>; | |
320 | interrupts = <14 4 5>; | |
321 | pinctrl-names = "default"; | |
322 | pinctrl-0 = <&pinctrl_usart2>; | |
323 | status = "disabled"; | |
324 | }; | |
325 | ||
326 | usart3: serial@f8024000 { | |
327 | compatible = "atmel,at91sam9260-usart"; | |
328 | reg = <0xf8024000 0x100>; | |
329 | interrupts = <15 4 5>; | |
330 | pinctrl-names = "default"; | |
331 | pinctrl-0 = <&pinctrl_usart3>; | |
332 | status = "disabled"; | |
333 | }; | |
334 | ||
335 | macb1: ethernet@f802c000 { | |
336 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
337 | reg = <0xf802c000 0x100>; | |
338 | interrupts = <35 4 3>; | |
339 | pinctrl-names = "default"; | |
340 | pinctrl-0 = <&pinctrl_macb1_rmii>; | |
341 | status = "disabled"; | |
342 | }; | |
343 | ||
344 | sha@f8034000 { | |
345 | compatible = "atmel,sam9g46-sha"; | |
346 | reg = <0xf8034000 0x100>; | |
347 | interrupts = <42 4 0>; | |
348 | }; | |
349 | ||
350 | aes@f8038000 { | |
351 | compatible = "atmel,sam9g46-aes"; | |
352 | reg = <0xf8038000 0x100>; | |
353 | interrupts = <43 4 0>; | |
354 | }; | |
355 | ||
356 | tdes@f803c000 { | |
357 | compatible = "atmel,sam9g46-tdes"; | |
358 | reg = <0xf803c000 0x100>; | |
359 | interrupts = <44 4 0>; | |
360 | }; | |
361 | ||
362 | dma0: dma-controller@ffffe600 { | |
363 | compatible = "atmel,at91sam9g45-dma"; | |
364 | reg = <0xffffe600 0x200>; | |
365 | interrupts = <30 4 0>; | |
980ce7d9 | 366 | #dma-cells = <2>; |
655ff266 LD |
367 | }; |
368 | ||
369 | dma1: dma-controller@ffffe800 { | |
370 | compatible = "atmel,at91sam9g45-dma"; | |
371 | reg = <0xffffe800 0x200>; | |
372 | interrupts = <31 4 0>; | |
980ce7d9 | 373 | #dma-cells = <2>; |
655ff266 LD |
374 | }; |
375 | ||
376 | ramc0: ramc@ffffea00 { | |
377 | compatible = "atmel,at91sam9g45-ddramc"; | |
378 | reg = <0xffffea00 0x200>; | |
379 | }; | |
380 | ||
381 | dbgu: serial@ffffee00 { | |
382 | compatible = "atmel,at91sam9260-usart"; | |
383 | reg = <0xffffee00 0x200>; | |
384 | interrupts = <2 4 7>; | |
385 | pinctrl-names = "default"; | |
386 | pinctrl-0 = <&pinctrl_dbgu>; | |
387 | status = "disabled"; | |
388 | }; | |
389 | ||
390 | aic: interrupt-controller@fffff000 { | |
391 | #interrupt-cells = <3>; | |
392 | compatible = "atmel,sama5d3-aic"; | |
393 | interrupt-controller; | |
394 | reg = <0xfffff000 0x200>; | |
395 | atmel,external-irqs = <47>; | |
396 | }; | |
397 | ||
398 | pinctrl@fffff200 { | |
399 | #address-cells = <1>; | |
400 | #size-cells = <1>; | |
401 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
402 | ranges = <0xfffff200 0xfffff200 0xa00>; | |
403 | atmel,mux-mask = < | |
404 | /* A B C */ | |
405 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | |
406 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | |
407 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | |
408 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | |
409 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | |
410 | >; | |
411 | ||
412 | /* shared pinctrl settings */ | |
413 | adc0 { | |
414 | pinctrl_adc0_adtrg: adc0_adtrg { | |
415 | atmel,pins = | |
416 | <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ | |
417 | }; | |
418 | pinctrl_adc0_ad0: adc0_ad0 { | |
419 | atmel,pins = | |
420 | <3 20 0x1 0x0>; /* PD20 periph A AD0 */ | |
421 | }; | |
422 | pinctrl_adc0_ad1: adc0_ad1 { | |
423 | atmel,pins = | |
424 | <3 21 0x1 0x0>; /* PD21 periph A AD1 */ | |
425 | }; | |
426 | pinctrl_adc0_ad2: adc0_ad2 { | |
427 | atmel,pins = | |
428 | <3 22 0x1 0x0>; /* PD22 periph A AD2 */ | |
429 | }; | |
430 | pinctrl_adc0_ad3: adc0_ad3 { | |
431 | atmel,pins = | |
432 | <3 23 0x1 0x0>; /* PD23 periph A AD3 */ | |
433 | }; | |
434 | pinctrl_adc0_ad4: adc0_ad4 { | |
435 | atmel,pins = | |
436 | <3 24 0x1 0x0>; /* PD24 periph A AD4 */ | |
437 | }; | |
438 | pinctrl_adc0_ad5: adc0_ad5 { | |
439 | atmel,pins = | |
440 | <3 25 0x1 0x0>; /* PD25 periph A AD5 */ | |
441 | }; | |
442 | pinctrl_adc0_ad6: adc0_ad6 { | |
443 | atmel,pins = | |
444 | <3 26 0x1 0x0>; /* PD26 periph A AD6 */ | |
445 | }; | |
446 | pinctrl_adc0_ad7: adc0_ad7 { | |
447 | atmel,pins = | |
448 | <3 27 0x1 0x0>; /* PD27 periph A AD7 */ | |
449 | }; | |
450 | pinctrl_adc0_ad8: adc0_ad8 { | |
451 | atmel,pins = | |
452 | <3 28 0x1 0x0>; /* PD28 periph A AD8 */ | |
453 | }; | |
454 | pinctrl_adc0_ad9: adc0_ad9 { | |
455 | atmel,pins = | |
456 | <3 29 0x1 0x0>; /* PD29 periph A AD9 */ | |
457 | }; | |
458 | pinctrl_adc0_ad10: adc0_ad10 { | |
459 | atmel,pins = | |
460 | <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ | |
461 | }; | |
462 | pinctrl_adc0_ad11: adc0_ad11 { | |
463 | atmel,pins = | |
464 | <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ | |
465 | }; | |
466 | }; | |
467 | ||
468 | can0 { | |
469 | pinctrl_can0_rx_tx: can0_rx_tx { | |
470 | atmel,pins = | |
471 | <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ | |
472 | 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ | |
473 | }; | |
474 | }; | |
475 | ||
476 | can1 { | |
477 | pinctrl_can1_rx_tx: can1_rx_tx { | |
478 | atmel,pins = | |
479 | <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ | |
480 | 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ | |
481 | }; | |
482 | }; | |
483 | ||
484 | dbgu { | |
485 | pinctrl_dbgu: dbgu-0 { | |
486 | atmel,pins = | |
487 | <1 30 0x1 0x0 /* PB30 periph A */ | |
488 | 1 31 0x1 0x1>; /* PB31 periph A with pullup */ | |
489 | }; | |
490 | }; | |
491 | ||
492 | i2c0 { | |
493 | pinctrl_i2c0: i2c0-0 { | |
494 | atmel,pins = | |
495 | <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ | |
496 | 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | |
497 | }; | |
498 | }; | |
499 | ||
500 | i2c1 { | |
501 | pinctrl_i2c1: i2c1-0 { | |
502 | atmel,pins = | |
503 | <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ | |
504 | 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | |
505 | }; | |
506 | }; | |
507 | ||
508 | isi { | |
509 | pinctrl_isi: isi-0 { | |
510 | atmel,pins = | |
511 | <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ | |
512 | 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | |
513 | 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | |
514 | 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | |
515 | 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | |
516 | 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | |
517 | 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | |
518 | 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | |
519 | 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | |
520 | 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | |
521 | 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | |
522 | 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | |
523 | 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | |
524 | }; | |
525 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | |
526 | atmel,pins = | |
527 | <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ | |
528 | }; | |
529 | }; | |
530 | ||
531 | lcd { | |
532 | pinctrl_lcd: lcd-0 { | |
533 | atmel,pins = | |
534 | <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ | |
535 | 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ | |
536 | 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ | |
537 | 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ | |
538 | 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ | |
539 | 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ | |
540 | 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ | |
541 | 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ | |
542 | 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ | |
543 | 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ | |
544 | 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ | |
545 | 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ | |
546 | 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ | |
547 | 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ | |
548 | 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ | |
549 | 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ | |
550 | 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ | |
551 | 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ | |
552 | 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ | |
553 | 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ | |
554 | 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ | |
555 | 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ | |
556 | 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ | |
557 | 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ | |
558 | 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ | |
559 | 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ | |
560 | 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ | |
561 | 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ | |
562 | 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ | |
563 | 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ | |
564 | }; | |
565 | }; | |
566 | ||
567 | macb0 { | |
568 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { | |
569 | atmel,pins = | |
570 | <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ | |
571 | 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ | |
572 | 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ | |
573 | 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ | |
574 | 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ | |
575 | 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ | |
576 | 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ | |
577 | 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ | |
578 | }; | |
579 | pinctrl_macb0_data_gmii: macb0_data_gmii { | |
580 | atmel,pins = | |
581 | <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ | |
582 | 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ | |
583 | 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ | |
584 | 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ | |
585 | 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ | |
586 | 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ | |
587 | 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ | |
588 | 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ | |
589 | }; | |
590 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { | |
591 | atmel,pins = | |
592 | <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ | |
593 | 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | |
594 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | |
595 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | |
596 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | |
597 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | |
598 | 1 18 0x1 0x0>; /* PB18 periph A G125CK */ | |
599 | }; | |
600 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { | |
601 | atmel,pins = | |
602 | <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | |
603 | 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ | |
604 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | |
605 | 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ | |
606 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | |
607 | 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ | |
608 | 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ | |
609 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | |
610 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | |
611 | 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ | |
612 | }; | |
613 | ||
614 | }; | |
615 | ||
616 | macb1 { | |
617 | pinctrl_macb1_rmii: macb1_rmii-0 { | |
618 | atmel,pins = | |
619 | <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ | |
620 | 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ | |
621 | 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ | |
622 | 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ | |
623 | 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ | |
624 | 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ | |
625 | 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ | |
626 | 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ | |
627 | 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ | |
628 | 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ | |
629 | }; | |
630 | }; | |
631 | ||
632 | mmc0 { | |
633 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | |
634 | atmel,pins = | |
635 | <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ | |
636 | 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ | |
637 | 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ | |
638 | }; | |
639 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | |
640 | atmel,pins = | |
641 | <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ | |
642 | 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ | |
643 | 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ | |
644 | }; | |
645 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | |
646 | atmel,pins = | |
647 | <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ | |
648 | 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | |
649 | 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | |
650 | 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | |
651 | }; | |
652 | }; | |
653 | ||
654 | mmc1 { | |
655 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | |
656 | atmel,pins = | |
657 | <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ | |
658 | 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | |
659 | 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | |
660 | }; | |
661 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | |
662 | atmel,pins = | |
663 | <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ | |
664 | 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | |
665 | 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | |
666 | }; | |
667 | }; | |
668 | ||
669 | mmc2 { | |
670 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { | |
671 | atmel,pins = | |
672 | <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ | |
673 | 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ | |
674 | 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ | |
675 | }; | |
676 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { | |
677 | atmel,pins = | |
678 | <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ | |
679 | 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ | |
680 | 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ | |
681 | }; | |
682 | }; | |
683 | ||
684 | nand0 { | |
685 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | |
686 | atmel,pins = | |
687 | <4 21 0x1 0x1 /* PE21 periph A with pullup */ | |
688 | 4 22 0x1 0x1>; /* PE22 periph A with pullup */ | |
689 | }; | |
690 | }; | |
691 | ||
692 | pioA: gpio@fffff200 { | |
693 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
694 | reg = <0xfffff200 0x100>; | |
695 | interrupts = <6 4 1>; | |
696 | #gpio-cells = <2>; | |
697 | gpio-controller; | |
698 | interrupt-controller; | |
699 | #interrupt-cells = <2>; | |
700 | }; | |
701 | ||
702 | pioB: gpio@fffff400 { | |
703 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
704 | reg = <0xfffff400 0x100>; | |
705 | interrupts = <7 4 1>; | |
706 | #gpio-cells = <2>; | |
707 | gpio-controller; | |
708 | interrupt-controller; | |
709 | #interrupt-cells = <2>; | |
710 | }; | |
711 | ||
712 | pioC: gpio@fffff600 { | |
713 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
714 | reg = <0xfffff600 0x100>; | |
715 | interrupts = <8 4 1>; | |
716 | #gpio-cells = <2>; | |
717 | gpio-controller; | |
718 | interrupt-controller; | |
719 | #interrupt-cells = <2>; | |
720 | }; | |
721 | ||
722 | pioD: gpio@fffff800 { | |
723 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
724 | reg = <0xfffff800 0x100>; | |
725 | interrupts = <9 4 1>; | |
726 | #gpio-cells = <2>; | |
727 | gpio-controller; | |
728 | interrupt-controller; | |
729 | #interrupt-cells = <2>; | |
730 | }; | |
731 | ||
732 | pioE: gpio@fffffa00 { | |
733 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
734 | reg = <0xfffffa00 0x100>; | |
735 | interrupts = <10 4 1>; | |
736 | #gpio-cells = <2>; | |
737 | gpio-controller; | |
738 | interrupt-controller; | |
739 | #interrupt-cells = <2>; | |
740 | }; | |
741 | ||
742 | spi0 { | |
743 | pinctrl_spi0: spi0-0 { | |
744 | atmel,pins = | |
745 | <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ | |
746 | 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ | |
747 | 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ | |
748 | 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ | |
749 | }; | |
750 | }; | |
751 | ||
752 | spi1 { | |
753 | pinctrl_spi1: spi1-0 { | |
754 | atmel,pins = | |
755 | <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ | |
756 | 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ | |
757 | 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ | |
758 | 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ | |
759 | }; | |
760 | }; | |
761 | ||
762 | ssc0 { | |
763 | pinctrl_ssc0_tx: ssc0_tx { | |
764 | atmel,pins = | |
765 | <2 16 0x1 0x0 /* PC16 periph A TK0 */ | |
766 | 2 17 0x1 0x0 /* PC17 periph A TF0 */ | |
767 | 2 18 0x1 0x0>; /* PC18 periph A TD0 */ | |
768 | }; | |
769 | ||
770 | pinctrl_ssc0_rx: ssc0_rx { | |
771 | atmel,pins = | |
772 | <2 19 0x1 0x0 /* PC19 periph A RK0 */ | |
773 | 2 20 0x1 0x0 /* PC20 periph A RF0 */ | |
774 | 2 21 0x1 0x0>; /* PC21 periph A RD0 */ | |
775 | }; | |
776 | }; | |
777 | ||
778 | ssc1 { | |
779 | pinctrl_ssc1_tx: ssc1_tx { | |
780 | atmel,pins = | |
781 | <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ | |
782 | 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ | |
783 | 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ | |
784 | }; | |
785 | ||
786 | pinctrl_ssc1_rx: ssc1_rx { | |
787 | atmel,pins = | |
788 | <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ | |
789 | 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ | |
790 | 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ | |
791 | }; | |
792 | }; | |
793 | ||
794 | uart0 { | |
795 | pinctrl_uart0: uart0-0 { | |
796 | atmel,pins = | |
797 | <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ | |
798 | 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ | |
799 | }; | |
800 | }; | |
801 | ||
802 | uart1 { | |
803 | pinctrl_uart1: uart1-0 { | |
804 | atmel,pins = | |
805 | <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ | |
806 | 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ | |
807 | }; | |
808 | }; | |
809 | ||
810 | usart0 { | |
811 | pinctrl_usart0: usart0-0 { | |
812 | atmel,pins = | |
813 | <3 17 0x1 0x0 /* PD17 periph A */ | |
814 | 3 18 0x1 0x1>; /* PD18 periph A with pullup */ | |
815 | }; | |
816 | ||
817 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | |
818 | atmel,pins = | |
819 | <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ | |
820 | 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | |
821 | }; | |
822 | }; | |
823 | ||
824 | usart1 { | |
825 | pinctrl_usart1: usart1-0 { | |
826 | atmel,pins = | |
827 | <1 28 0x1 0x0 /* PB28 periph A */ | |
828 | 1 29 0x1 0x1>; /* PB29 periph A with pullup */ | |
829 | }; | |
830 | ||
831 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | |
832 | atmel,pins = | |
833 | <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ | |
834 | 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ | |
835 | }; | |
836 | }; | |
837 | ||
838 | usart2 { | |
839 | pinctrl_usart2: usart2-0 { | |
840 | atmel,pins = | |
841 | <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ | |
842 | 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ | |
843 | }; | |
844 | ||
845 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | |
846 | atmel,pins = | |
847 | <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ | |
848 | 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ | |
849 | }; | |
850 | }; | |
851 | ||
852 | usart3 { | |
853 | pinctrl_usart3: usart3-0 { | |
854 | atmel,pins = | |
855 | <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ | |
856 | 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ | |
857 | }; | |
858 | ||
859 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | |
860 | atmel,pins = | |
861 | <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ | |
862 | 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ | |
863 | }; | |
864 | }; | |
865 | }; | |
866 | ||
867 | pmc: pmc@fffffc00 { | |
868 | compatible = "atmel,at91rm9200-pmc"; | |
869 | reg = <0xfffffc00 0x120>; | |
870 | }; | |
871 | ||
872 | rstc@fffffe00 { | |
873 | compatible = "atmel,at91sam9g45-rstc"; | |
874 | reg = <0xfffffe00 0x10>; | |
875 | }; | |
876 | ||
877 | pit: timer@fffffe30 { | |
878 | compatible = "atmel,at91sam9260-pit"; | |
879 | reg = <0xfffffe30 0xf>; | |
880 | interrupts = <3 4 5>; | |
881 | }; | |
882 | ||
883 | watchdog@fffffe40 { | |
884 | compatible = "atmel,at91sam9260-wdt"; | |
885 | reg = <0xfffffe40 0x10>; | |
886 | status = "disabled"; | |
887 | }; | |
888 | ||
889 | rtc@fffffeb0 { | |
890 | compatible = "atmel,at91rm9200-rtc"; | |
891 | reg = <0xfffffeb0 0x30>; | |
892 | interrupts = <1 4 7>; | |
893 | }; | |
894 | }; | |
895 | ||
896 | usb0: gadget@00500000 { | |
897 | #address-cells = <1>; | |
898 | #size-cells = <0>; | |
899 | compatible = "atmel,at91sam9rl-udc"; | |
900 | reg = <0x00500000 0x100000 | |
901 | 0xf8030000 0x4000>; | |
902 | interrupts = <33 4 2>; | |
903 | status = "disabled"; | |
904 | ||
905 | ep0 { | |
906 | reg = <0>; | |
907 | atmel,fifo-size = <64>; | |
908 | atmel,nb-banks = <1>; | |
909 | }; | |
910 | ||
911 | ep1 { | |
912 | reg = <1>; | |
913 | atmel,fifo-size = <1024>; | |
914 | atmel,nb-banks = <3>; | |
915 | atmel,can-dma; | |
916 | atmel,can-isoc; | |
917 | }; | |
918 | ||
919 | ep2 { | |
920 | reg = <2>; | |
921 | atmel,fifo-size = <1024>; | |
922 | atmel,nb-banks = <3>; | |
923 | atmel,can-dma; | |
924 | atmel,can-isoc; | |
925 | }; | |
926 | ||
927 | ep3 { | |
928 | reg = <3>; | |
929 | atmel,fifo-size = <1024>; | |
930 | atmel,nb-banks = <2>; | |
931 | atmel,can-dma; | |
932 | }; | |
933 | ||
934 | ep4 { | |
935 | reg = <4>; | |
936 | atmel,fifo-size = <1024>; | |
937 | atmel,nb-banks = <2>; | |
938 | atmel,can-dma; | |
939 | }; | |
940 | ||
941 | ep5 { | |
942 | reg = <5>; | |
943 | atmel,fifo-size = <1024>; | |
944 | atmel,nb-banks = <2>; | |
945 | atmel,can-dma; | |
946 | }; | |
947 | ||
948 | ep6 { | |
949 | reg = <6>; | |
950 | atmel,fifo-size = <1024>; | |
951 | atmel,nb-banks = <2>; | |
952 | atmel,can-dma; | |
953 | }; | |
954 | ||
955 | ep7 { | |
956 | reg = <7>; | |
957 | atmel,fifo-size = <1024>; | |
958 | atmel,nb-banks = <2>; | |
959 | atmel,can-dma; | |
960 | }; | |
961 | ||
962 | ep8 { | |
963 | reg = <8>; | |
964 | atmel,fifo-size = <1024>; | |
965 | atmel,nb-banks = <2>; | |
966 | }; | |
967 | ||
968 | ep9 { | |
969 | reg = <9>; | |
970 | atmel,fifo-size = <1024>; | |
971 | atmel,nb-banks = <2>; | |
972 | }; | |
973 | ||
974 | ep10 { | |
975 | reg = <10>; | |
976 | atmel,fifo-size = <1024>; | |
977 | atmel,nb-banks = <2>; | |
978 | }; | |
979 | ||
980 | ep11 { | |
981 | reg = <11>; | |
982 | atmel,fifo-size = <1024>; | |
983 | atmel,nb-banks = <2>; | |
984 | }; | |
985 | ||
986 | ep12 { | |
987 | reg = <12>; | |
988 | atmel,fifo-size = <1024>; | |
989 | atmel,nb-banks = <2>; | |
990 | }; | |
991 | ||
992 | ep13 { | |
993 | reg = <13>; | |
994 | atmel,fifo-size = <1024>; | |
995 | atmel,nb-banks = <2>; | |
996 | }; | |
997 | ||
998 | ep14 { | |
999 | reg = <14>; | |
1000 | atmel,fifo-size = <1024>; | |
1001 | atmel,nb-banks = <2>; | |
1002 | }; | |
1003 | ||
1004 | ep15 { | |
1005 | reg = <15>; | |
1006 | atmel,fifo-size = <1024>; | |
1007 | atmel,nb-banks = <2>; | |
1008 | }; | |
1009 | }; | |
1010 | ||
1011 | usb1: ohci@00600000 { | |
1012 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
1013 | reg = <0x00600000 0x100000>; | |
1014 | interrupts = <32 4 2>; | |
1015 | status = "disabled"; | |
1016 | }; | |
1017 | ||
1018 | usb2: ehci@00700000 { | |
1019 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
1020 | reg = <0x00700000 0x100000>; | |
1021 | interrupts = <32 4 2>; | |
1022 | status = "disabled"; | |
1023 | }; | |
1024 | ||
1025 | nand0: nand@60000000 { | |
1026 | compatible = "atmel,at91rm9200-nand"; | |
1027 | #address-cells = <1>; | |
1028 | #size-cells = <1>; | |
1029 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ | |
1030 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | |
1031 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | |
1032 | 0x00100000 0x00100000 /* ROM code */ | |
1033 | 0x70000000 0x10000000 /* NFC Command Registers */ | |
1034 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | |
1035 | 0x00200000 0x00100000 /* NFC SRAM banks */ | |
1036 | >; | |
1037 | interrupts = <5 4 6>; | |
1038 | atmel,nand-addr-offset = <21>; | |
1039 | atmel,nand-cmd-offset = <22>; | |
1040 | pinctrl-names = "default"; | |
1041 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | |
1042 | atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; | |
1043 | status = "disabled"; | |
1044 | }; | |
1045 | }; | |
1046 | }; |