]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/arm/boot/dts/sama5d3.dtsi
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: at91/dt: ethernut5: use at91sam9xe.dtsi
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
35d35aae 16#include <dt-bindings/clock/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
334394c0
AB		 61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
4753219d 67
334394c0
AB		 68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
4753219d 73
d2e8190b
BB		 74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <20000000>;
78 };
79 };
80
f04660e4
AB		 81 sram: sram@00300000 {
82 compatible = "mmio-sram";
83 reg = <0x00300000 0x20000>;
84 };
85
655ff266
LD		 86 ahb {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 apb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges;
97
98 mmc0: mmc@f0000000 {
99 compatible = "atmel,hsmci";
100 reg = <0xf0000000 0x600>;
5e8b3bc3 101 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 103 dma-names = "rxtx";
655ff266
LD		 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
106 status = "disabled";
107 #address-cells = <1>;
108 #size-cells = <0>;
d2e8190b
BB		 109 clocks = <&mci0_clk>;
110 clock-names = "mci_clk";
655ff266
LD		 111 };
112
113 spi0: spi@f0004000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
b7ef678e 116 compatible = "atmel,at91rm9200-spi";
655ff266 117 reg = <0xf0004000 0x100>;
5e8b3bc3 118 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 119 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
120 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
121 dma-names = "tx", "rx";
655ff266
LD		 122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 124 clocks = <&spi0_clk>;
125 clock-names = "spi_clk";
655ff266
LD		 126 status = "disabled";
127 };
128
129 ssc0: ssc@f0008000 {
130 compatible = "atmel,at91sam9g45-ssc";
131 reg = <0xf0008000 0x4000>;
5e8b3bc3 132 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 133 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
134 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
135 dma-names = "tx", "rx";
655ff266
LD		 136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 138 clocks = <&ssc0_clk>;
139 clock-names = "pclk";
655ff266
LD		 140 status = "disabled";
141 };
142
655ff266
LD		 143 tcb0: timer@f0010000 {
144 compatible = "atmel,at91sam9x5-tcb";
145 reg = <0xf0010000 0x100>;
5e8b3bc3 146 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 147 clocks = <&tcb0_clk>;
148 clock-names = "t0_clk";
655ff266
LD		 149 };
150
151 i2c0: i2c@f0014000 {
152 compatible = "atmel,at91sam9x5-i2c";
153 reg = <0xf0014000 0x4000>;
5e8b3bc3 154 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 155 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
156 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 157 dma-names = "tx", "rx";
655ff266
LD		 158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
d2e8190b 162 clocks = <&twi0_clk>;
655ff266
LD		 163 status = "disabled";
164 };
165
166 i2c1: i2c@f0018000 {
167 compatible = "atmel,at91sam9x5-i2c";
168 reg = <0xf0018000 0x4000>;
5e8b3bc3 169 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 170 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
171 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 172 dma-names = "tx", "rx";
655ff266
LD		 173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
175 #address-cells = <1>;
176 #size-cells = <0>;
d2e8190b 177 clocks = <&twi1_clk>;
655ff266
LD		 178 status = "disabled";
179 };
180
181 usart0: serial@f001c000 {
182 compatible = "atmel,at91sam9260-usart";
183 reg = <0xf001c000 0x100>;
5e8b3bc3 184 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 185 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
186 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
187 dma-names = "tx", "rx";
655ff266
LD		 188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 190 clocks = <&usart0_clk>;
191 clock-names = "usart";
655ff266
LD		 192 status = "disabled";
193 };
194
195 usart1: serial@f0020000 {
196 compatible = "atmel,at91sam9260-usart";
197 reg = <0xf0020000 0x100>;
5e8b3bc3 198 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 199 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
200 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
201 dma-names = "tx", "rx";
655ff266
LD		 202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 204 clocks = <&usart1_clk>;
205 clock-names = "usart";
655ff266
LD		 206 status = "disabled";
207 };
208
f3ab0527
BS		 209 pwm0: pwm@f002c000 {
210 compatible = "atmel,sama5d3-pwm";
211 reg = <0xf002c000 0x300>;
212 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
213 #pwm-cells = <3>;
214 clocks = <&pwm_clk>;
215 status = "disabled";
216 };
655ff266 217
655ff266
LD		 218 isi: isi@f0034000 {
219 compatible = "atmel,at91sam9g45-isi";
220 reg = <0xf0034000 0x4000>;
5e8b3bc3 221 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 222 status = "disabled";
223 };
224
6ced9f4a
AB		 225 sfr: sfr@f0038000 {
226 compatible = "atmel,sama5d3-sfr", "syscon";
227 reg = <0xf0038000 0x60>;
228 };
229
655ff266
LD		 230 mmc1: mmc@f8000000 {
231 compatible = "atmel,hsmci";
232 reg = <0xf8000000 0x600>;
5e8b3bc3 233 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 234 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 235 dma-names = "rxtx";
655ff266
LD		 236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
238 status = "disabled";
239 #address-cells = <1>;
240 #size-cells = <0>;
d2e8190b
BB		 241 clocks = <&mci1_clk>;
242 clock-names = "mci_clk";
655ff266
LD		 243 };
244
655ff266
LD		 245 spi1: spi@f8008000 {
246 #address-cells = <1>;
247 #size-cells = <0>;
b7ef678e 248 compatible = "atmel,at91rm9200-spi";
655ff266 249 reg = <0xf8008000 0x100>;
5e8b3bc3 250 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 251 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
252 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
253 dma-names = "tx", "rx";
655ff266
LD		 254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 256 clocks = <&spi1_clk>;
257 clock-names = "spi_clk";
655ff266
LD		 258 status = "disabled";
259 };
260
261 ssc1: ssc@f800c000 {
262 compatible = "atmel,at91sam9g45-ssc";
263 reg = <0xf800c000 0x4000>;
5e8b3bc3 264 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 265 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
266 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
267 dma-names = "tx", "rx";
655ff266
LD		 268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 270 clocks = <&ssc1_clk>;
271 clock-names = "pclk";
655ff266
LD		 272 status = "disabled";
273 };
274
655ff266 275 adc0: adc@f8018000 {
b3b84dec
AB		 276 #address-cells = <1>;
277 #size-cells = <0>;
9879b96d 278 compatible = "atmel,at91sam9x5-adc";
655ff266 279 reg = <0xf8018000 0x100>;
5e8b3bc3 280 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 281 pinctrl-names = "default";
282 pinctrl-0 = <
283 &pinctrl_adc0_adtrg
284 &pinctrl_adc0_ad0
285 &pinctrl_adc0_ad1
286 &pinctrl_adc0_ad2
287 &pinctrl_adc0_ad3
288 &pinctrl_adc0_ad4
289 &pinctrl_adc0_ad5
290 &pinctrl_adc0_ad6
291 &pinctrl_adc0_ad7
292 &pinctrl_adc0_ad8
293 &pinctrl_adc0_ad9
294 &pinctrl_adc0_ad10
295 &pinctrl_adc0_ad11
296 >;
d2e8190b
BB		 297 clocks = <&adc_clk>,
298 <&adc_op_clk>;
299 clock-names = "adc_clk", "adc_op_clk";
655ff266 300 atmel,adc-channels-used = <0xfff>;
655ff266 301 atmel,adc-startup-time = <40>;
b3b84dec 302 atmel,adc-use-external-triggers;
655ff266
LD		 303 atmel,adc-vref = <3000>;
304 atmel,adc-res = <10 12>;
305 atmel,adc-res-names = "lowres", "highres";
306 status = "disabled";
307
308 trigger@0 {
b3b84dec 309 reg = <0>;
655ff266
LD		 310 trigger-name = "external-rising";
311 trigger-value = <0x1>;
312 trigger-external;
313 };
314 trigger@1 {
b3b84dec 315 reg = <1>;
655ff266
LD		 316 trigger-name = "external-falling";
317 trigger-value = <0x2>;
318 trigger-external;
319 };
320 trigger@2 {
b3b84dec 321 reg = <2>;
655ff266
LD		 322 trigger-name = "external-any";
323 trigger-value = <0x3>;
324 trigger-external;
325 };
326 trigger@3 {
b3b84dec 327 reg = <3>;
655ff266
LD		 328 trigger-name = "continuous";
329 trigger-value = <0x6>;
330 };
331 };
332
655ff266
LD		 333 i2c2: i2c@f801c000 {
334 compatible = "atmel,at91sam9x5-i2c";
335 reg = <0xf801c000 0x4000>;
5e8b3bc3 336 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 337 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
338 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 339 dma-names = "tx", "rx";
557844ec
NF		 340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 342 #address-cells = <1>;
343 #size-cells = <0>;
d2e8190b 344 clocks = <&twi2_clk>;
655ff266
LD		 345 status = "disabled";
346 };
347
348 usart2: serial@f8020000 {
349 compatible = "atmel,at91sam9260-usart";
350 reg = <0xf8020000 0x100>;
5e8b3bc3 351 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 352 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
353 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
354 dma-names = "tx", "rx";
655ff266
LD		 355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 357 clocks = <&usart2_clk>;
358 clock-names = "usart";
655ff266
LD		 359 status = "disabled";
360 };
361
362 usart3: serial@f8024000 {
363 compatible = "atmel,at91sam9260-usart";
364 reg = <0xf8024000 0x100>;
5e8b3bc3 365 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 366 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
367 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
368 dma-names = "tx", "rx";
655ff266
LD		 369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 371 clocks = <&usart3_clk>;
372 clock-names = "usart";
655ff266
LD		 373 status = "disabled";
374 };
375
655ff266 376 sha@f8034000 {
c76f266d 377 compatible = "atmel,at91sam9g46-sha";
655ff266 378 reg = <0xf8034000 0x100>;
5e8b3bc3 379 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 380 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
381 dma-names = "tx";
4df4f446
BB		 382 clocks = <&sha_clk>;
383 clock-names = "sha_clk";
655ff266
LD		 384 };
385
386 aes@f8038000 {
c76f266d 387 compatible = "atmel,at91sam9g46-aes";
655ff266 388 reg = <0xf8038000 0x100>;
07f7d503 389 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 390 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
391 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
392 dma-names = "tx", "rx";
f68cd356
BB		 393 clocks = <&aes_clk>;
394 clock-names = "aes_clk";
655ff266
LD		 395 };
396
397 tdes@f803c000 {
c76f266d 398 compatible = "atmel,at91sam9g46-tdes";
655ff266 399 reg = <0xf803c000 0x100>;
5e8b3bc3 400 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 401 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
402 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
403 dma-names = "tx", "rx";
45e5c2cb
BB		 404 clocks = <&tdes_clk>;
405 clock-names = "tdes_clk";
655ff266
LD		 406 };
407
408 dma0: dma-controller@ffffe600 {
409 compatible = "atmel,at91sam9g45-dma";
410 reg = <0xffffe600 0x200>;
5e8b3bc3 411 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 412 #dma-cells = <2>;
d2e8190b
BB		 413 clocks = <&dma0_clk>;
414 clock-names = "dma_clk";
655ff266
LD		 415 };
416
417 dma1: dma-controller@ffffe800 {
418 compatible = "atmel,at91sam9g45-dma";
419 reg = <0xffffe800 0x200>;
5e8b3bc3 420 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 421 #dma-cells = <2>;
d2e8190b
BB		 422 clocks = <&dma1_clk>;
423 clock-names = "dma_clk";
655ff266
LD		 424 };
425
426 ramc0: ramc@ffffea00 {
063de897 427 compatible = "atmel,sama5d3-ddramc";
655ff266 428 reg = <0xffffea00 0x200>;
063de897
AB		 429 clocks = <&ddrck>, <&mpddr_clk>;
430 clock-names = "ddrck", "mpddr";
655ff266
LD		 431 };
432
433 dbgu: serial@ffffee00 {
434 compatible = "atmel,at91sam9260-usart";
435 reg = <0xffffee00 0x200>;
5e8b3bc3 436 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
d24cd783
LD		 437 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
438 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
439 dma-names = "tx", "rx";
655ff266
LD		 440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 442 clocks = <&dbgu_clk>;
443 clock-names = "usart";
655ff266
LD		 444 status = "disabled";
445 };
446
447 aic: interrupt-controller@fffff000 {
448 #interrupt-cells = <3>;
449 compatible = "atmel,sama5d3-aic";
450 interrupt-controller;
451 reg = <0xfffff000 0x200>;
452 atmel,external-irqs = <47>;
453 };
454
455 pinctrl@fffff200 {
456 #address-cells = <1>;
457 #size-cells = <1>;
e0065cf7 458 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
655ff266
LD		 459 ranges = <0xfffff200 0xfffff200 0xa00>;
460 atmel,mux-mask = <
461 /* A B C */
462 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
463 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
464 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
465 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
466 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
467 >;
468
469 /* shared pinctrl settings */
470 adc0 {
471 pinctrl_adc0_adtrg: adc0_adtrg {
472 atmel,pins =
c9d0f317 473 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 474 };
475 pinctrl_adc0_ad0: adc0_ad0 {
476 atmel,pins =
c9d0f317 477 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 478 };
479 pinctrl_adc0_ad1: adc0_ad1 {
480 atmel,pins =
c9d0f317 481 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 482 };
483 pinctrl_adc0_ad2: adc0_ad2 {
484 atmel,pins =
c9d0f317 485 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 486 };
487 pinctrl_adc0_ad3: adc0_ad3 {
488 atmel,pins =
c9d0f317 489 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 490 };
491 pinctrl_adc0_ad4: adc0_ad4 {
492 atmel,pins =
c9d0f317 493 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 494 };
495 pinctrl_adc0_ad5: adc0_ad5 {
496 atmel,pins =
c9d0f317 497 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 498 };
499 pinctrl_adc0_ad6: adc0_ad6 {
500 atmel,pins =
c9d0f317 501 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 502 };
503 pinctrl_adc0_ad7: adc0_ad7 {
504 atmel,pins =
c9d0f317 505 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 506 };
507 pinctrl_adc0_ad8: adc0_ad8 {
508 atmel,pins =
c9d0f317 509 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 510 };
511 pinctrl_adc0_ad9: adc0_ad9 {
512 atmel,pins =
c9d0f317 513 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 514 };
515 pinctrl_adc0_ad10: adc0_ad10 {
516 atmel,pins =
c9d0f317 517 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 518 };
519 pinctrl_adc0_ad11: adc0_ad11 {
520 atmel,pins =
c9d0f317 521 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 522 };
523 };
524
655ff266
LD		 525 dbgu {
526 pinctrl_dbgu: dbgu-0 {
527 atmel,pins =
c9d0f317
JCPV		 528 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
529 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 530 };
531 };
532
533 i2c0 {
534 pinctrl_i2c0: i2c0-0 {
535 atmel,pins =
c9d0f317
JCPV		 536 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
537 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 538 };
539 };
540
541 i2c1 {
542 pinctrl_i2c1: i2c1-0 {
543 atmel,pins =
c9d0f317
JCPV		 544 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
545 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 546 };
547 };
548
557844ec
NF		 549 i2c2 {
550 pinctrl_i2c2: i2c2-0 {
551 atmel,pins =
552 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
553 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
554 };
555 };
556
655ff266
LD		 557 isi {
558 pinctrl_isi: isi-0 {
559 atmel,pins =
c9d0f317
JCPV		 560 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
561 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
562 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
563 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
564 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
565 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
566 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
567 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
568 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
569 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
570 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
571 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
572 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 573 };
574 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
575 atmel,pins =
c9d0f317 576 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 577 };
578 };
579
655ff266
LD		 580 mmc0 {
581 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
582 atmel,pins =
c9d0f317
JCPV		 583 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
584 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
585 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 586 };
587 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
588 atmel,pins =
c9d0f317
JCPV		 589 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
590 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
591 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 592 };
593 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
594 atmel,pins =
c9d0f317
JCPV		 595 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
596 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
597 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
598 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 599 };
600 };
601
602 mmc1 {
603 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
604 atmel,pins =
c9d0f317
JCPV		 605 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
606 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
607 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 608 };
609 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
610 atmel,pins =
c9d0f317
JCPV		 611 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
612 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
613 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 614 };
615 };
616
655ff266
LD		 617 nand0 {
618 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
619 atmel,pins =
c9d0f317
JCPV		 620 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
621 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 622 };
623 };
624
5eefd5f4
NF		 625 pwm0 {
626 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
627 atmel,pins =
628 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
629 };
630 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
631 atmel,pins =
632 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
633 };
634 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
635 atmel,pins =
636 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
637 };
638 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
639 atmel,pins =
640 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
641 };
642
643 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
644 atmel,pins =
645 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
646 };
647 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
648 atmel,pins =
649 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
650 };
651 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
652 atmel,pins =
653 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
654 };
655 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
656 atmel,pins =
657 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
658 };
659 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
660 atmel,pins =
661 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
662 };
663 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
664 atmel,pins =
665 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
666 };
667
668 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
669 atmel,pins =
670 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
671 };
672 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
673 atmel,pins =
674 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
675 };
676 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
677 atmel,pins =
678 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
679 };
680 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
681 atmel,pins =
682 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
683 };
684
685 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
686 atmel,pins =
687 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
688 };
689 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
690 atmel,pins =
691 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
692 };
693 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
694 atmel,pins =
695 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
696 };
697 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
698 atmel,pins =
699 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
700 };
701 };
702
655ff266
LD		 703 spi0 {
704 pinctrl_spi0: spi0-0 {
705 atmel,pins =
c9d0f317
JCPV		 706 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
707 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
708 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 709 };
710 };
711
712 spi1 {
713 pinctrl_spi1: spi1-0 {
714 atmel,pins =
c9d0f317
JCPV		 715 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
716 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
717 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 718 };
719 };
720
721 ssc0 {
722 pinctrl_ssc0_tx: ssc0_tx {
723 atmel,pins =
c9d0f317
JCPV		 724 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
725 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
726 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 727 };
728
729 pinctrl_ssc0_rx: ssc0_rx {
730 atmel,pins =
c9d0f317
JCPV		 731 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
732 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
733 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 734 };
735 };
736
737 ssc1 {
738 pinctrl_ssc1_tx: ssc1_tx {
739 atmel,pins =
c9d0f317
JCPV		 740 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
741 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
742 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 743 };
744
745 pinctrl_ssc1_rx: ssc1_rx {
746 atmel,pins =
c9d0f317
JCPV		 747 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
748 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
749 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 750 };
751 };
752
655ff266
LD		 753 usart0 {
754 pinctrl_usart0: usart0-0 {
755 atmel,pins =
c9d0f317
JCPV		 756 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
757 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 758 };
759
760 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
761 atmel,pins =
c9d0f317
JCPV		 762 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
763 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 764 };
765 };
766
767 usart1 {
768 pinctrl_usart1: usart1-0 {
769 atmel,pins =
c9d0f317
JCPV		 770 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
771 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 772 };
773
774 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
775 atmel,pins =
c9d0f317
JCPV		 776 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
777 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 778 };
779 };
780
781 usart2 {
782 pinctrl_usart2: usart2-0 {
783 atmel,pins =
c9d0f317
JCPV		 784 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
785 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 786 };
787
788 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
789 atmel,pins =
c9d0f317
JCPV		 790 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
791 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 792 };
793 };
794
795 usart3 {
796 pinctrl_usart3: usart3-0 {
797 atmel,pins =
c9d0f317
JCPV		 798 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
799 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 800 };
801
802 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
803 atmel,pins =
c9d0f317
JCPV		 804 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
805 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 806 };
807 };
c9d0f317
JCPV		 808
809
810 pioA: gpio@fffff200 {
811 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
812 reg = <0xfffff200 0x100>;
5e8b3bc3 813 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 814 #gpio-cells = <2>;
815 gpio-controller;
816 interrupt-controller;
817 #interrupt-cells = <2>;
d2e8190b 818 clocks = <&pioA_clk>;
c9d0f317
JCPV		 819 };
820
821 pioB: gpio@fffff400 {
822 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
823 reg = <0xfffff400 0x100>;
5e8b3bc3 824 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 825 #gpio-cells = <2>;
826 gpio-controller;
827 interrupt-controller;
828 #interrupt-cells = <2>;
d2e8190b 829 clocks = <&pioB_clk>;
c9d0f317
JCPV		 830 };
831
832 pioC: gpio@fffff600 {
833 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
834 reg = <0xfffff600 0x100>;
5e8b3bc3 835 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 836 #gpio-cells = <2>;
837 gpio-controller;
838 interrupt-controller;
839 #interrupt-cells = <2>;
d2e8190b 840 clocks = <&pioC_clk>;
c9d0f317
JCPV		 841 };
842
843 pioD: gpio@fffff800 {
844 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
845 reg = <0xfffff800 0x100>;
5e8b3bc3 846 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 847 #gpio-cells = <2>;
848 gpio-controller;
849 interrupt-controller;
850 #interrupt-cells = <2>;
d2e8190b 851 clocks = <&pioD_clk>;
c9d0f317
JCPV		 852 };
853
854 pioE: gpio@fffffa00 {
855 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
856 reg = <0xfffffa00 0x100>;
5e8b3bc3 857 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 858 #gpio-cells = <2>;
859 gpio-controller;
860 interrupt-controller;
861 #interrupt-cells = <2>;
d2e8190b 862 clocks = <&pioE_clk>;
c9d0f317 863 };
655ff266
LD		 864 };
865
866 pmc: pmc@fffffc00 {
d2e8190b 867 compatible = "atmel,sama5d3-pmc";
655ff266 868 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 869 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
870 interrupt-controller;
871 #address-cells = <1>;
872 #size-cells = <0>;
873 #interrupt-cells = <1>;
874
4753219d
BB		 875 main_rc_osc: main_rc_osc {
876 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
d2e8190b 877 #clock-cells = <0>;
4753219d
BB		 878 interrupt-parent = <&pmc>;
879 interrupts = <AT91_PMC_MOSCRCS>;
880 clock-frequency = <12000000>;
881 clock-accuracy = <50000000>;
d2e8190b
BB		 882 };
883
4753219d
BB		 884 main_osc: main_osc {
885 compatible = "atmel,at91rm9200-clk-main-osc";
d2e8190b
BB		 886 #clock-cells = <0>;
887 interrupt-parent = <&pmc>;
888 interrupts = <AT91_PMC_MOSCS>;
4753219d
BB		 889 clocks = <&main_xtal>;
890 };
891
892 main: mainck {
893 compatible = "atmel,at91sam9x5-clk-main";
894 #clock-cells = <0>;
895 interrupt-parent = <&pmc>;
896 interrupts = <AT91_PMC_MOSCSELS>;
897 clocks = <&main_rc_osc &main_osc>;
d2e8190b
BB		 898 };
899
900 plla: pllack {
901 compatible = "atmel,sama5d3-clk-pll";
902 #clock-cells = <0>;
903 interrupt-parent = <&pmc>;
904 interrupts = <AT91_PMC_LOCKA>;
905 clocks = <&main>;
906 reg = <0>;
907 atmel,clk-input-range = <8000000 50000000>;
908 #atmel,pll-clk-output-range-cells = <4>;
909 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
910 };
911
912 plladiv: plladivck {
913 compatible = "atmel,at91sam9x5-clk-plldiv";
914 #clock-cells = <0>;
915 clocks = <&plla>;
916 };
917
918 utmi: utmick {
919 compatible = "atmel,at91sam9x5-clk-utmi";
920 #clock-cells = <0>;
921 interrupt-parent = <&pmc>;
922 interrupts = <AT91_PMC_LOCKU>;
923 clocks = <&main>;
924 };
925
926 mck: masterck {
927 compatible = "atmel,at91sam9x5-clk-master";
928 #clock-cells = <0>;
929 interrupt-parent = <&pmc>;
930 interrupts = <AT91_PMC_MCKRDY>;
931 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
932 atmel,clk-output-range = <0 166000000>;
933 atmel,clk-divisors = <1 2 4 3>;
934 };
935
936 usb: usbck {
937 compatible = "atmel,at91sam9x5-clk-usb";
938 #clock-cells = <0>;
939 clocks = <&plladiv>, <&utmi>;
940 };
941
942 prog: progck {
943 compatible = "atmel,at91sam9x5-clk-programmable";
944 #address-cells = <1>;
945 #size-cells = <0>;
946 interrupt-parent = <&pmc>;
947 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
948
949 prog0: prog0 {
950 #clock-cells = <0>;
951 reg = <0>;
952 interrupts = <AT91_PMC_PCKRDY(0)>;
953 };
954
955 prog1: prog1 {
956 #clock-cells = <0>;
957 reg = <1>;
958 interrupts = <AT91_PMC_PCKRDY(1)>;
959 };
960
961 prog2: prog2 {
962 #clock-cells = <0>;
963 reg = <2>;
964 interrupts = <AT91_PMC_PCKRDY(2)>;
965 };
966 };
967
968 smd: smdclk {
969 compatible = "atmel,at91sam9x5-clk-smd";
970 #clock-cells = <0>;
971 clocks = <&plladiv>, <&utmi>;
972 };
973
974 systemck {
975 compatible = "atmel,at91rm9200-clk-system";
976 #address-cells = <1>;
977 #size-cells = <0>;
978
979 ddrck: ddrck {
980 #clock-cells = <0>;
981 reg = <2>;
982 clocks = <&mck>;
983 };
984
985 smdck: smdck {
986 #clock-cells = <0>;
987 reg = <4>;
988 clocks = <&smd>;
989 };
990
991 uhpck: uhpck {
992 #clock-cells = <0>;
993 reg = <6>;
994 clocks = <&usb>;
995 };
996
997 udpck: udpck {
998 #clock-cells = <0>;
999 reg = <7>;
1000 clocks = <&usb>;
1001 };
1002
1003 pck0: pck0 {
1004 #clock-cells = <0>;
1005 reg = <8>;
1006 clocks = <&prog0>;
1007 };
1008
1009 pck1: pck1 {
1010 #clock-cells = <0>;
1011 reg = <9>;
1012 clocks = <&prog1>;
1013 };
1014
1015 pck2: pck2 {
1016 #clock-cells = <0>;
1017 reg = <10>;
1018 clocks = <&prog2>;
1019 };
1020 };
1021
1022 periphck {
1023 compatible = "atmel,at91sam9x5-clk-peripheral";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 clocks = <&mck>;
1027
1028 dbgu_clk: dbgu_clk {
1029 #clock-cells = <0>;
1030 reg = <2>;
1031 };
1032
8a85ba20
AB		 1033 hsmc_clk: hsmc_clk {
1034 #clock-cells = <0>;
1035 reg = <5>;
1036 };
1037
d2e8190b
BB		 1038 pioA_clk: pioA_clk {
1039 #clock-cells = <0>;
1040 reg = <6>;
1041 };
1042
1043 pioB_clk: pioB_clk {
1044 #clock-cells = <0>;
1045 reg = <7>;
1046 };
1047
1048 pioC_clk: pioC_clk {
1049 #clock-cells = <0>;
1050 reg = <8>;
1051 };
1052
1053 pioD_clk: pioD_clk {
1054 #clock-cells = <0>;
1055 reg = <9>;
1056 };
1057
1058 pioE_clk: pioE_clk {
1059 #clock-cells = <0>;
1060 reg = <10>;
1061 };
1062
1063 usart0_clk: usart0_clk {
1064 #clock-cells = <0>;
1065 reg = <12>;
1066 atmel,clk-output-range = <0 66000000>;
1067 };
1068
1069 usart1_clk: usart1_clk {
1070 #clock-cells = <0>;
1071 reg = <13>;
1072 atmel,clk-output-range = <0 66000000>;
1073 };
1074
1075 usart2_clk: usart2_clk {
1076 #clock-cells = <0>;
1077 reg = <14>;
1078 atmel,clk-output-range = <0 66000000>;
1079 };
1080
1081 usart3_clk: usart3_clk {
1082 #clock-cells = <0>;
1083 reg = <15>;
1084 atmel,clk-output-range = <0 66000000>;
1085 };
1086
1087 twi0_clk: twi0_clk {
1088 reg = <18>;
1089 #clock-cells = <0>;
1090 atmel,clk-output-range = <0 16625000>;
1091 };
1092
1093 twi1_clk: twi1_clk {
1094 #clock-cells = <0>;
1095 reg = <19>;
1096 atmel,clk-output-range = <0 16625000>;
1097 };
1098
1099 twi2_clk: twi2_clk {
1100 #clock-cells = <0>;
1101 reg = <20>;
1102 atmel,clk-output-range = <0 16625000>;
1103 };
1104
1105 mci0_clk: mci0_clk {
1106 #clock-cells = <0>;
1107 reg = <21>;
1108 };
1109
1110 mci1_clk: mci1_clk {
1111 #clock-cells = <0>;
1112 reg = <22>;
1113 };
1114
1115 spi0_clk: spi0_clk {
1116 #clock-cells = <0>;
1117 reg = <24>;
1118 atmel,clk-output-range = <0 133000000>;
1119 };
1120
1121 spi1_clk: spi1_clk {
1122 #clock-cells = <0>;
1123 reg = <25>;
1124 atmel,clk-output-range = <0 133000000>;
1125 };
1126
1127 tcb0_clk: tcb0_clk {
1128 #clock-cells = <0>;
1129 reg = <26>;
1130 atmel,clk-output-range = <0 133000000>;
1131 };
1132
1133 pwm_clk: pwm_clk {
1134 #clock-cells = <0>;
1135 reg = <28>;
1136 };
1137
1138 adc_clk: adc_clk {
1139 #clock-cells = <0>;
1140 reg = <29>;
1141 atmel,clk-output-range = <0 66000000>;
1142 };
1143
1144 dma0_clk: dma0_clk {
1145 #clock-cells = <0>;
1146 reg = <30>;
1147 };
1148
1149 dma1_clk: dma1_clk {
1150 #clock-cells = <0>;
1151 reg = <31>;
1152 };
1153
1154 uhphs_clk: uhphs_clk {
1155 #clock-cells = <0>;
1156 reg = <32>;
1157 };
1158
1159 udphs_clk: udphs_clk {
1160 #clock-cells = <0>;
1161 reg = <33>;
1162 };
1163
1164 isi_clk: isi_clk {
1165 #clock-cells = <0>;
1166 reg = <37>;
1167 };
1168
1169 ssc0_clk: ssc0_clk {
1170 #clock-cells = <0>;
1171 reg = <38>;
1172 atmel,clk-output-range = <0 66000000>;
1173 };
1174
1175 ssc1_clk: ssc1_clk {
1176 #clock-cells = <0>;
1177 reg = <39>;
1178 atmel,clk-output-range = <0 66000000>;
1179 };
1180
1181 sha_clk: sha_clk {
1182 #clock-cells = <0>;
1183 reg = <42>;
1184 };
1185
1186 aes_clk: aes_clk {
1187 #clock-cells = <0>;
1188 reg = <43>;
1189 };
1190
1191 tdes_clk: tdes_clk {
1192 #clock-cells = <0>;
1193 reg = <44>;
1194 };
1195
1196 trng_clk: trng_clk {
1197 #clock-cells = <0>;
1198 reg = <45>;
1199 };
1200
1201 fuse_clk: fuse_clk {
1202 #clock-cells = <0>;
1203 reg = <48>;
1204 };
063de897
AB		 1205
1206 mpddr_clk: mpddr_clk {
1207 #clock-cells = <0>;
1208 reg = <49>;
1209 };
d2e8190b 1210 };
655ff266
LD		 1211 };
1212
1213 rstc@fffffe00 {
1214 compatible = "atmel,at91sam9g45-rstc";
1215 reg = <0xfffffe00 0x10>;
1216 };
1217
16aa7f1f
MR		 1218 shutdown-controller@fffffe10 {
1219 compatible = "atmel,at91sam9x5-shdwc";
1220 reg = <0xfffffe10 0x10>;
1221 };
1222
655ff266
LD		 1223 pit: timer@fffffe30 {
1224 compatible = "atmel,at91sam9260-pit";
1225 reg = <0xfffffe30 0xf>;
5e8b3bc3 1226 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1227 clocks = <&mck>;
655ff266
LD		 1228 };
1229
1230 watchdog@fffffe40 {
1231 compatible = "atmel,at91sam9260-wdt";
1232 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1233 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1234 atmel,watchdog-type = "hardware";
1235 atmel,reset-type = "all";
1236 atmel,dbg-halt;
1237 atmel,idle-halt;
655ff266
LD		 1238 status = "disabled";
1239 };
1240
4753219d
BB		 1241 sckc@fffffe50 {
1242 compatible = "atmel,at91sam9x5-sckc";
1243 reg = <0xfffffe50 0x4>;
1244
1245 slow_rc_osc: slow_rc_osc {
1246 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1247 #clock-cells = <0>;
1248 clock-frequency = <32768>;
1249 clock-accuracy = <50000000>;
1250 atmel,startup-time-usec = <75>;
1251 };
1252
1253 slow_osc: slow_osc {
1254 compatible = "atmel,at91sam9x5-clk-slow-osc";
1255 #clock-cells = <0>;
1256 clocks = <&slow_xtal>;
1257 atmel,startup-time-usec = <1200000>;
1258 };
1259
1260 clk32k: slowck {
1261 compatible = "atmel,at91sam9x5-clk-slow";
1262 #clock-cells = <0>;
1263 clocks = <&slow_rc_osc &slow_osc>;
1264 };
1265 };
1266
655ff266
LD		 1267 rtc@fffffeb0 {
1268 compatible = "atmel,at91rm9200-rtc";
1269 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1270 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1271 };
1272 };
1273
1274 usb0: gadget@00500000 {
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1277 compatible = "atmel,at91sam9rl-udc";
1278 reg = <0x00500000 0x100000
1279 0xf8030000 0x4000>;
5e8b3bc3 1280 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1281 clocks = <&udphs_clk>, <&utmi>;
1282 clock-names = "pclk", "hclk";
655ff266
LD		 1283 status = "disabled";
1284
1285 ep0 {
1286 reg = <0>;
1287 atmel,fifo-size = <64>;
1288 atmel,nb-banks = <1>;
1289 };
1290
1291 ep1 {
1292 reg = <1>;
1293 atmel,fifo-size = <1024>;
1294 atmel,nb-banks = <3>;
1295 atmel,can-dma;
1296 atmel,can-isoc;
1297 };
1298
1299 ep2 {
1300 reg = <2>;
1301 atmel,fifo-size = <1024>;
1302 atmel,nb-banks = <3>;
1303 atmel,can-dma;
1304 atmel,can-isoc;
1305 };
1306
1307 ep3 {
1308 reg = <3>;
1309 atmel,fifo-size = <1024>;
1310 atmel,nb-banks = <2>;
1311 atmel,can-dma;
1312 };
1313
1314 ep4 {
1315 reg = <4>;
1316 atmel,fifo-size = <1024>;
1317 atmel,nb-banks = <2>;
1318 atmel,can-dma;
1319 };
1320
1321 ep5 {
1322 reg = <5>;
1323 atmel,fifo-size = <1024>;
1324 atmel,nb-banks = <2>;
1325 atmel,can-dma;
1326 };
1327
1328 ep6 {
1329 reg = <6>;
1330 atmel,fifo-size = <1024>;
1331 atmel,nb-banks = <2>;
1332 atmel,can-dma;
1333 };
1334
1335 ep7 {
1336 reg = <7>;
1337 atmel,fifo-size = <1024>;
1338 atmel,nb-banks = <2>;
1339 atmel,can-dma;
1340 };
1341
1342 ep8 {
1343 reg = <8>;
1344 atmel,fifo-size = <1024>;
1345 atmel,nb-banks = <2>;
1346 };
1347
1348 ep9 {
1349 reg = <9>;
1350 atmel,fifo-size = <1024>;
1351 atmel,nb-banks = <2>;
1352 };
1353
1354 ep10 {
1355 reg = <10>;
1356 atmel,fifo-size = <1024>;
1357 atmel,nb-banks = <2>;
1358 };
1359
1360 ep11 {
1361 reg = <11>;
1362 atmel,fifo-size = <1024>;
1363 atmel,nb-banks = <2>;
1364 };
1365
1366 ep12 {
1367 reg = <12>;
1368 atmel,fifo-size = <1024>;
1369 atmel,nb-banks = <2>;
1370 };
1371
1372 ep13 {
1373 reg = <13>;
1374 atmel,fifo-size = <1024>;
1375 atmel,nb-banks = <2>;
1376 };
1377
1378 ep14 {
1379 reg = <14>;
1380 atmel,fifo-size = <1024>;
1381 atmel,nb-banks = <2>;
1382 };
1383
1384 ep15 {
1385 reg = <15>;
1386 atmel,fifo-size = <1024>;
1387 atmel,nb-banks = <2>;
1388 };
1389 };
1390
1391 usb1: ohci@00600000 {
1392 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1393 reg = <0x00600000 0x100000>;
5e8b3bc3 1394 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1395 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1396 <&uhpck>;
1397 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1398 status = "disabled";
1399 };
1400
1401 usb2: ehci@00700000 {
1402 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1403 reg = <0x00700000 0x100000>;
5e8b3bc3 1404 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1405 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1406 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1407 status = "disabled";
1408 };
1409
1410 nand0: nand@60000000 {
1411 compatible = "atmel,at91rm9200-nand";
1412 #address-cells = <1>;
1413 #size-cells = <1>;
8ae599ef 1414 ranges;
655ff266
LD		 1415 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1416 0xffffc070 0x00000490 /* SMC PMECC regs */
1417 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1418 0x00110000 0x00018000 /* ROM code */
655ff266 1419 >;
5e8b3bc3 1420 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1421 atmel,nand-addr-offset = <21>;
1422 atmel,nand-cmd-offset = <22>;
e8b2da6e 1423 atmel,nand-has-dma;
655ff266
LD		 1424 pinctrl-names = "default";
1425 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1426 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1427 status = "disabled";
8ae599ef
JW		 1428
1429 nfc@70000000 {
1430 compatible = "atmel,sama5d3-nfc";
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1433 reg = <
1434 0x70000000 0x10000000 /* NFC Command Registers */
1435 0xffffc000 0x00000070 /* NFC HSMC regs */
1436 0x00200000 0x00100000 /* NFC SRAM banks */
1437 >;
8a85ba20 1438 clocks = <&hsmc_clk>;
8ae599ef 1439 };
655ff266
LD		 1440 };
1441 };
1442};
ubuntu-bionic-kernel mirror