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ARM: at91: add pull-up to i2c[02] on SAMA5D3 Xplained
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
d2e8190b 16#include <dt-bindings/clk/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
d2e8190b
BB		 61 clocks {
62 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <20000000>;
66 };
67 };
68
655ff266
LD		 69 ahb {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 apb {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 mmc0: mmc@f0000000 {
82 compatible = "atmel,hsmci";
83 reg = <0xf0000000 0x600>;
5e8b3bc3 84 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 85 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 86 dma-names = "rxtx";
655ff266
LD		 87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
89 status = "disabled";
90 #address-cells = <1>;
91 #size-cells = <0>;
d2e8190b
BB		 92 clocks = <&mci0_clk>;
93 clock-names = "mci_clk";
655ff266
LD		 94 };
95
96 spi0: spi@f0004000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
b7ef678e 99 compatible = "atmel,at91rm9200-spi";
655ff266 100 reg = <0xf0004000 0x100>;
5e8b3bc3 101 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
103 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
104 dma-names = "tx", "rx";
655ff266
LD		 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 107 clocks = <&spi0_clk>;
108 clock-names = "spi_clk";
655ff266
LD		 109 status = "disabled";
110 };
111
112 ssc0: ssc@f0008000 {
113 compatible = "atmel,at91sam9g45-ssc";
114 reg = <0xf0008000 0x4000>;
5e8b3bc3 115 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 116 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
117 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
118 dma-names = "tx", "rx";
655ff266
LD		 119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 121 clocks = <&ssc0_clk>;
122 clock-names = "pclk";
655ff266
LD		 123 status = "disabled";
124 };
125
655ff266
LD		 126 tcb0: timer@f0010000 {
127 compatible = "atmel,at91sam9x5-tcb";
128 reg = <0xf0010000 0x100>;
5e8b3bc3 129 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 130 clocks = <&tcb0_clk>;
131 clock-names = "t0_clk";
655ff266
LD		 132 };
133
134 i2c0: i2c@f0014000 {
135 compatible = "atmel,at91sam9x5-i2c";
136 reg = <0xf0014000 0x4000>;
5e8b3bc3 137 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 138 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
139 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 140 dma-names = "tx", "rx";
655ff266
LD		 141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_i2c0>;
143 #address-cells = <1>;
144 #size-cells = <0>;
d2e8190b 145 clocks = <&twi0_clk>;
655ff266
LD		 146 status = "disabled";
147 };
148
149 i2c1: i2c@f0018000 {
150 compatible = "atmel,at91sam9x5-i2c";
151 reg = <0xf0018000 0x4000>;
5e8b3bc3 152 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 153 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
154 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 155 dma-names = "tx", "rx";
655ff266
LD		 156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c1>;
158 #address-cells = <1>;
159 #size-cells = <0>;
d2e8190b 160 clocks = <&twi1_clk>;
655ff266
LD		 161 status = "disabled";
162 };
163
164 usart0: serial@f001c000 {
165 compatible = "atmel,at91sam9260-usart";
166 reg = <0xf001c000 0x100>;
5e8b3bc3 167 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 170 clocks = <&usart0_clk>;
171 clock-names = "usart";
655ff266
LD		 172 status = "disabled";
173 };
174
175 usart1: serial@f0020000 {
176 compatible = "atmel,at91sam9260-usart";
177 reg = <0xf0020000 0x100>;
5e8b3bc3 178 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 181 clocks = <&usart1_clk>;
182 clock-names = "usart";
655ff266
LD		 183 status = "disabled";
184 };
185
f3ab0527
BS		 186 pwm0: pwm@f002c000 {
187 compatible = "atmel,sama5d3-pwm";
188 reg = <0xf002c000 0x300>;
189 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
190 #pwm-cells = <3>;
191 clocks = <&pwm_clk>;
192 status = "disabled";
193 };
655ff266 194
655ff266
LD		 195 isi: isi@f0034000 {
196 compatible = "atmel,at91sam9g45-isi";
197 reg = <0xf0034000 0x4000>;
5e8b3bc3 198 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 199 status = "disabled";
200 };
201
202 mmc1: mmc@f8000000 {
203 compatible = "atmel,hsmci";
204 reg = <0xf8000000 0x600>;
5e8b3bc3 205 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 206 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 207 dma-names = "rxtx";
655ff266
LD		 208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
210 status = "disabled";
211 #address-cells = <1>;
212 #size-cells = <0>;
d2e8190b
BB		 213 clocks = <&mci1_clk>;
214 clock-names = "mci_clk";
655ff266
LD		 215 };
216
655ff266
LD		 217 spi1: spi@f8008000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
b7ef678e 220 compatible = "atmel,at91rm9200-spi";
655ff266 221 reg = <0xf8008000 0x100>;
5e8b3bc3 222 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 223 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
224 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
225 dma-names = "tx", "rx";
655ff266
LD		 226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 228 clocks = <&spi1_clk>;
229 clock-names = "spi_clk";
655ff266
LD		 230 status = "disabled";
231 };
232
233 ssc1: ssc@f800c000 {
234 compatible = "atmel,at91sam9g45-ssc";
235 reg = <0xf800c000 0x4000>;
5e8b3bc3 236 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 237 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
238 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
239 dma-names = "tx", "rx";
655ff266
LD		 240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 242 clocks = <&ssc1_clk>;
243 clock-names = "pclk";
655ff266
LD		 244 status = "disabled";
245 };
246
655ff266 247 adc0: adc@f8018000 {
b3b84dec
AB		 248 #address-cells = <1>;
249 #size-cells = <0>;
9879b96d 250 compatible = "atmel,at91sam9x5-adc";
655ff266 251 reg = <0xf8018000 0x100>;
5e8b3bc3 252 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 253 pinctrl-names = "default";
254 pinctrl-0 = <
255 &pinctrl_adc0_adtrg
256 &pinctrl_adc0_ad0
257 &pinctrl_adc0_ad1
258 &pinctrl_adc0_ad2
259 &pinctrl_adc0_ad3
260 &pinctrl_adc0_ad4
261 &pinctrl_adc0_ad5
262 &pinctrl_adc0_ad6
263 &pinctrl_adc0_ad7
264 &pinctrl_adc0_ad8
265 &pinctrl_adc0_ad9
266 &pinctrl_adc0_ad10
267 &pinctrl_adc0_ad11
268 >;
d2e8190b
BB		 269 clocks = <&adc_clk>,
270 <&adc_op_clk>;
271 clock-names = "adc_clk", "adc_op_clk";
655ff266 272 atmel,adc-channels-used = <0xfff>;
655ff266 273 atmel,adc-startup-time = <40>;
b3b84dec 274 atmel,adc-use-external-triggers;
655ff266
LD		 275 atmel,adc-vref = <3000>;
276 atmel,adc-res = <10 12>;
277 atmel,adc-res-names = "lowres", "highres";
278 status = "disabled";
279
280 trigger@0 {
b3b84dec 281 reg = <0>;
655ff266
LD		 282 trigger-name = "external-rising";
283 trigger-value = <0x1>;
284 trigger-external;
285 };
286 trigger@1 {
b3b84dec 287 reg = <1>;
655ff266
LD		 288 trigger-name = "external-falling";
289 trigger-value = <0x2>;
290 trigger-external;
291 };
292 trigger@2 {
b3b84dec 293 reg = <2>;
655ff266
LD		 294 trigger-name = "external-any";
295 trigger-value = <0x3>;
296 trigger-external;
297 };
298 trigger@3 {
b3b84dec 299 reg = <3>;
655ff266
LD		 300 trigger-name = "continuous";
301 trigger-value = <0x6>;
302 };
303 };
304
655ff266
LD		 305 i2c2: i2c@f801c000 {
306 compatible = "atmel,at91sam9x5-i2c";
307 reg = <0xf801c000 0x4000>;
5e8b3bc3 308 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 309 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
310 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 311 dma-names = "tx", "rx";
557844ec
NF		 312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 314 #address-cells = <1>;
315 #size-cells = <0>;
d2e8190b 316 clocks = <&twi2_clk>;
655ff266
LD		 317 status = "disabled";
318 };
319
320 usart2: serial@f8020000 {
321 compatible = "atmel,at91sam9260-usart";
322 reg = <0xf8020000 0x100>;
5e8b3bc3 323 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 326 clocks = <&usart2_clk>;
327 clock-names = "usart";
655ff266
LD		 328 status = "disabled";
329 };
330
331 usart3: serial@f8024000 {
332 compatible = "atmel,at91sam9260-usart";
333 reg = <0xf8024000 0x100>;
5e8b3bc3 334 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 337 clocks = <&usart3_clk>;
338 clock-names = "usart";
655ff266
LD		 339 status = "disabled";
340 };
341
655ff266 342 sha@f8034000 {
c76f266d 343 compatible = "atmel,at91sam9g46-sha";
655ff266 344 reg = <0xf8034000 0x100>;
5e8b3bc3 345 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 346 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
347 dma-names = "tx";
4df4f446
BB		 348 clocks = <&sha_clk>;
349 clock-names = "sha_clk";
655ff266
LD		 350 };
351
352 aes@f8038000 {
c76f266d 353 compatible = "atmel,at91sam9g46-aes";
655ff266 354 reg = <0xf8038000 0x100>;
07f7d503 355 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
357 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
358 dma-names = "tx", "rx";
f68cd356
BB		 359 clocks = <&aes_clk>;
360 clock-names = "aes_clk";
655ff266
LD		 361 };
362
363 tdes@f803c000 {
c76f266d 364 compatible = "atmel,at91sam9g46-tdes";
655ff266 365 reg = <0xf803c000 0x100>;
5e8b3bc3 366 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 367 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
368 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
369 dma-names = "tx", "rx";
45e5c2cb
BB		 370 clocks = <&tdes_clk>;
371 clock-names = "tdes_clk";
655ff266
LD		 372 };
373
374 dma0: dma-controller@ffffe600 {
375 compatible = "atmel,at91sam9g45-dma";
376 reg = <0xffffe600 0x200>;
5e8b3bc3 377 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 378 #dma-cells = <2>;
d2e8190b
BB		 379 clocks = <&dma0_clk>;
380 clock-names = "dma_clk";
655ff266
LD		 381 };
382
383 dma1: dma-controller@ffffe800 {
384 compatible = "atmel,at91sam9g45-dma";
385 reg = <0xffffe800 0x200>;
5e8b3bc3 386 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 387 #dma-cells = <2>;
d2e8190b
BB		 388 clocks = <&dma1_clk>;
389 clock-names = "dma_clk";
655ff266
LD		 390 };
391
392 ramc0: ramc@ffffea00 {
393 compatible = "atmel,at91sam9g45-ddramc";
394 reg = <0xffffea00 0x200>;
395 };
396
397 dbgu: serial@ffffee00 {
398 compatible = "atmel,at91sam9260-usart";
399 reg = <0xffffee00 0x200>;
5e8b3bc3 400 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 403 clocks = <&dbgu_clk>;
404 clock-names = "usart";
655ff266
LD		 405 status = "disabled";
406 };
407
408 aic: interrupt-controller@fffff000 {
409 #interrupt-cells = <3>;
410 compatible = "atmel,sama5d3-aic";
411 interrupt-controller;
412 reg = <0xfffff000 0x200>;
413 atmel,external-irqs = <47>;
414 };
415
416 pinctrl@fffff200 {
417 #address-cells = <1>;
418 #size-cells = <1>;
419 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
420 ranges = <0xfffff200 0xfffff200 0xa00>;
421 atmel,mux-mask = <
422 /* A B C */
423 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
424 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
425 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
426 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
427 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
428 >;
429
430 /* shared pinctrl settings */
431 adc0 {
432 pinctrl_adc0_adtrg: adc0_adtrg {
433 atmel,pins =
c9d0f317 434 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 435 };
436 pinctrl_adc0_ad0: adc0_ad0 {
437 atmel,pins =
c9d0f317 438 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 439 };
440 pinctrl_adc0_ad1: adc0_ad1 {
441 atmel,pins =
c9d0f317 442 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 443 };
444 pinctrl_adc0_ad2: adc0_ad2 {
445 atmel,pins =
c9d0f317 446 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 447 };
448 pinctrl_adc0_ad3: adc0_ad3 {
449 atmel,pins =
c9d0f317 450 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 451 };
452 pinctrl_adc0_ad4: adc0_ad4 {
453 atmel,pins =
c9d0f317 454 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 455 };
456 pinctrl_adc0_ad5: adc0_ad5 {
457 atmel,pins =
c9d0f317 458 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 459 };
460 pinctrl_adc0_ad6: adc0_ad6 {
461 atmel,pins =
c9d0f317 462 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 463 };
464 pinctrl_adc0_ad7: adc0_ad7 {
465 atmel,pins =
c9d0f317 466 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 467 };
468 pinctrl_adc0_ad8: adc0_ad8 {
469 atmel,pins =
c9d0f317 470 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 471 };
472 pinctrl_adc0_ad9: adc0_ad9 {
473 atmel,pins =
c9d0f317 474 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 475 };
476 pinctrl_adc0_ad10: adc0_ad10 {
477 atmel,pins =
c9d0f317 478 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 479 };
480 pinctrl_adc0_ad11: adc0_ad11 {
481 atmel,pins =
c9d0f317 482 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 483 };
484 };
485
655ff266
LD		 486 dbgu {
487 pinctrl_dbgu: dbgu-0 {
488 atmel,pins =
c9d0f317
JCPV		 489 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
490 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 491 };
492 };
493
494 i2c0 {
495 pinctrl_i2c0: i2c0-0 {
496 atmel,pins =
c9d0f317
JCPV		 497 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
498 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 499 };
500 };
501
502 i2c1 {
503 pinctrl_i2c1: i2c1-0 {
504 atmel,pins =
c9d0f317
JCPV		 505 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
506 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 507 };
508 };
509
557844ec
NF		 510 i2c2 {
511 pinctrl_i2c2: i2c2-0 {
512 atmel,pins =
513 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
514 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
515 };
516 };
517
655ff266
LD		 518 isi {
519 pinctrl_isi: isi-0 {
520 atmel,pins =
c9d0f317
JCPV		 521 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
522 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
523 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
524 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
525 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
526 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
527 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
528 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
529 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
530 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
531 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
532 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
533 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 534 };
535 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
536 atmel,pins =
c9d0f317 537 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 538 };
539 };
540
655ff266
LD		 541 mmc0 {
542 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
543 atmel,pins =
c9d0f317
JCPV		 544 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
545 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
546 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 547 };
548 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
549 atmel,pins =
c9d0f317
JCPV		 550 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
551 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
552 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 553 };
554 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
555 atmel,pins =
c9d0f317
JCPV		 556 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
557 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
558 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
559 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 560 };
561 };
562
563 mmc1 {
564 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
565 atmel,pins =
c9d0f317
JCPV		 566 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
567 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
568 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 569 };
570 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
571 atmel,pins =
c9d0f317
JCPV		 572 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
573 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
574 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 575 };
576 };
577
655ff266
LD		 578 nand0 {
579 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
580 atmel,pins =
c9d0f317
JCPV		 581 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
582 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 583 };
584 };
585
655ff266
LD		 586 spi0 {
587 pinctrl_spi0: spi0-0 {
588 atmel,pins =
c9d0f317
JCPV		 589 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
590 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
591 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 592 };
593 };
594
595 spi1 {
596 pinctrl_spi1: spi1-0 {
597 atmel,pins =
c9d0f317
JCPV		 598 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
599 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
600 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 601 };
602 };
603
604 ssc0 {
605 pinctrl_ssc0_tx: ssc0_tx {
606 atmel,pins =
c9d0f317
JCPV		 607 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
608 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
609 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 610 };
611
612 pinctrl_ssc0_rx: ssc0_rx {
613 atmel,pins =
c9d0f317
JCPV		 614 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
615 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
616 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 617 };
618 };
619
620 ssc1 {
621 pinctrl_ssc1_tx: ssc1_tx {
622 atmel,pins =
c9d0f317
JCPV		 623 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
624 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
625 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 626 };
627
628 pinctrl_ssc1_rx: ssc1_rx {
629 atmel,pins =
c9d0f317
JCPV		 630 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
631 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
632 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 633 };
634 };
635
655ff266
LD		 636 usart0 {
637 pinctrl_usart0: usart0-0 {
638 atmel,pins =
c9d0f317
JCPV		 639 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
640 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 641 };
642
643 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
644 atmel,pins =
c9d0f317
JCPV		 645 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
646 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 647 };
648 };
649
650 usart1 {
651 pinctrl_usart1: usart1-0 {
652 atmel,pins =
c9d0f317
JCPV		 653 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
654 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 655 };
656
657 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
658 atmel,pins =
c9d0f317
JCPV		 659 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
660 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 661 };
662 };
663
664 usart2 {
665 pinctrl_usart2: usart2-0 {
666 atmel,pins =
c9d0f317
JCPV		 667 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
668 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 669 };
670
671 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
672 atmel,pins =
c9d0f317
JCPV		 673 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
674 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 675 };
676 };
677
678 usart3 {
679 pinctrl_usart3: usart3-0 {
680 atmel,pins =
c9d0f317
JCPV		 681 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
682 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 683 };
684
685 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
686 atmel,pins =
c9d0f317
JCPV		 687 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
688 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 689 };
690 };
c9d0f317
JCPV		 691
692
693 pioA: gpio@fffff200 {
694 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
695 reg = <0xfffff200 0x100>;
5e8b3bc3 696 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 697 #gpio-cells = <2>;
698 gpio-controller;
699 interrupt-controller;
700 #interrupt-cells = <2>;
d2e8190b 701 clocks = <&pioA_clk>;
c9d0f317
JCPV		 702 };
703
704 pioB: gpio@fffff400 {
705 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
706 reg = <0xfffff400 0x100>;
5e8b3bc3 707 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 708 #gpio-cells = <2>;
709 gpio-controller;
710 interrupt-controller;
711 #interrupt-cells = <2>;
d2e8190b 712 clocks = <&pioB_clk>;
c9d0f317
JCPV		 713 };
714
715 pioC: gpio@fffff600 {
716 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
717 reg = <0xfffff600 0x100>;
5e8b3bc3 718 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 719 #gpio-cells = <2>;
720 gpio-controller;
721 interrupt-controller;
722 #interrupt-cells = <2>;
d2e8190b 723 clocks = <&pioC_clk>;
c9d0f317
JCPV		 724 };
725
726 pioD: gpio@fffff800 {
727 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
728 reg = <0xfffff800 0x100>;
5e8b3bc3 729 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 730 #gpio-cells = <2>;
731 gpio-controller;
732 interrupt-controller;
733 #interrupt-cells = <2>;
d2e8190b 734 clocks = <&pioD_clk>;
c9d0f317
JCPV		 735 };
736
737 pioE: gpio@fffffa00 {
738 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
739 reg = <0xfffffa00 0x100>;
5e8b3bc3 740 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 741 #gpio-cells = <2>;
742 gpio-controller;
743 interrupt-controller;
744 #interrupt-cells = <2>;
d2e8190b 745 clocks = <&pioE_clk>;
c9d0f317 746 };
655ff266
LD		 747 };
748
749 pmc: pmc@fffffc00 {
d2e8190b 750 compatible = "atmel,sama5d3-pmc";
655ff266 751 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 752 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
753 interrupt-controller;
754 #address-cells = <1>;
755 #size-cells = <0>;
756 #interrupt-cells = <1>;
757
758 clk32k: slck {
759 compatible = "fixed-clock";
760 #clock-cells = <0>;
761 clock-frequency = <32768>;
762 };
763
764 main: mainck {
765 compatible = "atmel,at91rm9200-clk-main";
766 #clock-cells = <0>;
767 interrupt-parent = <&pmc>;
768 interrupts = <AT91_PMC_MOSCS>;
769 clocks = <&clk32k>;
770 };
771
772 plla: pllack {
773 compatible = "atmel,sama5d3-clk-pll";
774 #clock-cells = <0>;
775 interrupt-parent = <&pmc>;
776 interrupts = <AT91_PMC_LOCKA>;
777 clocks = <&main>;
778 reg = <0>;
779 atmel,clk-input-range = <8000000 50000000>;
780 #atmel,pll-clk-output-range-cells = <4>;
781 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
782 };
783
784 plladiv: plladivck {
785 compatible = "atmel,at91sam9x5-clk-plldiv";
786 #clock-cells = <0>;
787 clocks = <&plla>;
788 };
789
790 utmi: utmick {
791 compatible = "atmel,at91sam9x5-clk-utmi";
792 #clock-cells = <0>;
793 interrupt-parent = <&pmc>;
794 interrupts = <AT91_PMC_LOCKU>;
795 clocks = <&main>;
796 };
797
798 mck: masterck {
799 compatible = "atmel,at91sam9x5-clk-master";
800 #clock-cells = <0>;
801 interrupt-parent = <&pmc>;
802 interrupts = <AT91_PMC_MCKRDY>;
803 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
804 atmel,clk-output-range = <0 166000000>;
805 atmel,clk-divisors = <1 2 4 3>;
806 };
807
808 usb: usbck {
809 compatible = "atmel,at91sam9x5-clk-usb";
810 #clock-cells = <0>;
811 clocks = <&plladiv>, <&utmi>;
812 };
813
814 prog: progck {
815 compatible = "atmel,at91sam9x5-clk-programmable";
816 #address-cells = <1>;
817 #size-cells = <0>;
818 interrupt-parent = <&pmc>;
819 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
820
821 prog0: prog0 {
822 #clock-cells = <0>;
823 reg = <0>;
824 interrupts = <AT91_PMC_PCKRDY(0)>;
825 };
826
827 prog1: prog1 {
828 #clock-cells = <0>;
829 reg = <1>;
830 interrupts = <AT91_PMC_PCKRDY(1)>;
831 };
832
833 prog2: prog2 {
834 #clock-cells = <0>;
835 reg = <2>;
836 interrupts = <AT91_PMC_PCKRDY(2)>;
837 };
838 };
839
840 smd: smdclk {
841 compatible = "atmel,at91sam9x5-clk-smd";
842 #clock-cells = <0>;
843 clocks = <&plladiv>, <&utmi>;
844 };
845
846 systemck {
847 compatible = "atmel,at91rm9200-clk-system";
848 #address-cells = <1>;
849 #size-cells = <0>;
850
851 ddrck: ddrck {
852 #clock-cells = <0>;
853 reg = <2>;
854 clocks = <&mck>;
855 };
856
857 smdck: smdck {
858 #clock-cells = <0>;
859 reg = <4>;
860 clocks = <&smd>;
861 };
862
863 uhpck: uhpck {
864 #clock-cells = <0>;
865 reg = <6>;
866 clocks = <&usb>;
867 };
868
869 udpck: udpck {
870 #clock-cells = <0>;
871 reg = <7>;
872 clocks = <&usb>;
873 };
874
875 pck0: pck0 {
876 #clock-cells = <0>;
877 reg = <8>;
878 clocks = <&prog0>;
879 };
880
881 pck1: pck1 {
882 #clock-cells = <0>;
883 reg = <9>;
884 clocks = <&prog1>;
885 };
886
887 pck2: pck2 {
888 #clock-cells = <0>;
889 reg = <10>;
890 clocks = <&prog2>;
891 };
892 };
893
894 periphck {
895 compatible = "atmel,at91sam9x5-clk-peripheral";
896 #address-cells = <1>;
897 #size-cells = <0>;
898 clocks = <&mck>;
899
900 dbgu_clk: dbgu_clk {
901 #clock-cells = <0>;
902 reg = <2>;
903 };
904
905 pioA_clk: pioA_clk {
906 #clock-cells = <0>;
907 reg = <6>;
908 };
909
910 pioB_clk: pioB_clk {
911 #clock-cells = <0>;
912 reg = <7>;
913 };
914
915 pioC_clk: pioC_clk {
916 #clock-cells = <0>;
917 reg = <8>;
918 };
919
920 pioD_clk: pioD_clk {
921 #clock-cells = <0>;
922 reg = <9>;
923 };
924
925 pioE_clk: pioE_clk {
926 #clock-cells = <0>;
927 reg = <10>;
928 };
929
930 usart0_clk: usart0_clk {
931 #clock-cells = <0>;
932 reg = <12>;
933 atmel,clk-output-range = <0 66000000>;
934 };
935
936 usart1_clk: usart1_clk {
937 #clock-cells = <0>;
938 reg = <13>;
939 atmel,clk-output-range = <0 66000000>;
940 };
941
942 usart2_clk: usart2_clk {
943 #clock-cells = <0>;
944 reg = <14>;
945 atmel,clk-output-range = <0 66000000>;
946 };
947
948 usart3_clk: usart3_clk {
949 #clock-cells = <0>;
950 reg = <15>;
951 atmel,clk-output-range = <0 66000000>;
952 };
953
954 twi0_clk: twi0_clk {
955 reg = <18>;
956 #clock-cells = <0>;
957 atmel,clk-output-range = <0 16625000>;
958 };
959
960 twi1_clk: twi1_clk {
961 #clock-cells = <0>;
962 reg = <19>;
963 atmel,clk-output-range = <0 16625000>;
964 };
965
966 twi2_clk: twi2_clk {
967 #clock-cells = <0>;
968 reg = <20>;
969 atmel,clk-output-range = <0 16625000>;
970 };
971
972 mci0_clk: mci0_clk {
973 #clock-cells = <0>;
974 reg = <21>;
975 };
976
977 mci1_clk: mci1_clk {
978 #clock-cells = <0>;
979 reg = <22>;
980 };
981
982 spi0_clk: spi0_clk {
983 #clock-cells = <0>;
984 reg = <24>;
985 atmel,clk-output-range = <0 133000000>;
986 };
987
988 spi1_clk: spi1_clk {
989 #clock-cells = <0>;
990 reg = <25>;
991 atmel,clk-output-range = <0 133000000>;
992 };
993
994 tcb0_clk: tcb0_clk {
995 #clock-cells = <0>;
996 reg = <26>;
997 atmel,clk-output-range = <0 133000000>;
998 };
999
1000 pwm_clk: pwm_clk {
1001 #clock-cells = <0>;
1002 reg = <28>;
1003 };
1004
1005 adc_clk: adc_clk {
1006 #clock-cells = <0>;
1007 reg = <29>;
1008 atmel,clk-output-range = <0 66000000>;
1009 };
1010
1011 dma0_clk: dma0_clk {
1012 #clock-cells = <0>;
1013 reg = <30>;
1014 };
1015
1016 dma1_clk: dma1_clk {
1017 #clock-cells = <0>;
1018 reg = <31>;
1019 };
1020
1021 uhphs_clk: uhphs_clk {
1022 #clock-cells = <0>;
1023 reg = <32>;
1024 };
1025
1026 udphs_clk: udphs_clk {
1027 #clock-cells = <0>;
1028 reg = <33>;
1029 };
1030
1031 isi_clk: isi_clk {
1032 #clock-cells = <0>;
1033 reg = <37>;
1034 };
1035
1036 ssc0_clk: ssc0_clk {
1037 #clock-cells = <0>;
1038 reg = <38>;
1039 atmel,clk-output-range = <0 66000000>;
1040 };
1041
1042 ssc1_clk: ssc1_clk {
1043 #clock-cells = <0>;
1044 reg = <39>;
1045 atmel,clk-output-range = <0 66000000>;
1046 };
1047
1048 sha_clk: sha_clk {
1049 #clock-cells = <0>;
1050 reg = <42>;
1051 };
1052
1053 aes_clk: aes_clk {
1054 #clock-cells = <0>;
1055 reg = <43>;
1056 };
1057
1058 tdes_clk: tdes_clk {
1059 #clock-cells = <0>;
1060 reg = <44>;
1061 };
1062
1063 trng_clk: trng_clk {
1064 #clock-cells = <0>;
1065 reg = <45>;
1066 };
1067
1068 fuse_clk: fuse_clk {
1069 #clock-cells = <0>;
1070 reg = <48>;
1071 };
1072 };
655ff266
LD		 1073 };
1074
1075 rstc@fffffe00 {
1076 compatible = "atmel,at91sam9g45-rstc";
1077 reg = <0xfffffe00 0x10>;
1078 };
1079
1080 pit: timer@fffffe30 {
1081 compatible = "atmel,at91sam9260-pit";
1082 reg = <0xfffffe30 0xf>;
5e8b3bc3 1083 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1084 clocks = <&mck>;
655ff266
LD		 1085 };
1086
1087 watchdog@fffffe40 {
1088 compatible = "atmel,at91sam9260-wdt";
1089 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1090 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1091 atmel,watchdog-type = "hardware";
1092 atmel,reset-type = "all";
1093 atmel,dbg-halt;
1094 atmel,idle-halt;
655ff266
LD		 1095 status = "disabled";
1096 };
1097
1098 rtc@fffffeb0 {
1099 compatible = "atmel,at91rm9200-rtc";
1100 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1101 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1102 };
1103 };
1104
1105 usb0: gadget@00500000 {
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108 compatible = "atmel,at91sam9rl-udc";
1109 reg = <0x00500000 0x100000
1110 0xf8030000 0x4000>;
5e8b3bc3 1111 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1112 clocks = <&udphs_clk>, <&utmi>;
1113 clock-names = "pclk", "hclk";
655ff266
LD		 1114 status = "disabled";
1115
1116 ep0 {
1117 reg = <0>;
1118 atmel,fifo-size = <64>;
1119 atmel,nb-banks = <1>;
1120 };
1121
1122 ep1 {
1123 reg = <1>;
1124 atmel,fifo-size = <1024>;
1125 atmel,nb-banks = <3>;
1126 atmel,can-dma;
1127 atmel,can-isoc;
1128 };
1129
1130 ep2 {
1131 reg = <2>;
1132 atmel,fifo-size = <1024>;
1133 atmel,nb-banks = <3>;
1134 atmel,can-dma;
1135 atmel,can-isoc;
1136 };
1137
1138 ep3 {
1139 reg = <3>;
1140 atmel,fifo-size = <1024>;
1141 atmel,nb-banks = <2>;
1142 atmel,can-dma;
1143 };
1144
1145 ep4 {
1146 reg = <4>;
1147 atmel,fifo-size = <1024>;
1148 atmel,nb-banks = <2>;
1149 atmel,can-dma;
1150 };
1151
1152 ep5 {
1153 reg = <5>;
1154 atmel,fifo-size = <1024>;
1155 atmel,nb-banks = <2>;
1156 atmel,can-dma;
1157 };
1158
1159 ep6 {
1160 reg = <6>;
1161 atmel,fifo-size = <1024>;
1162 atmel,nb-banks = <2>;
1163 atmel,can-dma;
1164 };
1165
1166 ep7 {
1167 reg = <7>;
1168 atmel,fifo-size = <1024>;
1169 atmel,nb-banks = <2>;
1170 atmel,can-dma;
1171 };
1172
1173 ep8 {
1174 reg = <8>;
1175 atmel,fifo-size = <1024>;
1176 atmel,nb-banks = <2>;
1177 };
1178
1179 ep9 {
1180 reg = <9>;
1181 atmel,fifo-size = <1024>;
1182 atmel,nb-banks = <2>;
1183 };
1184
1185 ep10 {
1186 reg = <10>;
1187 atmel,fifo-size = <1024>;
1188 atmel,nb-banks = <2>;
1189 };
1190
1191 ep11 {
1192 reg = <11>;
1193 atmel,fifo-size = <1024>;
1194 atmel,nb-banks = <2>;
1195 };
1196
1197 ep12 {
1198 reg = <12>;
1199 atmel,fifo-size = <1024>;
1200 atmel,nb-banks = <2>;
1201 };
1202
1203 ep13 {
1204 reg = <13>;
1205 atmel,fifo-size = <1024>;
1206 atmel,nb-banks = <2>;
1207 };
1208
1209 ep14 {
1210 reg = <14>;
1211 atmel,fifo-size = <1024>;
1212 atmel,nb-banks = <2>;
1213 };
1214
1215 ep15 {
1216 reg = <15>;
1217 atmel,fifo-size = <1024>;
1218 atmel,nb-banks = <2>;
1219 };
1220 };
1221
1222 usb1: ohci@00600000 {
1223 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1224 reg = <0x00600000 0x100000>;
5e8b3bc3 1225 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1226 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1227 <&uhpck>;
1228 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1229 status = "disabled";
1230 };
1231
1232 usb2: ehci@00700000 {
1233 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1234 reg = <0x00700000 0x100000>;
5e8b3bc3 1235 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1236 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1237 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1238 status = "disabled";
1239 };
1240
1241 nand0: nand@60000000 {
1242 compatible = "atmel,at91rm9200-nand";
1243 #address-cells = <1>;
1244 #size-cells = <1>;
8ae599ef 1245 ranges;
655ff266
LD		 1246 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1247 0xffffc070 0x00000490 /* SMC PMECC regs */
1248 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1249 0x00110000 0x00018000 /* ROM code */
655ff266 1250 >;
5e8b3bc3 1251 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1252 atmel,nand-addr-offset = <21>;
1253 atmel,nand-cmd-offset = <22>;
e8b2da6e 1254 atmel,nand-has-dma;
655ff266
LD		 1255 pinctrl-names = "default";
1256 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1257 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1258 status = "disabled";
8ae599ef
JW		 1259
1260 nfc@70000000 {
1261 compatible = "atmel,sama5d3-nfc";
1262 #address-cells = <1>;
1263 #size-cells = <1>;
1264 reg = <
1265 0x70000000 0x10000000 /* NFC Command Registers */
1266 0xffffc000 0x00000070 /* NFC HSMC regs */
1267 0x00200000 0x00100000 /* NFC SRAM banks */
1268 >;
1269 };
655ff266
LD		 1270 };
1271 };
1272};
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