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ARM: at91/dt: add clk properties to sama5d3 AES device node
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
d2e8190b 16#include <dt-bindings/clk/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
d2e8190b
BB		 61 clocks {
62 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <20000000>;
66 };
67 };
68
655ff266
LD		 69 ahb {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 apb {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 mmc0: mmc@f0000000 {
82 compatible = "atmel,hsmci";
83 reg = <0xf0000000 0x600>;
5e8b3bc3 84 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 85 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 86 dma-names = "rxtx";
655ff266
LD		 87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
89 status = "disabled";
90 #address-cells = <1>;
91 #size-cells = <0>;
d2e8190b
BB		 92 clocks = <&mci0_clk>;
93 clock-names = "mci_clk";
655ff266
LD		 94 };
95
96 spi0: spi@f0004000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
b7ef678e 99 compatible = "atmel,at91rm9200-spi";
655ff266 100 reg = <0xf0004000 0x100>;
5e8b3bc3 101 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
103 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
104 dma-names = "tx", "rx";
655ff266
LD		 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 107 clocks = <&spi0_clk>;
108 clock-names = "spi_clk";
655ff266
LD		 109 status = "disabled";
110 };
111
112 ssc0: ssc@f0008000 {
113 compatible = "atmel,at91sam9g45-ssc";
114 reg = <0xf0008000 0x4000>;
5e8b3bc3 115 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 118 clocks = <&ssc0_clk>;
119 clock-names = "pclk";
655ff266
LD		 120 status = "disabled";
121 };
122
655ff266
LD		 123 tcb0: timer@f0010000 {
124 compatible = "atmel,at91sam9x5-tcb";
125 reg = <0xf0010000 0x100>;
5e8b3bc3 126 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 127 clocks = <&tcb0_clk>;
128 clock-names = "t0_clk";
655ff266
LD		 129 };
130
131 i2c0: i2c@f0014000 {
132 compatible = "atmel,at91sam9x5-i2c";
133 reg = <0xf0014000 0x4000>;
5e8b3bc3 134 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 135 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
136 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 137 dma-names = "tx", "rx";
655ff266
LD		 138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c0>;
140 #address-cells = <1>;
141 #size-cells = <0>;
d2e8190b 142 clocks = <&twi0_clk>;
655ff266
LD		 143 status = "disabled";
144 };
145
146 i2c1: i2c@f0018000 {
147 compatible = "atmel,at91sam9x5-i2c";
148 reg = <0xf0018000 0x4000>;
5e8b3bc3 149 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
151 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 152 dma-names = "tx", "rx";
655ff266
LD		 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 #address-cells = <1>;
156 #size-cells = <0>;
d2e8190b 157 clocks = <&twi1_clk>;
655ff266
LD		 158 status = "disabled";
159 };
160
161 usart0: serial@f001c000 {
162 compatible = "atmel,at91sam9260-usart";
163 reg = <0xf001c000 0x100>;
5e8b3bc3 164 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 167 clocks = <&usart0_clk>;
168 clock-names = "usart";
655ff266
LD		 169 status = "disabled";
170 };
171
172 usart1: serial@f0020000 {
173 compatible = "atmel,at91sam9260-usart";
174 reg = <0xf0020000 0x100>;
5e8b3bc3 175 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 178 clocks = <&usart1_clk>;
179 clock-names = "usart";
655ff266
LD		 180 status = "disabled";
181 };
f3ab0527
BS		 182
183 pwm0: pwm@f002c000 {
184 compatible = "atmel,sama5d3-pwm";
185 reg = <0xf002c000 0x300>;
186 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
187 #pwm-cells = <3>;
188 clocks = <&pwm_clk>;
189 status = "disabled";
190 };
655ff266 191
655ff266
LD		 192 isi: isi@f0034000 {
193 compatible = "atmel,at91sam9g45-isi";
194 reg = <0xf0034000 0x4000>;
5e8b3bc3 195 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 196 status = "disabled";
197 };
198
199 mmc1: mmc@f8000000 {
200 compatible = "atmel,hsmci";
201 reg = <0xf8000000 0x600>;
5e8b3bc3 202 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 203 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 204 dma-names = "rxtx";
655ff266
LD		 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
207 status = "disabled";
208 #address-cells = <1>;
209 #size-cells = <0>;
d2e8190b
BB		 210 clocks = <&mci1_clk>;
211 clock-names = "mci_clk";
655ff266
LD		 212 };
213
655ff266
LD		 214 spi1: spi@f8008000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
b7ef678e 217 compatible = "atmel,at91rm9200-spi";
655ff266 218 reg = <0xf8008000 0x100>;
5e8b3bc3 219 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 220 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
221 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
222 dma-names = "tx", "rx";
655ff266
LD		 223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 225 clocks = <&spi1_clk>;
226 clock-names = "spi_clk";
655ff266
LD		 227 status = "disabled";
228 };
229
230 ssc1: ssc@f800c000 {
231 compatible = "atmel,at91sam9g45-ssc";
232 reg = <0xf800c000 0x4000>;
5e8b3bc3 233 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 236 clocks = <&ssc1_clk>;
237 clock-names = "pclk";
655ff266
LD		 238 status = "disabled";
239 };
240
655ff266
LD		 241 adc0: adc@f8018000 {
242 compatible = "atmel,at91sam9260-adc";
243 reg = <0xf8018000 0x100>;
5e8b3bc3 244 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 245 pinctrl-names = "default";
246 pinctrl-0 = <
247 &pinctrl_adc0_adtrg
248 &pinctrl_adc0_ad0
249 &pinctrl_adc0_ad1
250 &pinctrl_adc0_ad2
251 &pinctrl_adc0_ad3
252 &pinctrl_adc0_ad4
253 &pinctrl_adc0_ad5
254 &pinctrl_adc0_ad6
255 &pinctrl_adc0_ad7
256 &pinctrl_adc0_ad8
257 &pinctrl_adc0_ad9
258 &pinctrl_adc0_ad10
259 &pinctrl_adc0_ad11
260 >;
d2e8190b
BB		 261 clocks = <&adc_clk>,
262 <&adc_op_clk>;
263 clock-names = "adc_clk", "adc_op_clk";
655ff266
LD		 264 atmel,adc-channel-base = <0x50>;
265 atmel,adc-channels-used = <0xfff>;
266 atmel,adc-drdy-mask = <0x1000000>;
267 atmel,adc-num-channels = <12>;
268 atmel,adc-startup-time = <40>;
269 atmel,adc-status-register = <0x30>;
270 atmel,adc-trigger-register = <0xc0>;
271 atmel,adc-use-external;
272 atmel,adc-vref = <3000>;
273 atmel,adc-res = <10 12>;
274 atmel,adc-res-names = "lowres", "highres";
275 status = "disabled";
276
277 trigger@0 {
278 trigger-name = "external-rising";
279 trigger-value = <0x1>;
280 trigger-external;
281 };
282 trigger@1 {
283 trigger-name = "external-falling";
284 trigger-value = <0x2>;
285 trigger-external;
286 };
287 trigger@2 {
288 trigger-name = "external-any";
289 trigger-value = <0x3>;
290 trigger-external;
291 };
292 trigger@3 {
293 trigger-name = "continuous";
294 trigger-value = <0x6>;
295 };
296 };
297
298 tsadcc: tsadcc@f8018000 {
299 compatible = "atmel,at91sam9x5-tsadcc";
300 reg = <0xf8018000 0x4000>;
5e8b3bc3 301 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 302 atmel,tsadcc_clock = <300000>;
303 atmel,filtering_average = <0x03>;
304 atmel,pendet_debounce = <0x08>;
305 atmel,pendet_sensitivity = <0x02>;
306 atmel,ts_sample_hold_time = <0x0a>;
307 status = "disabled";
308 };
309
310 i2c2: i2c@f801c000 {
311 compatible = "atmel,at91sam9x5-i2c";
312 reg = <0xf801c000 0x4000>;
5e8b3bc3 313 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 314 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
315 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 316 dma-names = "tx", "rx";
557844ec
NF		 317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 319 #address-cells = <1>;
320 #size-cells = <0>;
d2e8190b 321 clocks = <&twi2_clk>;
655ff266
LD		 322 status = "disabled";
323 };
324
325 usart2: serial@f8020000 {
326 compatible = "atmel,at91sam9260-usart";
327 reg = <0xf8020000 0x100>;
5e8b3bc3 328 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 331 clocks = <&usart2_clk>;
332 clock-names = "usart";
655ff266
LD		 333 status = "disabled";
334 };
335
336 usart3: serial@f8024000 {
337 compatible = "atmel,at91sam9260-usart";
338 reg = <0xf8024000 0x100>;
5e8b3bc3 339 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 342 clocks = <&usart3_clk>;
343 clock-names = "usart";
655ff266
LD		 344 status = "disabled";
345 };
346
655ff266 347 sha@f8034000 {
c76f266d 348 compatible = "atmel,at91sam9g46-sha";
655ff266 349 reg = <0xf8034000 0x100>;
5e8b3bc3 350 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 351 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
352 dma-names = "tx";
4df4f446
BB		 353 clocks = <&sha_clk>;
354 clock-names = "sha_clk";
655ff266
LD		 355 };
356
357 aes@f8038000 {
c76f266d 358 compatible = "atmel,at91sam9g46-aes";
655ff266 359 reg = <0xf8038000 0x100>;
07f7d503 360 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 361 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
362 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
363 dma-names = "tx", "rx";
f68cd356
BB		 364 clocks = <&aes_clk>;
365 clock-names = "aes_clk";
655ff266
LD		 366 };
367
368 tdes@f803c000 {
c76f266d 369 compatible = "atmel,at91sam9g46-tdes";
655ff266 370 reg = <0xf803c000 0x100>;
5e8b3bc3 371 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 372 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
373 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
374 dma-names = "tx", "rx";
655ff266
LD		 375 };
376
377 dma0: dma-controller@ffffe600 {
378 compatible = "atmel,at91sam9g45-dma";
379 reg = <0xffffe600 0x200>;
5e8b3bc3 380 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 381 #dma-cells = <2>;
d2e8190b
BB		 382 clocks = <&dma0_clk>;
383 clock-names = "dma_clk";
655ff266
LD		 384 };
385
386 dma1: dma-controller@ffffe800 {
387 compatible = "atmel,at91sam9g45-dma";
388 reg = <0xffffe800 0x200>;
5e8b3bc3 389 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 390 #dma-cells = <2>;
d2e8190b
BB		 391 clocks = <&dma1_clk>;
392 clock-names = "dma_clk";
655ff266
LD		 393 };
394
395 ramc0: ramc@ffffea00 {
396 compatible = "atmel,at91sam9g45-ddramc";
397 reg = <0xffffea00 0x200>;
398 };
399
400 dbgu: serial@ffffee00 {
401 compatible = "atmel,at91sam9260-usart";
402 reg = <0xffffee00 0x200>;
5e8b3bc3 403 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 406 clocks = <&dbgu_clk>;
407 clock-names = "usart";
655ff266
LD		 408 status = "disabled";
409 };
410
411 aic: interrupt-controller@fffff000 {
412 #interrupt-cells = <3>;
413 compatible = "atmel,sama5d3-aic";
414 interrupt-controller;
415 reg = <0xfffff000 0x200>;
416 atmel,external-irqs = <47>;
417 };
418
419 pinctrl@fffff200 {
420 #address-cells = <1>;
421 #size-cells = <1>;
422 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
423 ranges = <0xfffff200 0xfffff200 0xa00>;
424 atmel,mux-mask = <
425 /* A B C */
426 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
427 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
428 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
429 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
430 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
431 >;
432
433 /* shared pinctrl settings */
434 adc0 {
435 pinctrl_adc0_adtrg: adc0_adtrg {
436 atmel,pins =
c9d0f317 437 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 438 };
439 pinctrl_adc0_ad0: adc0_ad0 {
440 atmel,pins =
c9d0f317 441 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 442 };
443 pinctrl_adc0_ad1: adc0_ad1 {
444 atmel,pins =
c9d0f317 445 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 446 };
447 pinctrl_adc0_ad2: adc0_ad2 {
448 atmel,pins =
c9d0f317 449 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 450 };
451 pinctrl_adc0_ad3: adc0_ad3 {
452 atmel,pins =
c9d0f317 453 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 454 };
455 pinctrl_adc0_ad4: adc0_ad4 {
456 atmel,pins =
c9d0f317 457 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 458 };
459 pinctrl_adc0_ad5: adc0_ad5 {
460 atmel,pins =
c9d0f317 461 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 462 };
463 pinctrl_adc0_ad6: adc0_ad6 {
464 atmel,pins =
c9d0f317 465 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 466 };
467 pinctrl_adc0_ad7: adc0_ad7 {
468 atmel,pins =
c9d0f317 469 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 470 };
471 pinctrl_adc0_ad8: adc0_ad8 {
472 atmel,pins =
c9d0f317 473 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 474 };
475 pinctrl_adc0_ad9: adc0_ad9 {
476 atmel,pins =
c9d0f317 477 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 478 };
479 pinctrl_adc0_ad10: adc0_ad10 {
480 atmel,pins =
c9d0f317 481 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 482 };
483 pinctrl_adc0_ad11: adc0_ad11 {
484 atmel,pins =
c9d0f317 485 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 486 };
487 };
488
655ff266
LD		 489 dbgu {
490 pinctrl_dbgu: dbgu-0 {
491 atmel,pins =
c9d0f317
JCPV		 492 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
493 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 494 };
495 };
496
497 i2c0 {
498 pinctrl_i2c0: i2c0-0 {
499 atmel,pins =
c9d0f317
JCPV		 500 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
501 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 502 };
503 };
504
505 i2c1 {
506 pinctrl_i2c1: i2c1-0 {
507 atmel,pins =
c9d0f317
JCPV		 508 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
509 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 510 };
511 };
512
557844ec
NF		 513 i2c2 {
514 pinctrl_i2c2: i2c2-0 {
515 atmel,pins =
516 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
517 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
518 };
519 };
520
655ff266
LD		 521 isi {
522 pinctrl_isi: isi-0 {
523 atmel,pins =
c9d0f317
JCPV		 524 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
525 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
526 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
527 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
528 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
529 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
530 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
531 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
532 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
533 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
534 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
535 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
536 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 537 };
538 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
539 atmel,pins =
c9d0f317 540 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 541 };
542 };
543
655ff266
LD		 544 mmc0 {
545 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
546 atmel,pins =
c9d0f317
JCPV		 547 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
548 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
549 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 550 };
551 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
552 atmel,pins =
c9d0f317
JCPV		 553 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
554 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
555 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 556 };
557 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
558 atmel,pins =
c9d0f317
JCPV		 559 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
560 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
561 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
562 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 563 };
564 };
565
566 mmc1 {
567 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
568 atmel,pins =
c9d0f317
JCPV		 569 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
570 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
571 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 572 };
573 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
574 atmel,pins =
c9d0f317
JCPV		 575 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
576 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
577 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 578 };
579 };
580
655ff266
LD		 581 nand0 {
582 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
583 atmel,pins =
c9d0f317
JCPV		 584 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
585 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 586 };
587 };
588
655ff266
LD		 589 spi0 {
590 pinctrl_spi0: spi0-0 {
591 atmel,pins =
c9d0f317
JCPV		 592 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
593 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
594 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 595 };
596 };
597
598 spi1 {
599 pinctrl_spi1: spi1-0 {
600 atmel,pins =
c9d0f317
JCPV		 601 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
602 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
603 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 604 };
605 };
606
607 ssc0 {
608 pinctrl_ssc0_tx: ssc0_tx {
609 atmel,pins =
c9d0f317
JCPV		 610 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
611 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
612 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 613 };
614
615 pinctrl_ssc0_rx: ssc0_rx {
616 atmel,pins =
c9d0f317
JCPV		 617 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
618 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
619 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 620 };
621 };
622
623 ssc1 {
624 pinctrl_ssc1_tx: ssc1_tx {
625 atmel,pins =
c9d0f317
JCPV		 626 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
627 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
628 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 629 };
630
631 pinctrl_ssc1_rx: ssc1_rx {
632 atmel,pins =
c9d0f317
JCPV		 633 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
634 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
635 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 636 };
637 };
638
655ff266
LD		 639 usart0 {
640 pinctrl_usart0: usart0-0 {
641 atmel,pins =
c9d0f317
JCPV		 642 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
643 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 644 };
645
646 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
647 atmel,pins =
c9d0f317
JCPV		 648 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
649 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 650 };
651 };
652
653 usart1 {
654 pinctrl_usart1: usart1-0 {
655 atmel,pins =
c9d0f317
JCPV		 656 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
657 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 658 };
659
660 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
661 atmel,pins =
c9d0f317
JCPV		 662 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
663 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 664 };
665 };
666
667 usart2 {
668 pinctrl_usart2: usart2-0 {
669 atmel,pins =
c9d0f317
JCPV		 670 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
671 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 672 };
673
674 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
675 atmel,pins =
c9d0f317
JCPV		 676 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
677 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 678 };
679 };
680
681 usart3 {
682 pinctrl_usart3: usart3-0 {
683 atmel,pins =
c9d0f317
JCPV		 684 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
685 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 686 };
687
688 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
689 atmel,pins =
c9d0f317
JCPV		 690 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
691 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 692 };
693 };
c9d0f317
JCPV		 694
695
696 pioA: gpio@fffff200 {
697 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
698 reg = <0xfffff200 0x100>;
5e8b3bc3 699 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 700 #gpio-cells = <2>;
701 gpio-controller;
702 interrupt-controller;
703 #interrupt-cells = <2>;
d2e8190b 704 clocks = <&pioA_clk>;
c9d0f317
JCPV		 705 };
706
707 pioB: gpio@fffff400 {
708 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
709 reg = <0xfffff400 0x100>;
5e8b3bc3 710 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 711 #gpio-cells = <2>;
712 gpio-controller;
713 interrupt-controller;
714 #interrupt-cells = <2>;
d2e8190b 715 clocks = <&pioB_clk>;
c9d0f317
JCPV		 716 };
717
718 pioC: gpio@fffff600 {
719 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
720 reg = <0xfffff600 0x100>;
5e8b3bc3 721 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 722 #gpio-cells = <2>;
723 gpio-controller;
724 interrupt-controller;
725 #interrupt-cells = <2>;
d2e8190b 726 clocks = <&pioC_clk>;
c9d0f317
JCPV		 727 };
728
729 pioD: gpio@fffff800 {
730 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
731 reg = <0xfffff800 0x100>;
5e8b3bc3 732 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 733 #gpio-cells = <2>;
734 gpio-controller;
735 interrupt-controller;
736 #interrupt-cells = <2>;
d2e8190b 737 clocks = <&pioD_clk>;
c9d0f317
JCPV		 738 };
739
740 pioE: gpio@fffffa00 {
741 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
742 reg = <0xfffffa00 0x100>;
5e8b3bc3 743 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 744 #gpio-cells = <2>;
745 gpio-controller;
746 interrupt-controller;
747 #interrupt-cells = <2>;
d2e8190b 748 clocks = <&pioE_clk>;
c9d0f317 749 };
655ff266
LD		 750 };
751
752 pmc: pmc@fffffc00 {
d2e8190b 753 compatible = "atmel,sama5d3-pmc";
655ff266 754 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 755 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
756 interrupt-controller;
757 #address-cells = <1>;
758 #size-cells = <0>;
759 #interrupt-cells = <1>;
760
761 clk32k: slck {
762 compatible = "fixed-clock";
763 #clock-cells = <0>;
764 clock-frequency = <32768>;
765 };
766
767 main: mainck {
768 compatible = "atmel,at91rm9200-clk-main";
769 #clock-cells = <0>;
770 interrupt-parent = <&pmc>;
771 interrupts = <AT91_PMC_MOSCS>;
772 clocks = <&clk32k>;
773 };
774
775 plla: pllack {
776 compatible = "atmel,sama5d3-clk-pll";
777 #clock-cells = <0>;
778 interrupt-parent = <&pmc>;
779 interrupts = <AT91_PMC_LOCKA>;
780 clocks = <&main>;
781 reg = <0>;
782 atmel,clk-input-range = <8000000 50000000>;
783 #atmel,pll-clk-output-range-cells = <4>;
784 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
785 };
786
787 plladiv: plladivck {
788 compatible = "atmel,at91sam9x5-clk-plldiv";
789 #clock-cells = <0>;
790 clocks = <&plla>;
791 };
792
793 utmi: utmick {
794 compatible = "atmel,at91sam9x5-clk-utmi";
795 #clock-cells = <0>;
796 interrupt-parent = <&pmc>;
797 interrupts = <AT91_PMC_LOCKU>;
798 clocks = <&main>;
799 };
800
801 mck: masterck {
802 compatible = "atmel,at91sam9x5-clk-master";
803 #clock-cells = <0>;
804 interrupt-parent = <&pmc>;
805 interrupts = <AT91_PMC_MCKRDY>;
806 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
807 atmel,clk-output-range = <0 166000000>;
808 atmel,clk-divisors = <1 2 4 3>;
809 };
810
811 usb: usbck {
812 compatible = "atmel,at91sam9x5-clk-usb";
813 #clock-cells = <0>;
814 clocks = <&plladiv>, <&utmi>;
815 };
816
817 prog: progck {
818 compatible = "atmel,at91sam9x5-clk-programmable";
819 #address-cells = <1>;
820 #size-cells = <0>;
821 interrupt-parent = <&pmc>;
822 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
823
824 prog0: prog0 {
825 #clock-cells = <0>;
826 reg = <0>;
827 interrupts = <AT91_PMC_PCKRDY(0)>;
828 };
829
830 prog1: prog1 {
831 #clock-cells = <0>;
832 reg = <1>;
833 interrupts = <AT91_PMC_PCKRDY(1)>;
834 };
835
836 prog2: prog2 {
837 #clock-cells = <0>;
838 reg = <2>;
839 interrupts = <AT91_PMC_PCKRDY(2)>;
840 };
841 };
842
843 smd: smdclk {
844 compatible = "atmel,at91sam9x5-clk-smd";
845 #clock-cells = <0>;
846 clocks = <&plladiv>, <&utmi>;
847 };
848
849 systemck {
850 compatible = "atmel,at91rm9200-clk-system";
851 #address-cells = <1>;
852 #size-cells = <0>;
853
854 ddrck: ddrck {
855 #clock-cells = <0>;
856 reg = <2>;
857 clocks = <&mck>;
858 };
859
860 smdck: smdck {
861 #clock-cells = <0>;
862 reg = <4>;
863 clocks = <&smd>;
864 };
865
866 uhpck: uhpck {
867 #clock-cells = <0>;
868 reg = <6>;
869 clocks = <&usb>;
870 };
871
872 udpck: udpck {
873 #clock-cells = <0>;
874 reg = <7>;
875 clocks = <&usb>;
876 };
877
878 pck0: pck0 {
879 #clock-cells = <0>;
880 reg = <8>;
881 clocks = <&prog0>;
882 };
883
884 pck1: pck1 {
885 #clock-cells = <0>;
886 reg = <9>;
887 clocks = <&prog1>;
888 };
889
890 pck2: pck2 {
891 #clock-cells = <0>;
892 reg = <10>;
893 clocks = <&prog2>;
894 };
895 };
896
897 periphck {
898 compatible = "atmel,at91sam9x5-clk-peripheral";
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&mck>;
902
903 dbgu_clk: dbgu_clk {
904 #clock-cells = <0>;
905 reg = <2>;
906 };
907
908 pioA_clk: pioA_clk {
909 #clock-cells = <0>;
910 reg = <6>;
911 };
912
913 pioB_clk: pioB_clk {
914 #clock-cells = <0>;
915 reg = <7>;
916 };
917
918 pioC_clk: pioC_clk {
919 #clock-cells = <0>;
920 reg = <8>;
921 };
922
923 pioD_clk: pioD_clk {
924 #clock-cells = <0>;
925 reg = <9>;
926 };
927
928 pioE_clk: pioE_clk {
929 #clock-cells = <0>;
930 reg = <10>;
931 };
932
933 usart0_clk: usart0_clk {
934 #clock-cells = <0>;
935 reg = <12>;
936 atmel,clk-output-range = <0 66000000>;
937 };
938
939 usart1_clk: usart1_clk {
940 #clock-cells = <0>;
941 reg = <13>;
942 atmel,clk-output-range = <0 66000000>;
943 };
944
945 usart2_clk: usart2_clk {
946 #clock-cells = <0>;
947 reg = <14>;
948 atmel,clk-output-range = <0 66000000>;
949 };
950
951 usart3_clk: usart3_clk {
952 #clock-cells = <0>;
953 reg = <15>;
954 atmel,clk-output-range = <0 66000000>;
955 };
956
957 twi0_clk: twi0_clk {
958 reg = <18>;
959 #clock-cells = <0>;
960 atmel,clk-output-range = <0 16625000>;
961 };
962
963 twi1_clk: twi1_clk {
964 #clock-cells = <0>;
965 reg = <19>;
966 atmel,clk-output-range = <0 16625000>;
967 };
968
969 twi2_clk: twi2_clk {
970 #clock-cells = <0>;
971 reg = <20>;
972 atmel,clk-output-range = <0 16625000>;
973 };
974
975 mci0_clk: mci0_clk {
976 #clock-cells = <0>;
977 reg = <21>;
978 };
979
980 mci1_clk: mci1_clk {
981 #clock-cells = <0>;
982 reg = <22>;
983 };
984
985 spi0_clk: spi0_clk {
986 #clock-cells = <0>;
987 reg = <24>;
988 atmel,clk-output-range = <0 133000000>;
989 };
990
991 spi1_clk: spi1_clk {
992 #clock-cells = <0>;
993 reg = <25>;
994 atmel,clk-output-range = <0 133000000>;
995 };
996
997 tcb0_clk: tcb0_clk {
998 #clock-cells = <0>;
999 reg = <26>;
1000 atmel,clk-output-range = <0 133000000>;
1001 };
1002
1003 pwm_clk: pwm_clk {
1004 #clock-cells = <0>;
1005 reg = <28>;
1006 };
1007
1008 adc_clk: adc_clk {
1009 #clock-cells = <0>;
1010 reg = <29>;
1011 atmel,clk-output-range = <0 66000000>;
1012 };
1013
1014 dma0_clk: dma0_clk {
1015 #clock-cells = <0>;
1016 reg = <30>;
1017 };
1018
1019 dma1_clk: dma1_clk {
1020 #clock-cells = <0>;
1021 reg = <31>;
1022 };
1023
1024 uhphs_clk: uhphs_clk {
1025 #clock-cells = <0>;
1026 reg = <32>;
1027 };
1028
1029 udphs_clk: udphs_clk {
1030 #clock-cells = <0>;
1031 reg = <33>;
1032 };
1033
1034 isi_clk: isi_clk {
1035 #clock-cells = <0>;
1036 reg = <37>;
1037 };
1038
1039 ssc0_clk: ssc0_clk {
1040 #clock-cells = <0>;
1041 reg = <38>;
1042 atmel,clk-output-range = <0 66000000>;
1043 };
1044
1045 ssc1_clk: ssc1_clk {
1046 #clock-cells = <0>;
1047 reg = <39>;
1048 atmel,clk-output-range = <0 66000000>;
1049 };
1050
1051 sha_clk: sha_clk {
1052 #clock-cells = <0>;
1053 reg = <42>;
1054 };
1055
1056 aes_clk: aes_clk {
1057 #clock-cells = <0>;
1058 reg = <43>;
1059 };
1060
1061 tdes_clk: tdes_clk {
1062 #clock-cells = <0>;
1063 reg = <44>;
1064 };
1065
1066 trng_clk: trng_clk {
1067 #clock-cells = <0>;
1068 reg = <45>;
1069 };
1070
1071 fuse_clk: fuse_clk {
1072 #clock-cells = <0>;
1073 reg = <48>;
1074 };
1075 };
655ff266
LD		 1076 };
1077
1078 rstc@fffffe00 {
1079 compatible = "atmel,at91sam9g45-rstc";
1080 reg = <0xfffffe00 0x10>;
1081 };
1082
1083 pit: timer@fffffe30 {
1084 compatible = "atmel,at91sam9260-pit";
1085 reg = <0xfffffe30 0xf>;
5e8b3bc3 1086 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1087 clocks = <&mck>;
655ff266
LD		 1088 };
1089
1090 watchdog@fffffe40 {
1091 compatible = "atmel,at91sam9260-wdt";
1092 reg = <0xfffffe40 0x10>;
1093 status = "disabled";
1094 };
1095
1096 rtc@fffffeb0 {
1097 compatible = "atmel,at91rm9200-rtc";
1098 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1099 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1100 };
1101 };
1102
1103 usb0: gadget@00500000 {
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 compatible = "atmel,at91sam9rl-udc";
1107 reg = <0x00500000 0x100000
1108 0xf8030000 0x4000>;
5e8b3bc3 1109 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1110 clocks = <&udphs_clk>, <&utmi>;
1111 clock-names = "pclk", "hclk";
655ff266
LD		 1112 status = "disabled";
1113
1114 ep0 {
1115 reg = <0>;
1116 atmel,fifo-size = <64>;
1117 atmel,nb-banks = <1>;
1118 };
1119
1120 ep1 {
1121 reg = <1>;
1122 atmel,fifo-size = <1024>;
1123 atmel,nb-banks = <3>;
1124 atmel,can-dma;
1125 atmel,can-isoc;
1126 };
1127
1128 ep2 {
1129 reg = <2>;
1130 atmel,fifo-size = <1024>;
1131 atmel,nb-banks = <3>;
1132 atmel,can-dma;
1133 atmel,can-isoc;
1134 };
1135
1136 ep3 {
1137 reg = <3>;
1138 atmel,fifo-size = <1024>;
1139 atmel,nb-banks = <2>;
1140 atmel,can-dma;
1141 };
1142
1143 ep4 {
1144 reg = <4>;
1145 atmel,fifo-size = <1024>;
1146 atmel,nb-banks = <2>;
1147 atmel,can-dma;
1148 };
1149
1150 ep5 {
1151 reg = <5>;
1152 atmel,fifo-size = <1024>;
1153 atmel,nb-banks = <2>;
1154 atmel,can-dma;
1155 };
1156
1157 ep6 {
1158 reg = <6>;
1159 atmel,fifo-size = <1024>;
1160 atmel,nb-banks = <2>;
1161 atmel,can-dma;
1162 };
1163
1164 ep7 {
1165 reg = <7>;
1166 atmel,fifo-size = <1024>;
1167 atmel,nb-banks = <2>;
1168 atmel,can-dma;
1169 };
1170
1171 ep8 {
1172 reg = <8>;
1173 atmel,fifo-size = <1024>;
1174 atmel,nb-banks = <2>;
1175 };
1176
1177 ep9 {
1178 reg = <9>;
1179 atmel,fifo-size = <1024>;
1180 atmel,nb-banks = <2>;
1181 };
1182
1183 ep10 {
1184 reg = <10>;
1185 atmel,fifo-size = <1024>;
1186 atmel,nb-banks = <2>;
1187 };
1188
1189 ep11 {
1190 reg = <11>;
1191 atmel,fifo-size = <1024>;
1192 atmel,nb-banks = <2>;
1193 };
1194
1195 ep12 {
1196 reg = <12>;
1197 atmel,fifo-size = <1024>;
1198 atmel,nb-banks = <2>;
1199 };
1200
1201 ep13 {
1202 reg = <13>;
1203 atmel,fifo-size = <1024>;
1204 atmel,nb-banks = <2>;
1205 };
1206
1207 ep14 {
1208 reg = <14>;
1209 atmel,fifo-size = <1024>;
1210 atmel,nb-banks = <2>;
1211 };
1212
1213 ep15 {
1214 reg = <15>;
1215 atmel,fifo-size = <1024>;
1216 atmel,nb-banks = <2>;
1217 };
1218 };
1219
1220 usb1: ohci@00600000 {
1221 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1222 reg = <0x00600000 0x100000>;
5e8b3bc3 1223 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1224 clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1225 <&uhpck>;
1226 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1227 status = "disabled";
1228 };
1229
1230 usb2: ehci@00700000 {
1231 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1232 reg = <0x00700000 0x100000>;
5e8b3bc3 1233 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1234 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1235 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1236 status = "disabled";
1237 };
1238
1239 nand0: nand@60000000 {
1240 compatible = "atmel,at91rm9200-nand";
1241 #address-cells = <1>;
1242 #size-cells = <1>;
8ae599ef 1243 ranges;
655ff266
LD		 1244 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1245 0xffffc070 0x00000490 /* SMC PMECC regs */
1246 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1247 0x00110000 0x00018000 /* ROM code */
655ff266 1248 >;
5e8b3bc3 1249 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1250 atmel,nand-addr-offset = <21>;
1251 atmel,nand-cmd-offset = <22>;
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1254 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1255 status = "disabled";
8ae599ef
JW		 1256
1257 nfc@70000000 {
1258 compatible = "atmel,sama5d3-nfc";
1259 #address-cells = <1>;
1260 #size-cells = <1>;
1261 reg = <
1262 0x70000000 0x10000000 /* NFC Command Registers */
1263 0xffffc000 0x00000070 /* NFC HSMC regs */
1264 0x00200000 0x00100000 /* NFC SRAM banks */
1265 >;
1266 };
655ff266
LD		 1267 };
1268 };
1269};
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