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Commit | Line | Data |
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66314223 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera <www.altera.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
7da9b436 | 18 | #include "skeleton.dtsi" |
16fb4f8b | 19 | #include <dt-bindings/reset/altr,rst-mgr.h> |
66314223 DN |
20 | |
21 | / { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | ||
25 | aliases { | |
26 | ethernet0 = &gmac0; | |
3d954cf1 | 27 | ethernet1 = &gmac1; |
66314223 DN |
28 | serial0 = &uart0; |
29 | serial1 = &uart1; | |
c2ad2844 DN |
30 | timer0 = &timer0; |
31 | timer1 = &timer1; | |
32 | timer2 = &timer2; | |
33 | timer3 = &timer3; | |
66314223 DN |
34 | }; |
35 | ||
36 | cpus { | |
37 | #address-cells = <1>; | |
38 | #size-cells = <0>; | |
39 | ||
40 | cpu@0 { | |
41 | compatible = "arm,cortex-a9"; | |
42 | device_type = "cpu"; | |
43 | reg = <0>; | |
44 | next-level-cache = <&L2>; | |
45 | }; | |
46 | cpu@1 { | |
47 | compatible = "arm,cortex-a9"; | |
48 | device_type = "cpu"; | |
49 | reg = <1>; | |
50 | next-level-cache = <&L2>; | |
51 | }; | |
52 | }; | |
53 | ||
54 | intc: intc@fffed000 { | |
55 | compatible = "arm,cortex-a9-gic"; | |
56 | #interrupt-cells = <3>; | |
57 | interrupt-controller; | |
58 | reg = <0xfffed000 0x1000>, | |
59 | <0xfffec100 0x100>; | |
60 | }; | |
61 | ||
62 | soc { | |
63 | #address-cells = <1>; | |
64 | #size-cells = <1>; | |
65 | compatible = "simple-bus"; | |
66 | device_type = "soc"; | |
67 | interrupt-parent = <&intc>; | |
68 | ranges; | |
69 | ||
70 | amba { | |
71 | compatible = "arm,amba-bus"; | |
72 | #address-cells = <1>; | |
73 | #size-cells = <1>; | |
74 | ranges; | |
75 | ||
76 | pdma: pdma@ffe01000 { | |
77 | compatible = "arm,pl330", "arm,primecell"; | |
78 | reg = <0xffe01000 0x1000>; | |
18d56199 ST |
79 | interrupts = <0 104 4>, |
80 | <0 105 4>, | |
81 | <0 106 4>, | |
82 | <0 107 4>, | |
83 | <0 108 4>, | |
84 | <0 109 4>, | |
85 | <0 110 4>, | |
86 | <0 111 4>; | |
0d8abbfd PV |
87 | #dma-cells = <1>; |
88 | #dma-channels = <8>; | |
89 | #dma-requests = <32>; | |
672ef909 ST |
90 | clocks = <&l4_main_clk>; |
91 | clock-names = "apb_pclk"; | |
66314223 DN |
92 | }; |
93 | }; | |
94 | ||
36fe3f54 ST |
95 | can0: can@ffc00000 { |
96 | compatible = "bosch,d_can"; | |
97 | reg = <0xffc00000 0x1000>; | |
98 | interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; | |
99 | clocks = <&can0_clk>; | |
100 | status = "disabled"; | |
101 | }; | |
102 | ||
103 | can1: can@ffc01000 { | |
104 | compatible = "bosch,d_can"; | |
105 | reg = <0xffc01000 0x1000>; | |
106 | interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; | |
107 | clocks = <&can1_clk>; | |
108 | status = "disabled"; | |
109 | }; | |
110 | ||
042000b0 DN |
111 | clkmgr@ffd04000 { |
112 | compatible = "altr,clk-mgr"; | |
113 | reg = <0xffd04000 0x1000>; | |
114 | ||
115 | clocks { | |
116 | #address-cells = <1>; | |
117 | #size-cells = <0>; | |
118 | ||
f1ce1a99 DN |
119 | osc1: osc1 { |
120 | #clock-cells = <0>; | |
121 | compatible = "fixed-clock"; | |
122 | }; | |
123 | ||
124 | osc2: osc2 { | |
042000b0 DN |
125 | #clock-cells = <0>; |
126 | compatible = "fixed-clock"; | |
127 | }; | |
128 | ||
a92b83af DN |
129 | f2s_periph_ref_clk: f2s_periph_ref_clk { |
130 | #clock-cells = <0>; | |
131 | compatible = "fixed-clock"; | |
f1ce1a99 DN |
132 | }; |
133 | ||
134 | f2s_sdram_ref_clk: f2s_sdram_ref_clk { | |
135 | #clock-cells = <0>; | |
136 | compatible = "fixed-clock"; | |
a92b83af DN |
137 | }; |
138 | ||
042000b0 DN |
139 | main_pll: main_pll { |
140 | #address-cells = <1>; | |
141 | #size-cells = <0>; | |
142 | #clock-cells = <0>; | |
143 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 144 | clocks = <&osc1>; |
042000b0 DN |
145 | reg = <0x40>; |
146 | ||
147 | mpuclk: mpuclk { | |
148 | #clock-cells = <0>; | |
149 | compatible = "altr,socfpga-perip-clk"; | |
150 | clocks = <&main_pll>; | |
8cb289ed | 151 | div-reg = <0xe0 0 9>; |
042000b0 DN |
152 | reg = <0x48>; |
153 | }; | |
154 | ||
155 | mainclk: mainclk { | |
156 | #clock-cells = <0>; | |
157 | compatible = "altr,socfpga-perip-clk"; | |
158 | clocks = <&main_pll>; | |
8cb289ed | 159 | div-reg = <0xe4 0 9>; |
042000b0 DN |
160 | reg = <0x4C>; |
161 | }; | |
162 | ||
163 | dbg_base_clk: dbg_base_clk { | |
164 | #clock-cells = <0>; | |
165 | compatible = "altr,socfpga-perip-clk"; | |
166 | clocks = <&main_pll>; | |
8cb289ed | 167 | div-reg = <0xe8 0 9>; |
042000b0 DN |
168 | reg = <0x50>; |
169 | }; | |
170 | ||
171 | main_qspi_clk: main_qspi_clk { | |
172 | #clock-cells = <0>; | |
173 | compatible = "altr,socfpga-perip-clk"; | |
174 | clocks = <&main_pll>; | |
175 | reg = <0x54>; | |
176 | }; | |
177 | ||
178 | main_nand_sdmmc_clk: main_nand_sdmmc_clk { | |
179 | #clock-cells = <0>; | |
180 | compatible = "altr,socfpga-perip-clk"; | |
181 | clocks = <&main_pll>; | |
182 | reg = <0x58>; | |
183 | }; | |
184 | ||
01ed80b0 | 185 | cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { |
042000b0 DN |
186 | #clock-cells = <0>; |
187 | compatible = "altr,socfpga-perip-clk"; | |
188 | clocks = <&main_pll>; | |
189 | reg = <0x5C>; | |
190 | }; | |
191 | }; | |
192 | ||
193 | periph_pll: periph_pll { | |
194 | #address-cells = <1>; | |
195 | #size-cells = <0>; | |
196 | #clock-cells = <0>; | |
197 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 198 | clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; |
042000b0 DN |
199 | reg = <0x80>; |
200 | ||
201 | emac0_clk: emac0_clk { | |
202 | #clock-cells = <0>; | |
203 | compatible = "altr,socfpga-perip-clk"; | |
204 | clocks = <&periph_pll>; | |
205 | reg = <0x88>; | |
206 | }; | |
207 | ||
208 | emac1_clk: emac1_clk { | |
209 | #clock-cells = <0>; | |
210 | compatible = "altr,socfpga-perip-clk"; | |
211 | clocks = <&periph_pll>; | |
212 | reg = <0x8C>; | |
213 | }; | |
214 | ||
215 | per_qspi_clk: per_qsi_clk { | |
216 | #clock-cells = <0>; | |
217 | compatible = "altr,socfpga-perip-clk"; | |
218 | clocks = <&periph_pll>; | |
219 | reg = <0x90>; | |
220 | }; | |
221 | ||
222 | per_nand_mmc_clk: per_nand_mmc_clk { | |
223 | #clock-cells = <0>; | |
224 | compatible = "altr,socfpga-perip-clk"; | |
225 | clocks = <&periph_pll>; | |
226 | reg = <0x94>; | |
227 | }; | |
228 | ||
229 | per_base_clk: per_base_clk { | |
230 | #clock-cells = <0>; | |
231 | compatible = "altr,socfpga-perip-clk"; | |
232 | clocks = <&periph_pll>; | |
233 | reg = <0x98>; | |
234 | }; | |
235 | ||
01ed80b0 | 236 | h2f_usr1_clk: h2f_usr1_clk { |
042000b0 DN |
237 | #clock-cells = <0>; |
238 | compatible = "altr,socfpga-perip-clk"; | |
239 | clocks = <&periph_pll>; | |
240 | reg = <0x9C>; | |
241 | }; | |
242 | }; | |
243 | ||
244 | sdram_pll: sdram_pll { | |
245 | #address-cells = <1>; | |
246 | #size-cells = <0>; | |
247 | #clock-cells = <0>; | |
248 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 249 | clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; |
042000b0 DN |
250 | reg = <0xC0>; |
251 | ||
252 | ddr_dqs_clk: ddr_dqs_clk { | |
253 | #clock-cells = <0>; | |
254 | compatible = "altr,socfpga-perip-clk"; | |
255 | clocks = <&sdram_pll>; | |
256 | reg = <0xC8>; | |
257 | }; | |
258 | ||
259 | ddr_2x_dqs_clk: ddr_2x_dqs_clk { | |
260 | #clock-cells = <0>; | |
261 | compatible = "altr,socfpga-perip-clk"; | |
262 | clocks = <&sdram_pll>; | |
263 | reg = <0xCC>; | |
264 | }; | |
265 | ||
266 | ddr_dq_clk: ddr_dq_clk { | |
267 | #clock-cells = <0>; | |
268 | compatible = "altr,socfpga-perip-clk"; | |
269 | clocks = <&sdram_pll>; | |
270 | reg = <0xD0>; | |
271 | }; | |
272 | ||
01ed80b0 | 273 | h2f_usr2_clk: h2f_usr2_clk { |
042000b0 DN |
274 | #clock-cells = <0>; |
275 | compatible = "altr,socfpga-perip-clk"; | |
276 | clocks = <&sdram_pll>; | |
277 | reg = <0xD4>; | |
278 | }; | |
279 | }; | |
a92b83af | 280 | |
7857d560 ST |
281 | mpu_periph_clk: mpu_periph_clk { |
282 | #clock-cells = <0>; | |
a5c6e87a | 283 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
284 | clocks = <&mpuclk>; |
285 | fixed-divider = <4>; | |
a92b83af DN |
286 | }; |
287 | ||
7857d560 ST |
288 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
289 | #clock-cells = <0>; | |
a5c6e87a | 290 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
291 | clocks = <&mpuclk>; |
292 | fixed-divider = <2>; | |
a92b83af DN |
293 | }; |
294 | ||
7857d560 ST |
295 | l4_main_clk: l4_main_clk { |
296 | #clock-cells = <0>; | |
297 | compatible = "altr,socfpga-gate-clk"; | |
298 | clocks = <&mainclk>; | |
299 | clk-gate = <0x60 0>; | |
a92b83af DN |
300 | }; |
301 | ||
7857d560 ST |
302 | l3_main_clk: l3_main_clk { |
303 | #clock-cells = <0>; | |
a5c6e87a | 304 | compatible = "altr,socfpga-perip-clk"; |
7857d560 | 305 | clocks = <&mainclk>; |
a5c6e87a | 306 | fixed-divider = <1>; |
a92b83af DN |
307 | }; |
308 | ||
7857d560 ST |
309 | l3_mp_clk: l3_mp_clk { |
310 | #clock-cells = <0>; | |
311 | compatible = "altr,socfpga-gate-clk"; | |
312 | clocks = <&mainclk>; | |
313 | div-reg = <0x64 0 2>; | |
314 | clk-gate = <0x60 1>; | |
a92b83af DN |
315 | }; |
316 | ||
7857d560 ST |
317 | l3_sp_clk: l3_sp_clk { |
318 | #clock-cells = <0>; | |
319 | compatible = "altr,socfpga-gate-clk"; | |
320 | clocks = <&mainclk>; | |
321 | div-reg = <0x64 2 2>; | |
322 | }; | |
a92b83af | 323 | |
7857d560 ST |
324 | l4_mp_clk: l4_mp_clk { |
325 | #clock-cells = <0>; | |
326 | compatible = "altr,socfpga-gate-clk"; | |
327 | clocks = <&mainclk>, <&per_base_clk>; | |
328 | div-reg = <0x64 4 3>; | |
329 | clk-gate = <0x60 2>; | |
a92b83af DN |
330 | }; |
331 | ||
7857d560 ST |
332 | l4_sp_clk: l4_sp_clk { |
333 | #clock-cells = <0>; | |
334 | compatible = "altr,socfpga-gate-clk"; | |
335 | clocks = <&mainclk>, <&per_base_clk>; | |
336 | div-reg = <0x64 7 3>; | |
337 | clk-gate = <0x60 3>; | |
a92b83af DN |
338 | }; |
339 | ||
7857d560 ST |
340 | dbg_at_clk: dbg_at_clk { |
341 | #clock-cells = <0>; | |
342 | compatible = "altr,socfpga-gate-clk"; | |
343 | clocks = <&dbg_base_clk>; | |
344 | div-reg = <0x68 0 2>; | |
345 | clk-gate = <0x60 4>; | |
a92b83af DN |
346 | }; |
347 | ||
7857d560 ST |
348 | dbg_clk: dbg_clk { |
349 | #clock-cells = <0>; | |
350 | compatible = "altr,socfpga-gate-clk"; | |
351 | clocks = <&dbg_base_clk>; | |
352 | div-reg = <0x68 2 2>; | |
353 | clk-gate = <0x60 5>; | |
a92b83af DN |
354 | }; |
355 | ||
7857d560 ST |
356 | dbg_trace_clk: dbg_trace_clk { |
357 | #clock-cells = <0>; | |
358 | compatible = "altr,socfpga-gate-clk"; | |
359 | clocks = <&dbg_base_clk>; | |
360 | div-reg = <0x6C 0 3>; | |
361 | clk-gate = <0x60 6>; | |
a92b83af DN |
362 | }; |
363 | ||
7857d560 ST |
364 | dbg_timer_clk: dbg_timer_clk { |
365 | #clock-cells = <0>; | |
366 | compatible = "altr,socfpga-gate-clk"; | |
367 | clocks = <&dbg_base_clk>; | |
368 | clk-gate = <0x60 7>; | |
a92b83af DN |
369 | }; |
370 | ||
7857d560 ST |
371 | cfg_clk: cfg_clk { |
372 | #clock-cells = <0>; | |
373 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 374 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 375 | clk-gate = <0x60 8>; |
a92b83af DN |
376 | }; |
377 | ||
01ed80b0 | 378 | h2f_user0_clk: h2f_user0_clk { |
7857d560 ST |
379 | #clock-cells = <0>; |
380 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 381 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 382 | clk-gate = <0x60 9>; |
a92b83af DN |
383 | }; |
384 | ||
7857d560 ST |
385 | emac_0_clk: emac_0_clk { |
386 | #clock-cells = <0>; | |
387 | compatible = "altr,socfpga-gate-clk"; | |
388 | clocks = <&emac0_clk>; | |
389 | clk-gate = <0xa0 0>; | |
a92b83af DN |
390 | }; |
391 | ||
7857d560 ST |
392 | emac_1_clk: emac_1_clk { |
393 | #clock-cells = <0>; | |
394 | compatible = "altr,socfpga-gate-clk"; | |
395 | clocks = <&emac1_clk>; | |
396 | clk-gate = <0xa0 1>; | |
a92b83af DN |
397 | }; |
398 | ||
7857d560 ST |
399 | usb_mp_clk: usb_mp_clk { |
400 | #clock-cells = <0>; | |
401 | compatible = "altr,socfpga-gate-clk"; | |
402 | clocks = <&per_base_clk>; | |
403 | clk-gate = <0xa0 2>; | |
404 | div-reg = <0xa4 0 3>; | |
a92b83af DN |
405 | }; |
406 | ||
7857d560 ST |
407 | spi_m_clk: spi_m_clk { |
408 | #clock-cells = <0>; | |
409 | compatible = "altr,socfpga-gate-clk"; | |
410 | clocks = <&per_base_clk>; | |
411 | clk-gate = <0xa0 3>; | |
412 | div-reg = <0xa4 3 3>; | |
a92b83af DN |
413 | }; |
414 | ||
7857d560 ST |
415 | can0_clk: can0_clk { |
416 | #clock-cells = <0>; | |
417 | compatible = "altr,socfpga-gate-clk"; | |
418 | clocks = <&per_base_clk>; | |
419 | clk-gate = <0xa0 4>; | |
420 | div-reg = <0xa4 6 3>; | |
a92b83af DN |
421 | }; |
422 | ||
7857d560 ST |
423 | can1_clk: can1_clk { |
424 | #clock-cells = <0>; | |
425 | compatible = "altr,socfpga-gate-clk"; | |
426 | clocks = <&per_base_clk>; | |
427 | clk-gate = <0xa0 5>; | |
428 | div-reg = <0xa4 9 3>; | |
a92b83af DN |
429 | }; |
430 | ||
7857d560 ST |
431 | gpio_db_clk: gpio_db_clk { |
432 | #clock-cells = <0>; | |
433 | compatible = "altr,socfpga-gate-clk"; | |
434 | clocks = <&per_base_clk>; | |
435 | clk-gate = <0xa0 6>; | |
436 | div-reg = <0xa8 0 24>; | |
a92b83af DN |
437 | }; |
438 | ||
01ed80b0 | 439 | h2f_user1_clk: h2f_user1_clk { |
7857d560 ST |
440 | #clock-cells = <0>; |
441 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 442 | clocks = <&h2f_usr1_clk>; |
7857d560 | 443 | clk-gate = <0xa0 7>; |
a92b83af DN |
444 | }; |
445 | ||
7857d560 ST |
446 | sdmmc_clk: sdmmc_clk { |
447 | #clock-cells = <0>; | |
448 | compatible = "altr,socfpga-gate-clk"; | |
449 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
450 | clk-gate = <0xa0 8>; | |
044abbde | 451 | clk-phase = <0 135>; |
a92b83af DN |
452 | }; |
453 | ||
7857d560 ST |
454 | nand_x_clk: nand_x_clk { |
455 | #clock-cells = <0>; | |
456 | compatible = "altr,socfpga-gate-clk"; | |
457 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
458 | clk-gate = <0xa0 9>; | |
a92b83af DN |
459 | }; |
460 | ||
7857d560 ST |
461 | nand_clk: nand_clk { |
462 | #clock-cells = <0>; | |
463 | compatible = "altr,socfpga-gate-clk"; | |
464 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
465 | clk-gate = <0xa0 10>; | |
466 | fixed-divider = <4>; | |
a92b83af DN |
467 | }; |
468 | ||
7857d560 ST |
469 | qspi_clk: qspi_clk { |
470 | #clock-cells = <0>; | |
471 | compatible = "altr,socfpga-gate-clk"; | |
472 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | |
473 | clk-gate = <0xa0 11>; | |
a92b83af | 474 | }; |
042000b0 DN |
475 | }; |
476 | }; | |
477 | ||
3d954cf1 | 478 | gmac0: ethernet@ff700000 { |
66314223 | 479 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
2755e187 | 480 | altr,sysmgr-syscon = <&sysmgr 0x60 0>; |
66314223 DN |
481 | reg = <0xff700000 0x2000>; |
482 | interrupts = <0 115 4>; | |
483 | interrupt-names = "macirq"; | |
484 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
3d954cf1 DN |
485 | clocks = <&emac0_clk>; |
486 | clock-names = "stmmaceth"; | |
16fb4f8b ST |
487 | resets = <&rst EMAC0_RESET>; |
488 | reset-names = "stmmaceth"; | |
ea6856e3 VB |
489 | snps,multicast-filter-bins = <256>; |
490 | snps,perfect-filter-entries = <128>; | |
3d954cf1 DN |
491 | status = "disabled"; |
492 | }; | |
493 | ||
494 | gmac1: ethernet@ff702000 { | |
495 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | |
2755e187 | 496 | altr,sysmgr-syscon = <&sysmgr 0x60 2>; |
3d954cf1 DN |
497 | reg = <0xff702000 0x2000>; |
498 | interrupts = <0 120 4>; | |
499 | interrupt-names = "macirq"; | |
500 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
501 | clocks = <&emac1_clk>; | |
502 | clock-names = "stmmaceth"; | |
16fb4f8b ST |
503 | resets = <&rst EMAC1_RESET>; |
504 | reset-names = "stmmaceth"; | |
ea6856e3 VB |
505 | snps,multicast-filter-bins = <256>; |
506 | snps,perfect-filter-entries = <128>; | |
3d954cf1 | 507 | status = "disabled"; |
66314223 DN |
508 | }; |
509 | ||
fdeda156 ST |
510 | i2c0: i2c@ffc04000 { |
511 | #address-cells = <1>; | |
512 | #size-cells = <0>; | |
513 | compatible = "snps,designware-i2c"; | |
514 | reg = <0xffc04000 0x1000>; | |
515 | clocks = <&l4_sp_clk>; | |
516 | interrupts = <0 158 0x4>; | |
517 | status = "disabled"; | |
518 | }; | |
519 | ||
520 | i2c1: i2c@ffc05000 { | |
521 | #address-cells = <1>; | |
522 | #size-cells = <0>; | |
523 | compatible = "snps,designware-i2c"; | |
524 | reg = <0xffc05000 0x1000>; | |
525 | clocks = <&l4_sp_clk>; | |
526 | interrupts = <0 159 0x4>; | |
527 | status = "disabled"; | |
528 | }; | |
529 | ||
530 | i2c2: i2c@ffc06000 { | |
531 | #address-cells = <1>; | |
532 | #size-cells = <0>; | |
533 | compatible = "snps,designware-i2c"; | |
534 | reg = <0xffc06000 0x1000>; | |
535 | clocks = <&l4_sp_clk>; | |
536 | interrupts = <0 160 0x4>; | |
537 | status = "disabled"; | |
538 | }; | |
539 | ||
540 | i2c3: i2c@ffc07000 { | |
541 | #address-cells = <1>; | |
542 | #size-cells = <0>; | |
543 | compatible = "snps,designware-i2c"; | |
544 | reg = <0xffc07000 0x1000>; | |
545 | clocks = <&l4_sp_clk>; | |
546 | interrupts = <0 161 0x4>; | |
547 | status = "disabled"; | |
548 | }; | |
549 | ||
d11ac1d2 | 550 | gpio0: gpio@ff708000 { |
6ec08c71 SAS |
551 | #address-cells = <1>; |
552 | #size-cells = <0>; | |
553 | compatible = "snps,dw-apb-gpio"; | |
554 | reg = <0xff708000 0x1000>; | |
555 | clocks = <&per_base_clk>; | |
556 | status = "disabled"; | |
557 | ||
d11ac1d2 | 558 | porta: gpio-controller@0 { |
6ec08c71 SAS |
559 | compatible = "snps,dw-apb-gpio-port"; |
560 | gpio-controller; | |
561 | #gpio-cells = <2>; | |
562 | snps,nr-gpios = <29>; | |
563 | reg = <0>; | |
564 | interrupt-controller; | |
565 | #interrupt-cells = <2>; | |
566 | interrupts = <0 164 4>; | |
567 | }; | |
568 | }; | |
569 | ||
d11ac1d2 | 570 | gpio1: gpio@ff709000 { |
6ec08c71 SAS |
571 | #address-cells = <1>; |
572 | #size-cells = <0>; | |
573 | compatible = "snps,dw-apb-gpio"; | |
574 | reg = <0xff709000 0x1000>; | |
575 | clocks = <&per_base_clk>; | |
576 | status = "disabled"; | |
577 | ||
d11ac1d2 | 578 | portb: gpio-controller@0 { |
6ec08c71 SAS |
579 | compatible = "snps,dw-apb-gpio-port"; |
580 | gpio-controller; | |
581 | #gpio-cells = <2>; | |
582 | snps,nr-gpios = <29>; | |
583 | reg = <0>; | |
584 | interrupt-controller; | |
585 | #interrupt-cells = <2>; | |
586 | interrupts = <0 165 4>; | |
587 | }; | |
588 | }; | |
589 | ||
d11ac1d2 | 590 | gpio2: gpio@ff70a000 { |
6ec08c71 SAS |
591 | #address-cells = <1>; |
592 | #size-cells = <0>; | |
593 | compatible = "snps,dw-apb-gpio"; | |
594 | reg = <0xff70a000 0x1000>; | |
595 | clocks = <&per_base_clk>; | |
596 | status = "disabled"; | |
597 | ||
d11ac1d2 | 598 | portc: gpio-controller@0 { |
6ec08c71 SAS |
599 | compatible = "snps,dw-apb-gpio-port"; |
600 | gpio-controller; | |
601 | #gpio-cells = <2>; | |
602 | snps,nr-gpios = <27>; | |
603 | reg = <0>; | |
604 | interrupt-controller; | |
605 | #interrupt-cells = <2>; | |
606 | interrupts = <0 166 4>; | |
607 | }; | |
608 | }; | |
609 | ||
75a41826 TT |
610 | sdr: sdr@ffc25000 { |
611 | compatible = "syscon"; | |
612 | reg = <0xffc25000 0x1000>; | |
613 | }; | |
614 | ||
615 | sdramedac { | |
616 | compatible = "altr,sdram-edac"; | |
617 | altr,sdr-syscon = <&sdr>; | |
618 | interrupts = <0 39 4>; | |
619 | }; | |
620 | ||
66314223 DN |
621 | L2: l2-cache@fffef000 { |
622 | compatible = "arm,pl310-cache"; | |
623 | reg = <0xfffef000 0x1000>; | |
624 | interrupts = <0 38 0x04>; | |
625 | cache-unified; | |
626 | cache-level = <2>; | |
9a21e55d DN |
627 | arm,tag-latency = <1 1 1>; |
628 | arm,data-latency = <2 1 1>; | |
66314223 DN |
629 | }; |
630 | ||
9b931361 DN |
631 | mmc: dwmmc0@ff704000 { |
632 | compatible = "altr,socfpga-dw-mshc"; | |
633 | reg = <0xff704000 0x1000>; | |
634 | interrupts = <0 139 4>; | |
635 | fifo-depth = <0x400>; | |
636 | #address-cells = <1>; | |
637 | #size-cells = <0>; | |
638 | clocks = <&l4_mp_clk>, <&sdmmc_clk>; | |
639 | clock-names = "biu", "ciu"; | |
640 | }; | |
641 | ||
8b907c8b DN |
642 | ocram: sram@ffff0000 { |
643 | compatible = "mmio-sram"; | |
644 | reg = <0xffff0000 0x10000>; | |
645 | }; | |
646 | ||
ba6b96b3 TT |
647 | spi0: spi@fff00000 { |
648 | compatible = "snps,dw-apb-ssi"; | |
649 | #address-cells = <1>; | |
650 | #size-cells = <0>; | |
651 | reg = <0xfff00000 0x1000>; | |
652 | interrupts = <0 154 4>; | |
653 | num-cs = <4>; | |
654 | clocks = <&spi_m_clk>; | |
655 | status = "disabled"; | |
656 | }; | |
657 | ||
658 | spi1: spi@fff01000 { | |
659 | compatible = "snps,dw-apb-ssi"; | |
660 | #address-cells = <1>; | |
661 | #size-cells = <0>; | |
662 | reg = <0xfff01000 0x1000>; | |
663 | interrupts = <0 156 4>; | |
664 | num-cs = <4>; | |
665 | clocks = <&spi_m_clk>; | |
666 | status = "disabled"; | |
667 | }; | |
668 | ||
66314223 DN |
669 | /* Local timer */ |
670 | timer@fffec600 { | |
671 | compatible = "arm,cortex-a9-twd-timer"; | |
672 | reg = <0xfffec600 0x100>; | |
673 | interrupts = <1 13 0xf04>; | |
159c7f89 | 674 | clocks = <&mpu_periph_clk>; |
66314223 DN |
675 | }; |
676 | ||
c2ad2844 | 677 | timer0: timer0@ffc08000 { |
620f5e1c | 678 | compatible = "snps,dw-apb-timer"; |
66314223 | 679 | interrupts = <0 167 4>; |
66314223 | 680 | reg = <0xffc08000 0x1000>; |
bd785efd DN |
681 | clocks = <&l4_sp_clk>; |
682 | clock-names = "timer"; | |
66314223 DN |
683 | }; |
684 | ||
c2ad2844 | 685 | timer1: timer1@ffc09000 { |
620f5e1c | 686 | compatible = "snps,dw-apb-timer"; |
66314223 | 687 | interrupts = <0 168 4>; |
66314223 | 688 | reg = <0xffc09000 0x1000>; |
bd785efd DN |
689 | clocks = <&l4_sp_clk>; |
690 | clock-names = "timer"; | |
66314223 DN |
691 | }; |
692 | ||
c2ad2844 | 693 | timer2: timer2@ffd00000 { |
620f5e1c | 694 | compatible = "snps,dw-apb-timer"; |
66314223 | 695 | interrupts = <0 169 4>; |
66314223 | 696 | reg = <0xffd00000 0x1000>; |
bd785efd DN |
697 | clocks = <&osc1>; |
698 | clock-names = "timer"; | |
66314223 DN |
699 | }; |
700 | ||
c2ad2844 | 701 | timer3: timer3@ffd01000 { |
620f5e1c | 702 | compatible = "snps,dw-apb-timer"; |
66314223 | 703 | interrupts = <0 170 4>; |
66314223 | 704 | reg = <0xffd01000 0x1000>; |
bd785efd DN |
705 | clocks = <&osc1>; |
706 | clock-names = "timer"; | |
66314223 DN |
707 | }; |
708 | ||
c2ad2844 | 709 | uart0: serial0@ffc02000 { |
66314223 DN |
710 | compatible = "snps,dw-apb-uart"; |
711 | reg = <0xffc02000 0x1000>; | |
66314223 DN |
712 | interrupts = <0 162 4>; |
713 | reg-shift = <2>; | |
714 | reg-io-width = <4>; | |
bd785efd | 715 | clocks = <&l4_sp_clk>; |
66314223 DN |
716 | }; |
717 | ||
c2ad2844 | 718 | uart1: serial1@ffc03000 { |
66314223 DN |
719 | compatible = "snps,dw-apb-uart"; |
720 | reg = <0xffc03000 0x1000>; | |
66314223 DN |
721 | interrupts = <0 163 4>; |
722 | reg-shift = <2>; | |
723 | reg-io-width = <4>; | |
bd785efd | 724 | clocks = <&l4_sp_clk>; |
66314223 | 725 | }; |
9c4566a1 | 726 | |
16fb4f8b | 727 | rst: rstmgr@ffd05000 { |
dc8fbed5 | 728 | #reset-cells = <1>; |
7857d560 ST |
729 | compatible = "altr,rst-mgr"; |
730 | reg = <0xffd05000 0x1000>; | |
731 | }; | |
9c4566a1 | 732 | |
1403250b DN |
733 | usbphy0: usbphy@0 { |
734 | #phy-cells = <0>; | |
735 | compatible = "usb-nop-xceiv"; | |
736 | status = "okay"; | |
737 | }; | |
738 | ||
739 | usb0: usb@ffb00000 { | |
740 | compatible = "snps,dwc2"; | |
741 | reg = <0xffb00000 0xffff>; | |
742 | interrupts = <0 125 4>; | |
743 | clocks = <&usb_mp_clk>; | |
744 | clock-names = "otg"; | |
745 | phys = <&usbphy0>; | |
746 | phy-names = "usb2-phy"; | |
747 | status = "disabled"; | |
748 | }; | |
749 | ||
750 | usb1: usb@ffb40000 { | |
751 | compatible = "snps,dwc2"; | |
752 | reg = <0xffb40000 0xffff>; | |
753 | interrupts = <0 128 4>; | |
754 | clocks = <&usb_mp_clk>; | |
755 | clock-names = "otg"; | |
756 | phys = <&usbphy0>; | |
757 | phy-names = "usb2-phy"; | |
758 | status = "disabled"; | |
759 | }; | |
760 | ||
a98b6057 ST |
761 | watchdog0: watchdog@ffd02000 { |
762 | compatible = "snps,dw-wdt"; | |
763 | reg = <0xffd02000 0x1000>; | |
764 | interrupts = <0 171 4>; | |
765 | clocks = <&osc1>; | |
766 | status = "disabled"; | |
767 | }; | |
768 | ||
769 | watchdog1: watchdog@ffd03000 { | |
770 | compatible = "snps,dw-wdt"; | |
771 | reg = <0xffd03000 0x1000>; | |
772 | interrupts = <0 172 4>; | |
773 | clocks = <&osc1>; | |
774 | status = "disabled"; | |
775 | }; | |
776 | ||
a5d6ac2a | 777 | sysmgr: sysmgr@ffd08000 { |
9b931361 DN |
778 | compatible = "altr,sys-mgr", "syscon"; |
779 | reg = <0xffd08000 0x4000>; | |
780 | }; | |
66314223 DN |
781 | }; |
782 | }; |