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Commit | Line | Data |
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5d0769f0 AB |
1 | /* |
2 | * Copyright 2012 Linaro Ltd | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
90c40257 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
841cd0c0 | 13 | #include <dt-bindings/mfd/dbx500-prcmu.h> |
807e8838 | 14 | #include "skeleton.dtsi" |
5d0769f0 AB |
15 | |
16 | / { | |
b1ba1439 | 17 | soc { |
5d0769f0 AB |
18 | #address-cells = <1>; |
19 | #size-cells = <1>; | |
7e0ce270 | 20 | compatible = "stericsson,db8500"; |
dab6487e | 21 | interrupt-parent = <&intc>; |
5d0769f0 | 22 | ranges; |
7e0ce270 | 23 | |
dab6487e LJ |
24 | intc: interrupt-controller@a0411000 { |
25 | compatible = "arm,cortex-a9-gic"; | |
26 | #interrupt-cells = <3>; | |
27 | #address-cells = <1>; | |
28 | interrupt-controller; | |
dab6487e LJ |
29 | reg = <0xa0411000 0x1000>, |
30 | <0xa0410100 0x100>; | |
31 | }; | |
32 | ||
f1949ea0 LJ |
33 | L2: l2-cache { |
34 | compatible = "arm,pl310-cache"; | |
35 | reg = <0xa0412000 0x1000>; | |
90c40257 | 36 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; |
f1949ea0 LJ |
37 | cache-unified; |
38 | cache-level = <2>; | |
39 | }; | |
40 | ||
7e0ce270 LJ |
41 | pmu { |
42 | compatible = "arm,cortex-a9-pmu"; | |
90c40257 | 43 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 LJ |
44 | }; |
45 | ||
8132ed1b | 46 | |
841cd0c0 LJ |
47 | clocks { |
48 | compatible = "stericsson,u8500-clks"; | |
49 | ||
50 | prcmu_clk: prcmu-clock { | |
51 | #clock-cells = <1>; | |
52 | }; | |
fcbe5e90 LJ |
53 | |
54 | prcc_pclk: prcc-periph-clock { | |
55 | #clock-cells = <2>; | |
56 | }; | |
2588fea6 LJ |
57 | |
58 | prcc_kclk: prcc-kernel-clock { | |
59 | #clock-cells = <2>; | |
60 | }; | |
589d9839 LJ |
61 | |
62 | rtc_clk: rtc32k-clock { | |
63 | #clock-cells = <0>; | |
64 | }; | |
309012d7 LJ |
65 | |
66 | smp_twd_clk: smp-twd-clock { | |
67 | #clock-cells = <0>; | |
68 | }; | |
841cd0c0 LJ |
69 | }; |
70 | ||
8132ed1b LJ |
71 | mtu@a03c6000 { |
72 | /* Nomadik System Timer */ | |
73 | compatible = "st,nomadik-mtu"; | |
74 | reg = <0xa03c6000 0x1000>; | |
75 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | |
76 | ||
77 | clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; | |
78 | clock-names = "timclk", "apb_pclk"; | |
79 | }; | |
80 | ||
71de5c46 LJ |
81 | timer@a0410600 { |
82 | compatible = "arm,cortex-a9-twd-timer"; | |
83 | reg = <0xa0410600 0x20>; | |
90c40257 | 84 | interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ |
a8acb1ec LJ |
85 | |
86 | clocks = <&smp_twd_clk>; | |
71de5c46 LJ |
87 | }; |
88 | ||
7e0ce270 | 89 | rtc@80154000 { |
ddb3b99c | 90 | compatible = "arm,rtc-pl031", "arm,primecell"; |
7e0ce270 | 91 | reg = <0x80154000 0x1000>; |
90c40257 | 92 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
d299b5a5 LJ |
93 | |
94 | clocks = <&rtc_clk>; | |
95 | clock-names = "apb_pclk"; | |
7e0ce270 LJ |
96 | }; |
97 | ||
98 | gpio0: gpio@8012e000 { | |
99 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 100 | "st,nomadik-gpio"; |
7e0ce270 | 101 | reg = <0x8012e000 0x80>; |
90c40257 | 102 | interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
103 | interrupt-controller; |
104 | #interrupt-cells = <2>; | |
61be4981 | 105 | st,supports-sleepmode; |
7e0ce270 | 106 | gpio-controller; |
c0b133bd LJ |
107 | #gpio-cells = <2>; |
108 | gpio-bank = <0>; | |
9d891073 LJ |
109 | |
110 | clocks = <&prcc_pclk 1 9>; | |
7e0ce270 LJ |
111 | }; |
112 | ||
113 | gpio1: gpio@8012e080 { | |
114 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 115 | "st,nomadik-gpio"; |
7e0ce270 | 116 | reg = <0x8012e080 0x80>; |
90c40257 | 117 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
118 | interrupt-controller; |
119 | #interrupt-cells = <2>; | |
61be4981 | 120 | st,supports-sleepmode; |
7e0ce270 | 121 | gpio-controller; |
c0b133bd LJ |
122 | #gpio-cells = <2>; |
123 | gpio-bank = <1>; | |
9d891073 LJ |
124 | |
125 | clocks = <&prcc_pclk 1 9>; | |
7e0ce270 LJ |
126 | }; |
127 | ||
128 | gpio2: gpio@8000e000 { | |
129 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 130 | "st,nomadik-gpio"; |
7e0ce270 | 131 | reg = <0x8000e000 0x80>; |
90c40257 | 132 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
133 | interrupt-controller; |
134 | #interrupt-cells = <2>; | |
61be4981 | 135 | st,supports-sleepmode; |
7e0ce270 | 136 | gpio-controller; |
c0b133bd LJ |
137 | #gpio-cells = <2>; |
138 | gpio-bank = <2>; | |
9d891073 LJ |
139 | |
140 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
141 | }; |
142 | ||
143 | gpio3: gpio@8000e080 { | |
144 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 145 | "st,nomadik-gpio"; |
7e0ce270 | 146 | reg = <0x8000e080 0x80>; |
90c40257 | 147 | interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
148 | interrupt-controller; |
149 | #interrupt-cells = <2>; | |
61be4981 | 150 | st,supports-sleepmode; |
7e0ce270 | 151 | gpio-controller; |
c0b133bd LJ |
152 | #gpio-cells = <2>; |
153 | gpio-bank = <3>; | |
9d891073 LJ |
154 | |
155 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
156 | }; |
157 | ||
158 | gpio4: gpio@8000e100 { | |
159 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 160 | "st,nomadik-gpio"; |
7e0ce270 | 161 | reg = <0x8000e100 0x80>; |
90c40257 | 162 | interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
163 | interrupt-controller; |
164 | #interrupt-cells = <2>; | |
61be4981 | 165 | st,supports-sleepmode; |
7e0ce270 | 166 | gpio-controller; |
c0b133bd LJ |
167 | #gpio-cells = <2>; |
168 | gpio-bank = <4>; | |
9d891073 LJ |
169 | |
170 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
171 | }; |
172 | ||
173 | gpio5: gpio@8000e180 { | |
174 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 175 | "st,nomadik-gpio"; |
7e0ce270 | 176 | reg = <0x8000e180 0x80>; |
90c40257 | 177 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
178 | interrupt-controller; |
179 | #interrupt-cells = <2>; | |
61be4981 | 180 | st,supports-sleepmode; |
7e0ce270 | 181 | gpio-controller; |
c0b133bd LJ |
182 | #gpio-cells = <2>; |
183 | gpio-bank = <5>; | |
9d891073 LJ |
184 | |
185 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
186 | }; |
187 | ||
188 | gpio6: gpio@8011e000 { | |
189 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 190 | "st,nomadik-gpio"; |
7e0ce270 | 191 | reg = <0x8011e000 0x80>; |
90c40257 | 192 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
193 | interrupt-controller; |
194 | #interrupt-cells = <2>; | |
61be4981 | 195 | st,supports-sleepmode; |
7e0ce270 | 196 | gpio-controller; |
c0b133bd LJ |
197 | #gpio-cells = <2>; |
198 | gpio-bank = <6>; | |
9d891073 | 199 | |
d591640a | 200 | clocks = <&prcc_pclk 2 11>; |
7e0ce270 LJ |
201 | }; |
202 | ||
203 | gpio7: gpio@8011e080 { | |
204 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 205 | "st,nomadik-gpio"; |
7e0ce270 | 206 | reg = <0x8011e080 0x80>; |
90c40257 | 207 | interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
208 | interrupt-controller; |
209 | #interrupt-cells = <2>; | |
61be4981 | 210 | st,supports-sleepmode; |
7e0ce270 | 211 | gpio-controller; |
c0b133bd LJ |
212 | #gpio-cells = <2>; |
213 | gpio-bank = <7>; | |
9d891073 | 214 | |
d591640a | 215 | clocks = <&prcc_pclk 2 11>; |
7e0ce270 LJ |
216 | }; |
217 | ||
218 | gpio8: gpio@a03fe000 { | |
219 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 220 | "st,nomadik-gpio"; |
7e0ce270 | 221 | reg = <0xa03fe000 0x80>; |
90c40257 | 222 | interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
223 | interrupt-controller; |
224 | #interrupt-cells = <2>; | |
61be4981 | 225 | st,supports-sleepmode; |
7e0ce270 | 226 | gpio-controller; |
c0b133bd LJ |
227 | #gpio-cells = <2>; |
228 | gpio-bank = <8>; | |
9d891073 | 229 | |
84873cb7 | 230 | clocks = <&prcc_pclk 5 1>; |
7e0ce270 LJ |
231 | }; |
232 | ||
8979cfef | 233 | pinctrl { |
818d99a9 | 234 | compatible = "stericsson,db8500-pinctrl"; |
8979cfef | 235 | prcm = <&prcmu>; |
5910de9e LJ |
236 | }; |
237 | ||
b32dc865 | 238 | usb_per5@a03e0000 { |
4a6cd43f | 239 | compatible = "stericsson,db8500-musb"; |
7e0ce270 | 240 | reg = <0xa03e0000 0x10000>; |
90c40257 | 241 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
b32dc865 LJ |
242 | interrupt-names = "mc"; |
243 | ||
244 | dr_mode = "otg"; | |
245 | ||
246 | dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ | |
247 | <&dma 38 0 0x0>, /* Logical - MemToDev */ | |
248 | <&dma 37 0 0x2>, /* Logical - DevToMem */ | |
249 | <&dma 37 0 0x0>, /* Logical - MemToDev */ | |
250 | <&dma 36 0 0x2>, /* Logical - DevToMem */ | |
251 | <&dma 36 0 0x0>, /* Logical - MemToDev */ | |
252 | <&dma 19 0 0x2>, /* Logical - DevToMem */ | |
253 | <&dma 19 0 0x0>, /* Logical - MemToDev */ | |
254 | <&dma 18 0 0x2>, /* Logical - DevToMem */ | |
255 | <&dma 18 0 0x0>, /* Logical - MemToDev */ | |
256 | <&dma 17 0 0x2>, /* Logical - DevToMem */ | |
257 | <&dma 17 0 0x0>, /* Logical - MemToDev */ | |
258 | <&dma 16 0 0x2>, /* Logical - DevToMem */ | |
259 | <&dma 16 0 0x0>, /* Logical - MemToDev */ | |
260 | <&dma 39 0 0x2>, /* Logical - DevToMem */ | |
261 | <&dma 39 0 0x0>; /* Logical - MemToDev */ | |
262 | ||
263 | dma-names = "iep_1_9", "oep_1_9", | |
264 | "iep_2_10", "oep_2_10", | |
265 | "iep_3_11", "oep_3_11", | |
266 | "iep_4_12", "oep_4_12", | |
267 | "iep_5_13", "oep_5_13", | |
268 | "iep_6_14", "oep_6_14", | |
269 | "iep_7_15", "oep_7_15", | |
270 | "iep_8", "oep_8"; | |
e47339ff LJ |
271 | |
272 | clocks = <&prcc_pclk 5 0>; | |
7e0ce270 LJ |
273 | }; |
274 | ||
ba074aec LJ |
275 | dma: dma-controller@801C0000 { |
276 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | |
7e0ce270 | 277 | reg = <0x801C0000 0x1000 0x40010000 0x800>; |
70d39a8d | 278 | reg-names = "base", "lcpa"; |
90c40257 | 279 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
ba074aec LJ |
280 | |
281 | #dma-cells = <3>; | |
d37fcdb6 | 282 | memcpy-channels = <56 57 58 59 60>; |
e064cb24 LJ |
283 | |
284 | clocks = <&prcmu_clk PRCMU_DMACLK>; | |
7e0ce270 LJ |
285 | }; |
286 | ||
8979cfef | 287 | prcmu: prcmu@80157000 { |
7e0ce270 | 288 | compatible = "stericsson,db8500-prcmu"; |
4d26aa30 | 289 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; |
e73081d9 | 290 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; |
90c40257 | 291 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 | 292 | #address-cells = <1>; |
3de3d749 | 293 | #size-cells = <1>; |
c09090bb LJ |
294 | interrupt-controller; |
295 | #interrupt-cells = <2>; | |
3de3d749 LJ |
296 | ranges; |
297 | ||
ccf74f76 | 298 | prcmu-timer-4@80157450 { |
3de3d749 LJ |
299 | compatible = "stericsson,db8500-prcmu-timer-4"; |
300 | reg = <0x80157450 0xC>; | |
301 | }; | |
7e0ce270 | 302 | |
98585616 LJ |
303 | cpufreq { |
304 | compatible = "stericsson,cpufreq-ux500"; | |
305 | clocks = <&prcmu_clk PRCMU_ARMSS>; | |
306 | clock-names = "armss"; | |
307 | status = "disabled"; | |
308 | }; | |
309 | ||
dc1956b5 | 310 | thermal@801573c0 { |
311 | compatible = "stericsson,db8500-thermal"; | |
312 | reg = <0x801573c0 0x40>; | |
90c40257 LW |
313 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, |
314 | <22 IRQ_TYPE_LEVEL_HIGH>; | |
dc1956b5 | 315 | interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; |
316 | status = "disabled"; | |
1d3f99f5 | 317 | }; |
dc1956b5 | 318 | |
e5999f28 LJ |
319 | db8500-prcmu-regulators { |
320 | compatible = "stericsson,db8500-prcmu-regulator"; | |
321 | ||
322 | // DB8500_REGULATOR_VAPE | |
323 | db8500_vape_reg: db8500_vape { | |
da26848a | 324 | regulator-compatible = "db8500_vape"; |
e5999f28 LJ |
325 | regulator-always-on; |
326 | }; | |
327 | ||
328 | // DB8500_REGULATOR_VARM | |
329 | db8500_varm_reg: db8500_varm { | |
da26848a | 330 | regulator-compatible = "db8500_varm"; |
e5999f28 LJ |
331 | }; |
332 | ||
333 | // DB8500_REGULATOR_VMODEM | |
334 | db8500_vmodem_reg: db8500_vmodem { | |
da26848a | 335 | regulator-compatible = "db8500_vmodem"; |
e5999f28 LJ |
336 | }; |
337 | ||
338 | // DB8500_REGULATOR_VPLL | |
339 | db8500_vpll_reg: db8500_vpll { | |
da26848a | 340 | regulator-compatible = "db8500_vpll"; |
e5999f28 LJ |
341 | }; |
342 | ||
343 | // DB8500_REGULATOR_VSMPS1 | |
344 | db8500_vsmps1_reg: db8500_vsmps1 { | |
da26848a | 345 | regulator-compatible = "db8500_vsmps1"; |
e5999f28 LJ |
346 | }; |
347 | ||
348 | // DB8500_REGULATOR_VSMPS2 | |
349 | db8500_vsmps2_reg: db8500_vsmps2 { | |
da26848a | 350 | regulator-compatible = "db8500_vsmps2"; |
e5999f28 LJ |
351 | }; |
352 | ||
353 | // DB8500_REGULATOR_VSMPS3 | |
354 | db8500_vsmps3_reg: db8500_vsmps3 { | |
da26848a | 355 | regulator-compatible = "db8500_vsmps3"; |
e5999f28 LJ |
356 | }; |
357 | ||
358 | // DB8500_REGULATOR_VRF1 | |
359 | db8500_vrf1_reg: db8500_vrf1 { | |
da26848a | 360 | regulator-compatible = "db8500_vrf1"; |
e5999f28 LJ |
361 | }; |
362 | ||
363 | // DB8500_REGULATOR_SWITCH_SVAMMDSP | |
364 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { | |
da26848a | 365 | regulator-compatible = "db8500_sva_mmdsp"; |
e5999f28 LJ |
366 | }; |
367 | ||
368 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET | |
369 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { | |
da26848a | 370 | regulator-compatible = "db8500_sva_mmdsp_ret"; |
e5999f28 LJ |
371 | }; |
372 | ||
373 | // DB8500_REGULATOR_SWITCH_SVAPIPE | |
374 | db8500_sva_pipe_reg: db8500_sva_pipe { | |
da26848a | 375 | regulator-compatible = "db8500_sva_pipe"; |
e5999f28 LJ |
376 | }; |
377 | ||
378 | // DB8500_REGULATOR_SWITCH_SIAMMDSP | |
379 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { | |
da26848a | 380 | regulator-compatible = "db8500_sia_mmdsp"; |
e5999f28 LJ |
381 | }; |
382 | ||
383 | // DB8500_REGULATOR_SWITCH_SIAMMDSPRET | |
384 | db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { | |
e5999f28 LJ |
385 | }; |
386 | ||
387 | // DB8500_REGULATOR_SWITCH_SIAPIPE | |
388 | db8500_sia_pipe_reg: db8500_sia_pipe { | |
da26848a | 389 | regulator-compatible = "db8500_sia_pipe"; |
e5999f28 LJ |
390 | }; |
391 | ||
392 | // DB8500_REGULATOR_SWITCH_SGA | |
393 | db8500_sga_reg: db8500_sga { | |
da26848a | 394 | regulator-compatible = "db8500_sga"; |
e5999f28 LJ |
395 | vin-supply = <&db8500_vape_reg>; |
396 | }; | |
397 | ||
398 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE | |
399 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { | |
da26848a | 400 | regulator-compatible = "db8500_b2r2_mcde"; |
e5999f28 LJ |
401 | vin-supply = <&db8500_vape_reg>; |
402 | }; | |
403 | ||
404 | // DB8500_REGULATOR_SWITCH_ESRAM12 | |
405 | db8500_esram12_reg: db8500_esram12 { | |
da26848a | 406 | regulator-compatible = "db8500_esram12"; |
e5999f28 LJ |
407 | }; |
408 | ||
409 | // DB8500_REGULATOR_SWITCH_ESRAM12RET | |
410 | db8500_esram12_ret_reg: db8500_esram12_ret { | |
da26848a | 411 | regulator-compatible = "db8500_esram12_ret"; |
e5999f28 LJ |
412 | }; |
413 | ||
414 | // DB8500_REGULATOR_SWITCH_ESRAM34 | |
415 | db8500_esram34_reg: db8500_esram34 { | |
da26848a | 416 | regulator-compatible = "db8500_esram34"; |
e5999f28 LJ |
417 | }; |
418 | ||
419 | // DB8500_REGULATOR_SWITCH_ESRAM34RET | |
420 | db8500_esram34_ret_reg: db8500_esram34_ret { | |
da26848a | 421 | regulator-compatible = "db8500_esram34_ret"; |
e5999f28 LJ |
422 | }; |
423 | }; | |
424 | ||
d52701d3 | 425 | ab8500 { |
7e0ce270 | 426 | compatible = "stericsson,ab8500"; |
8d4c6d45 | 427 | interrupt-parent = <&intc>; |
90c40257 | 428 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
732973c8 LJ |
429 | interrupt-controller; |
430 | #interrupt-cells = <2>; | |
4a85c7fa | 431 | |
348f3bc6 LJ |
432 | ab8500_gpio: ab8500-gpio { |
433 | gpio-controller; | |
434 | #gpio-cells = <2>; | |
435 | }; | |
436 | ||
d4b29ac1 LJ |
437 | ab8500-rtc { |
438 | compatible = "stericsson,ab8500-rtc"; | |
90c40257 LW |
439 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH |
440 | 18 IRQ_TYPE_LEVEL_HIGH>; | |
d4b29ac1 LJ |
441 | interrupt-names = "60S", "ALARM"; |
442 | }; | |
443 | ||
4eda9129 LJ |
444 | ab8500-gpadc { |
445 | compatible = "stericsson,ab8500-gpadc"; | |
90c40257 LW |
446 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH |
447 | 39 IRQ_TYPE_LEVEL_HIGH>; | |
4eda9129 LJ |
448 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; |
449 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
450 | }; | |
451 | ||
e0f1abeb R |
452 | ab8500_battery: ab8500_battery { |
453 | stericsson,battery-type = "LIPO"; | |
454 | thermistor-on-batctrl; | |
455 | }; | |
456 | ||
457 | ab8500_fg { | |
458 | compatible = "stericsson,ab8500-fg"; | |
459 | battery = <&ab8500_battery>; | |
460 | }; | |
461 | ||
bd9e8ab2 R |
462 | ab8500_btemp { |
463 | compatible = "stericsson,ab8500-btemp"; | |
464 | battery = <&ab8500_battery>; | |
465 | }; | |
466 | ||
4aef72db R |
467 | ab8500_charger { |
468 | compatible = "stericsson,ab8500-charger"; | |
469 | battery = <&ab8500_battery>; | |
470 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
471 | }; | |
472 | ||
a12810ab R |
473 | ab8500_chargalg { |
474 | compatible = "stericsson,ab8500-chargalg"; | |
475 | battery = <&ab8500_battery>; | |
476 | }; | |
477 | ||
e0f1abeb | 478 | ab8500_usb { |
ee189cef | 479 | compatible = "stericsson,ab8500-usb"; |
90c40257 LW |
480 | interrupts = < 90 IRQ_TYPE_LEVEL_HIGH |
481 | 96 IRQ_TYPE_LEVEL_HIGH | |
482 | 14 IRQ_TYPE_LEVEL_HIGH | |
483 | 15 IRQ_TYPE_LEVEL_HIGH | |
484 | 79 IRQ_TYPE_LEVEL_HIGH | |
485 | 74 IRQ_TYPE_LEVEL_HIGH | |
486 | 75 IRQ_TYPE_LEVEL_HIGH>; | |
ee189cef LJ |
487 | interrupt-names = "ID_WAKEUP_R", |
488 | "ID_WAKEUP_F", | |
489 | "VBUS_DET_F", | |
490 | "VBUS_DET_R", | |
491 | "USB_LINK_STATUS", | |
492 | "USB_ADP_PROBE_PLUG", | |
493 | "USB_ADP_PROBE_UNPLUG"; | |
99b38eef | 494 | vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; |
ee189cef LJ |
495 | v-ape-supply = <&db8500_vape_reg>; |
496 | musb_1v8-supply = <&db8500_vsmps2_reg>; | |
497 | }; | |
498 | ||
12cb7bd4 | 499 | ab8500-ponkey { |
74630706 | 500 | compatible = "stericsson,ab8500-poweron-key"; |
90c40257 LW |
501 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH |
502 | 7 IRQ_TYPE_LEVEL_HIGH>; | |
12cb7bd4 LJ |
503 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; |
504 | }; | |
505 | ||
401cd1b8 LJ |
506 | ab8500-sysctrl { |
507 | compatible = "stericsson,ab8500-sysctrl"; | |
508 | }; | |
509 | ||
78451de7 LJ |
510 | ab8500-pwm { |
511 | compatible = "stericsson,ab8500-pwm"; | |
512 | }; | |
513 | ||
215891ec LJ |
514 | ab8500-debugfs { |
515 | compatible = "stericsson,ab8500-debug"; | |
516 | }; | |
4a85c7fa | 517 | |
9c06af30 LJ |
518 | codec: ab8500-codec { |
519 | compatible = "stericsson,ab8500-codec"; | |
520 | ||
f99808a6 FB |
521 | V-AUD-supply = <&ab8500_ldo_audio_reg>; |
522 | V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; | |
523 | V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; | |
524 | V-DMIC-supply = <&ab8500_ldo_dmic_reg>; | |
525 | ||
9c06af30 LJ |
526 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ |
527 | }; | |
528 | ||
62ebfe6b LJ |
529 | ext_regulators: ab8500-ext-regulators { |
530 | compatible = "stericsson,ab8500-ext-regulator"; | |
531 | ||
532 | ab8500_ext1_reg: ab8500_ext1 { | |
533 | regulator-compatible = "ab8500_ext1"; | |
534 | regulator-min-microvolt = <1800000>; | |
535 | regulator-max-microvolt = <1800000>; | |
536 | regulator-boot-on; | |
537 | regulator-always-on; | |
538 | }; | |
539 | ||
540 | ab8500_ext2_reg: ab8500_ext2 { | |
541 | regulator-compatible = "ab8500_ext2"; | |
542 | regulator-min-microvolt = <1360000>; | |
543 | regulator-max-microvolt = <1360000>; | |
544 | regulator-boot-on; | |
545 | regulator-always-on; | |
546 | }; | |
547 | ||
548 | ab8500_ext3_reg: ab8500_ext3 { | |
549 | regulator-compatible = "ab8500_ext3"; | |
550 | regulator-min-microvolt = <3400000>; | |
551 | regulator-max-microvolt = <3400000>; | |
552 | regulator-boot-on; | |
553 | }; | |
554 | }; | |
555 | ||
4a85c7fa LJ |
556 | ab8500-regulators { |
557 | compatible = "stericsson,ab8500-regulator"; | |
75f0999a | 558 | vin-supply = <&ab8500_ext3_reg>; |
4a85c7fa LJ |
559 | |
560 | // supplies to the display/camera | |
561 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | |
da26848a | 562 | regulator-compatible = "ab8500_ldo_aux1"; |
4a85c7fa LJ |
563 | regulator-min-microvolt = <2500000>; |
564 | regulator-max-microvolt = <2900000>; | |
565 | regulator-boot-on; | |
566 | /* BUG: If turned off MMC will be affected. */ | |
567 | regulator-always-on; | |
568 | }; | |
569 | ||
570 | // supplies to the on-board eMMC | |
571 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { | |
da26848a | 572 | regulator-compatible = "ab8500_ldo_aux2"; |
4a85c7fa LJ |
573 | regulator-min-microvolt = <1100000>; |
574 | regulator-max-microvolt = <3300000>; | |
575 | }; | |
576 | ||
577 | // supply for VAUX3; SDcard slots | |
578 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { | |
da26848a | 579 | regulator-compatible = "ab8500_ldo_aux3"; |
4a85c7fa LJ |
580 | regulator-min-microvolt = <1100000>; |
581 | regulator-max-microvolt = <3300000>; | |
582 | }; | |
583 | ||
584 | // supply for v-intcore12; VINTCORE12 LDO | |
99b38eef FB |
585 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
586 | regulator-compatible = "ab8500_ldo_intcore"; | |
4a85c7fa LJ |
587 | }; |
588 | ||
589 | // supply for tvout; gpadc; TVOUT LDO | |
590 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { | |
da26848a | 591 | regulator-compatible = "ab8500_ldo_tvout"; |
4a85c7fa LJ |
592 | }; |
593 | ||
594 | // supply for ab8500-usb; USB LDO | |
595 | ab8500_ldo_usb_reg: ab8500_ldo_usb { | |
da26848a | 596 | regulator-compatible = "ab8500_ldo_usb"; |
4a85c7fa LJ |
597 | }; |
598 | ||
599 | // supply for ab8500-vaudio; VAUDIO LDO | |
600 | ab8500_ldo_audio_reg: ab8500_ldo_audio { | |
da26848a | 601 | regulator-compatible = "ab8500_ldo_audio"; |
4a85c7fa LJ |
602 | }; |
603 | ||
4aa44874 | 604 | // supply for v-anamic1 VAMIC1 LDO |
4a85c7fa | 605 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { |
da26848a | 606 | regulator-compatible = "ab8500_ldo_anamic1"; |
4a85c7fa LJ |
607 | }; |
608 | ||
609 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 | |
5510ed9f FB |
610 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
611 | regulator-compatible = "ab8500_ldo_anamic2"; | |
4a85c7fa LJ |
612 | }; |
613 | ||
614 | // supply for v-dmic; VDMIC LDO | |
615 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { | |
da26848a | 616 | regulator-compatible = "ab8500_ldo_dmic"; |
4a85c7fa LJ |
617 | }; |
618 | ||
619 | // supply for U8500 CSI/DSI; VANA LDO | |
620 | ab8500_ldo_ana_reg: ab8500_ldo_ana { | |
da26848a | 621 | regulator-compatible = "ab8500_ldo_ana"; |
4a85c7fa LJ |
622 | }; |
623 | }; | |
7e0ce270 LJ |
624 | }; |
625 | }; | |
626 | ||
627 | i2c@80004000 { | |
d524fa7f | 628 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 629 | reg = <0x80004000 0x1000>; |
90c40257 | 630 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 631 | |
7e0ce270 LJ |
632 | #address-cells = <1>; |
633 | #size-cells = <0>; | |
d524fa7f LJ |
634 | v-i2c-supply = <&db8500_vape_reg>; |
635 | ||
636 | clock-frequency = <400000>; | |
afd653e9 LJ |
637 | clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; |
638 | clock-names = "i2cclk", "apb_pclk"; | |
7e0ce270 LJ |
639 | }; |
640 | ||
641 | i2c@80122000 { | |
d524fa7f | 642 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 643 | reg = <0x80122000 0x1000>; |
90c40257 | 644 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 645 | |
7e0ce270 LJ |
646 | #address-cells = <1>; |
647 | #size-cells = <0>; | |
d524fa7f LJ |
648 | v-i2c-supply = <&db8500_vape_reg>; |
649 | ||
650 | clock-frequency = <400000>; | |
afd653e9 LJ |
651 | |
652 | clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; | |
653 | clock-names = "i2cclk", "apb_pclk"; | |
7e0ce270 LJ |
654 | }; |
655 | ||
656 | i2c@80128000 { | |
d524fa7f | 657 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 658 | reg = <0x80128000 0x1000>; |
90c40257 | 659 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 660 | |
7e0ce270 LJ |
661 | #address-cells = <1>; |
662 | #size-cells = <0>; | |
d524fa7f LJ |
663 | v-i2c-supply = <&db8500_vape_reg>; |
664 | ||
665 | clock-frequency = <400000>; | |
afd653e9 LJ |
666 | |
667 | clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; | |
668 | clock-names = "i2cclk", "apb_pclk"; | |
7e0ce270 LJ |
669 | }; |
670 | ||
671 | i2c@80110000 { | |
d524fa7f | 672 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 673 | reg = <0x80110000 0x1000>; |
90c40257 | 674 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 675 | |
7e0ce270 LJ |
676 | #address-cells = <1>; |
677 | #size-cells = <0>; | |
d524fa7f LJ |
678 | v-i2c-supply = <&db8500_vape_reg>; |
679 | ||
680 | clock-frequency = <400000>; | |
afd653e9 LJ |
681 | |
682 | clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; | |
683 | clock-names = "i2cclk", "apb_pclk"; | |
7e0ce270 LJ |
684 | }; |
685 | ||
686 | i2c@8012a000 { | |
d524fa7f | 687 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 688 | reg = <0x8012a000 0x1000>; |
90c40257 | 689 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 690 | |
7e0ce270 LJ |
691 | #address-cells = <1>; |
692 | #size-cells = <0>; | |
d524fa7f LJ |
693 | v-i2c-supply = <&db8500_vape_reg>; |
694 | ||
695 | clock-frequency = <400000>; | |
afd653e9 | 696 | |
72b3e249 | 697 | clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; |
afd653e9 | 698 | clock-names = "i2cclk", "apb_pclk"; |
7e0ce270 LJ |
699 | }; |
700 | ||
701 | ssp@80002000 { | |
702 | compatible = "arm,pl022", "arm,primecell"; | |
c164fa62 | 703 | reg = <0x80002000 0x1000>; |
90c40257 | 704 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 LJ |
705 | #address-cells = <1>; |
706 | #size-cells = <0>; | |
6e1484c2 LW |
707 | clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; |
708 | clock-names = "ssp0clk", "apb_pclk"; | |
709 | dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ | |
710 | <&dma 8 0 0x0>; /* Logical - MemToDev */ | |
711 | dma-names = "rx", "tx"; | |
712 | }; | |
713 | ||
714 | ssp@80003000 { | |
715 | compatible = "arm,pl022", "arm,primecell"; | |
716 | reg = <0x80003000 0x1000>; | |
717 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; | |
718 | #address-cells = <1>; | |
719 | #size-cells = <0>; | |
720 | clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; | |
721 | clock-names = "ssp1clk", "apb_pclk"; | |
722 | dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ | |
723 | <&dma 9 0 0x0>; /* Logical - MemToDev */ | |
724 | dma-names = "rx", "tx"; | |
725 | }; | |
726 | ||
727 | spi@8011a000 { | |
728 | compatible = "arm,pl022", "arm,primecell"; | |
729 | reg = <0x8011a000 0x1000>; | |
730 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | |
731 | #address-cells = <1>; | |
732 | #size-cells = <0>; | |
733 | /* Same clock wired to kernel and pclk */ | |
734 | clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; | |
735 | clock-names = "spi0clk", "apb_pclk"; | |
736 | dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ | |
737 | <&dma 0 0 0x0>; /* Logical - MemToDev */ | |
738 | dma-names = "rx", "tx"; | |
739 | }; | |
740 | ||
741 | spi@80112000 { | |
742 | compatible = "arm,pl022", "arm,primecell"; | |
743 | reg = <0x80112000 0x1000>; | |
744 | interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
745 | #address-cells = <1>; | |
746 | #size-cells = <0>; | |
747 | /* Same clock wired to kernel and pclk */ | |
748 | clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; | |
749 | clock-names = "spi1clk", "apb_pclk"; | |
750 | dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ | |
751 | <&dma 35 0 0x0>; /* Logical - MemToDev */ | |
752 | dma-names = "rx", "tx"; | |
753 | }; | |
754 | ||
755 | spi@80111000 { | |
756 | compatible = "arm,pl022", "arm,primecell"; | |
757 | reg = <0x80111000 0x1000>; | |
758 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | |
759 | #address-cells = <1>; | |
760 | #size-cells = <0>; | |
761 | /* Same clock wired to kernel and pclk */ | |
762 | clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; | |
763 | clock-names = "spi2clk", "apb_pclk"; | |
764 | dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ | |
765 | <&dma 33 0 0x0>; /* Logical - MemToDev */ | |
766 | dma-names = "rx", "tx"; | |
767 | }; | |
768 | ||
769 | spi@80129000 { | |
770 | compatible = "arm,pl022", "arm,primecell"; | |
771 | reg = <0x80129000 0x1000>; | |
772 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; | |
773 | #address-cells = <1>; | |
774 | #size-cells = <0>; | |
775 | /* Same clock wired to kernel and pclk */ | |
776 | clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; | |
777 | clock-names = "spi3clk", "apb_pclk"; | |
778 | dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ | |
779 | <&dma 40 0 0x0>; /* Logical - MemToDev */ | |
780 | dma-names = "rx", "tx"; | |
7e0ce270 LJ |
781 | }; |
782 | ||
783 | uart@80120000 { | |
784 | compatible = "arm,pl011", "arm,primecell"; | |
785 | reg = <0x80120000 0x1000>; | |
90c40257 | 786 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
787 | |
788 | dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ | |
789 | <&dma 13 0 0x0>; /* Logical - MemToDev */ | |
790 | dma-names = "rx", "tx"; | |
791 | ||
5a323fb4 LJ |
792 | clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; |
793 | clock-names = "uart", "apb_pclk"; | |
794 | ||
7e0ce270 LJ |
795 | status = "disabled"; |
796 | }; | |
fbff01cc | 797 | |
7e0ce270 LJ |
798 | uart@80121000 { |
799 | compatible = "arm,pl011", "arm,primecell"; | |
800 | reg = <0x80121000 0x1000>; | |
90c40257 | 801 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
802 | |
803 | dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ | |
804 | <&dma 12 0 0x0>; /* Logical - MemToDev */ | |
805 | dma-names = "rx", "tx"; | |
806 | ||
5a323fb4 LJ |
807 | clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; |
808 | clock-names = "uart", "apb_pclk"; | |
809 | ||
7e0ce270 LJ |
810 | status = "disabled"; |
811 | }; | |
fbff01cc | 812 | |
7e0ce270 LJ |
813 | uart@80007000 { |
814 | compatible = "arm,pl011", "arm,primecell"; | |
815 | reg = <0x80007000 0x1000>; | |
90c40257 | 816 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
817 | |
818 | dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ | |
819 | <&dma 11 0 0x0>; /* Logical - MemToDev */ | |
820 | dma-names = "rx", "tx"; | |
821 | ||
5a323fb4 LJ |
822 | clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; |
823 | clock-names = "uart", "apb_pclk"; | |
824 | ||
7e0ce270 LJ |
825 | status = "disabled"; |
826 | }; | |
827 | ||
81bf8c2e | 828 | sdi0_per1@80126000 { |
7e0ce270 LJ |
829 | compatible = "arm,pl18x", "arm,primecell"; |
830 | reg = <0x80126000 0x1000>; | |
90c40257 | 831 | interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
832 | |
833 | dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ | |
834 | <&dma 29 0 0x0>; /* Logical - MemToDev */ | |
835 | dma-names = "rx", "tx"; | |
836 | ||
604be898 LJ |
837 | clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; |
838 | clock-names = "sdi", "apb_pclk"; | |
839 | ||
7e0ce270 LJ |
840 | status = "disabled"; |
841 | }; | |
76ff4e43 | 842 | |
81bf8c2e | 843 | sdi1_per2@80118000 { |
7e0ce270 LJ |
844 | compatible = "arm,pl18x", "arm,primecell"; |
845 | reg = <0x80118000 0x1000>; | |
90c40257 | 846 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
847 | |
848 | dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ | |
849 | <&dma 32 0 0x0>; /* Logical - MemToDev */ | |
850 | dma-names = "rx", "tx"; | |
851 | ||
604be898 LJ |
852 | clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; |
853 | clock-names = "sdi", "apb_pclk"; | |
854 | ||
7e0ce270 LJ |
855 | status = "disabled"; |
856 | }; | |
76ff4e43 | 857 | |
81bf8c2e | 858 | sdi2_per3@80005000 { |
7e0ce270 LJ |
859 | compatible = "arm,pl18x", "arm,primecell"; |
860 | reg = <0x80005000 0x1000>; | |
90c40257 | 861 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
862 | |
863 | dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ | |
864 | <&dma 28 0 0x0>; /* Logical - MemToDev */ | |
865 | dma-names = "rx", "tx"; | |
866 | ||
604be898 LJ |
867 | clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; |
868 | clock-names = "sdi", "apb_pclk"; | |
869 | ||
7e0ce270 LJ |
870 | status = "disabled"; |
871 | }; | |
76ff4e43 | 872 | |
81bf8c2e | 873 | sdi3_per2@80119000 { |
7e0ce270 LJ |
874 | compatible = "arm,pl18x", "arm,primecell"; |
875 | reg = <0x80119000 0x1000>; | |
90c40257 | 876 | interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; |
604be898 LJ |
877 | |
878 | clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; | |
879 | clock-names = "sdi", "apb_pclk"; | |
880 | ||
7e0ce270 LJ |
881 | status = "disabled"; |
882 | }; | |
76ff4e43 | 883 | |
81bf8c2e | 884 | sdi4_per2@80114000 { |
7e0ce270 LJ |
885 | compatible = "arm,pl18x", "arm,primecell"; |
886 | reg = <0x80114000 0x1000>; | |
90c40257 | 887 | interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
888 | |
889 | dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ | |
890 | <&dma 42 0 0x0>; /* Logical - MemToDev */ | |
891 | dma-names = "rx", "tx"; | |
892 | ||
604be898 LJ |
893 | clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; |
894 | clock-names = "sdi", "apb_pclk"; | |
895 | ||
7e0ce270 LJ |
896 | status = "disabled"; |
897 | }; | |
76ff4e43 | 898 | |
81bf8c2e | 899 | sdi5_per3@80008000 { |
7e0ce270 | 900 | compatible = "arm,pl18x", "arm,primecell"; |
76ff4e43 | 901 | reg = <0x80008000 0x1000>; |
90c40257 | 902 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; |
604be898 LJ |
903 | |
904 | clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; | |
905 | clock-names = "sdi", "apb_pclk"; | |
906 | ||
7e0ce270 LJ |
907 | status = "disabled"; |
908 | }; | |
bf76e062 | 909 | |
fe164529 LJ |
910 | msp0: msp@80123000 { |
911 | compatible = "stericsson,ux500-msp-i2s"; | |
912 | reg = <0x80123000 0x1000>; | |
90c40257 | 913 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 914 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 915 | |
618111ca LJ |
916 | dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ |
917 | <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ | |
918 | dma-names = "rx", "tx"; | |
919 | ||
133e6027 LJ |
920 | clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; |
921 | clock-names = "msp", "apb_pclk"; | |
922 | ||
fe164529 LJ |
923 | status = "disabled"; |
924 | }; | |
925 | ||
926 | msp1: msp@80124000 { | |
927 | compatible = "stericsson,ux500-msp-i2s"; | |
928 | reg = <0x80124000 0x1000>; | |
90c40257 | 929 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 930 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 931 | |
618111ca LJ |
932 | dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ |
933 | dma-names = "tx"; | |
934 | ||
133e6027 LJ |
935 | clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; |
936 | clock-names = "msp", "apb_pclk"; | |
937 | ||
fe164529 LJ |
938 | status = "disabled"; |
939 | }; | |
940 | ||
941 | // HDMI sound | |
942 | msp2: msp@80117000 { | |
943 | compatible = "stericsson,ux500-msp-i2s"; | |
944 | reg = <0x80117000 0x1000>; | |
90c40257 | 945 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 946 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 947 | |
618111ca LJ |
948 | dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ |
949 | <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev | |
950 | HighPrio - Fixed */ | |
951 | dma-names = "rx", "tx"; | |
952 | ||
133e6027 LJ |
953 | clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; |
954 | clock-names = "msp", "apb_pclk"; | |
955 | ||
fe164529 LJ |
956 | status = "disabled"; |
957 | }; | |
958 | ||
959 | msp3: msp@80125000 { | |
960 | compatible = "stericsson,ux500-msp-i2s"; | |
961 | reg = <0x80125000 0x1000>; | |
90c40257 | 962 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 963 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 964 | |
618111ca LJ |
965 | dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ |
966 | dma-names = "rx"; | |
967 | ||
133e6027 LJ |
968 | clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; |
969 | clock-names = "msp", "apb_pclk"; | |
970 | ||
fe164529 LJ |
971 | status = "disabled"; |
972 | }; | |
973 | ||
bf76e062 LJ |
974 | external-bus@50000000 { |
975 | compatible = "simple-bus"; | |
976 | reg = <0x50000000 0x4000000>; | |
977 | #address-cells = <1>; | |
978 | #size-cells = <1>; | |
979 | ranges = <0 0x50000000 0x4000000>; | |
980 | status = "disabled"; | |
981 | }; | |
dc1956b5 | 982 | |
983 | cpufreq-cooling { | |
984 | compatible = "stericsson,db8500-cpufreq-cooling"; | |
985 | status = "disabled"; | |
d460d28b | 986 | }; |
dc1956b5 | 987 | |
0563f638 LJ |
988 | vmmci: regulator-gpio { |
989 | compatible = "regulator-gpio"; | |
990 | ||
991 | regulator-min-microvolt = <1800000>; | |
4f902b42 | 992 | regulator-max-microvolt = <2900000>; |
0563f638 LJ |
993 | regulator-name = "mmci-reg"; |
994 | regulator-type = "voltage"; | |
995 | ||
874c9202 | 996 | startup-delay-us = <100>; |
e7bda303 LJ |
997 | enable-active-high; |
998 | ||
0563f638 LJ |
999 | states = <1800000 0x1 |
1000 | 2900000 0x0>; | |
c94a4ab7 LJ |
1001 | |
1002 | status = "disabled"; | |
0563f638 | 1003 | }; |
fe2e9f92 | 1004 | |
6e9a88a0 LW |
1005 | mcde@a0350000 { |
1006 | compatible = "stericsson,mcde"; | |
1007 | reg = <0xa0350000 0x1000>, /* MCDE */ | |
1008 | <0xa0351000 0x1000>, /* DSI link 1 */ | |
1009 | <0xa0352000 0x1000>, /* DSI link 2 */ | |
1010 | <0xa0353000 0x1000>; /* DSI link 3 */ | |
1011 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; | |
1012 | clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ | |
1013 | <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ | |
1014 | <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ | |
1015 | <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ | |
1016 | <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ | |
1017 | <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ | |
1018 | <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ | |
1019 | <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ | |
1020 | }; | |
1021 | ||
fe2e9f92 LJ |
1022 | cryp@a03cb000 { |
1023 | compatible = "stericsson,ux500-cryp"; | |
1024 | reg = <0xa03cb000 0x1000>; | |
90c40257 | 1025 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
fe2e9f92 LJ |
1026 | |
1027 | v-ape-supply = <&db8500_vape_reg>; | |
d2f898ce | 1028 | clocks = <&prcc_pclk 6 1>; |
fe2e9f92 | 1029 | }; |
61122cf2 LJ |
1030 | |
1031 | hash@a03c2000 { | |
1032 | compatible = "stericsson,ux500-hash"; | |
1033 | reg = <0xa03c2000 0x1000>; | |
1034 | ||
1035 | v-ape-supply = <&db8500_vape_reg>; | |
024cfe88 | 1036 | clocks = <&prcc_pclk 6 2>; |
61122cf2 | 1037 | }; |
5d0769f0 AB |
1038 | }; |
1039 | }; |