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Commit | Line | Data |
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5d0769f0 AB |
1 | /* |
2 | * Copyright 2012 Linaro Ltd | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
90c40257 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
841cd0c0 | 13 | #include <dt-bindings/mfd/dbx500-prcmu.h> |
067addec | 14 | #include <dt-bindings/arm/ux500_pm_domains.h> |
807e8838 | 15 | #include "skeleton.dtsi" |
5d0769f0 AB |
16 | |
17 | / { | |
bf64dd26 LW |
18 | cpus { |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
21 | enable-method = "ste,dbx500-smp"; | |
22 | ||
23 | cpu-map { | |
24 | cluster0 { | |
25 | core0 { | |
26 | cpu = <&CPU0>; | |
27 | }; | |
28 | core1 { | |
29 | cpu = <&CPU1>; | |
30 | }; | |
31 | }; | |
32 | }; | |
33 | CPU0: cpu@300 { | |
34 | device_type = "cpu"; | |
35 | compatible = "arm,cortex-a9"; | |
36 | reg = <0x300>; | |
37 | }; | |
38 | CPU1: cpu@301 { | |
39 | device_type = "cpu"; | |
40 | compatible = "arm,cortex-a9"; | |
41 | reg = <0x301>; | |
42 | }; | |
43 | }; | |
44 | ||
b1ba1439 | 45 | soc { |
5d0769f0 AB |
46 | #address-cells = <1>; |
47 | #size-cells = <1>; | |
7e0ce270 | 48 | compatible = "stericsson,db8500"; |
dab6487e | 49 | interrupt-parent = <&intc>; |
5d0769f0 | 50 | ranges; |
7e0ce270 | 51 | |
b557457f LW |
52 | ptm@801ae000 { |
53 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
54 | reg = <0x801ae000 0x1000>; | |
55 | ||
56 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
57 | clock-names = "apb_pclk", "atclk"; | |
58 | cpu = <&CPU0>; | |
59 | port { | |
60 | ptm0_out_port: endpoint { | |
61 | remote-endpoint = <&funnel_in_port0>; | |
62 | }; | |
63 | }; | |
64 | }; | |
65 | ||
66 | ptm@801af000 { | |
67 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
68 | reg = <0x801af000 0x1000>; | |
69 | ||
70 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
71 | clock-names = "apb_pclk", "atclk"; | |
72 | cpu = <&CPU1>; | |
73 | port { | |
74 | ptm1_out_port: endpoint { | |
75 | remote-endpoint = <&funnel_in_port1>; | |
76 | }; | |
77 | }; | |
78 | }; | |
79 | ||
80 | funnel@801a6000 { | |
81 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
82 | reg = <0x801a6000 0x1000>; | |
83 | ||
84 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
85 | clock-names = "apb_pclk", "atclk"; | |
86 | ports { | |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
89 | ||
90 | /* funnel output ports */ | |
91 | port@0 { | |
92 | reg = <0>; | |
93 | funnel_out_port: endpoint { | |
94 | remote-endpoint = | |
95 | <&replicator_in_port0>; | |
96 | }; | |
97 | }; | |
98 | ||
99 | /* funnel input ports */ | |
100 | port@1 { | |
101 | reg = <0>; | |
102 | funnel_in_port0: endpoint { | |
103 | slave-mode; | |
104 | remote-endpoint = <&ptm0_out_port>; | |
105 | }; | |
106 | }; | |
107 | ||
108 | port@2 { | |
109 | reg = <1>; | |
110 | funnel_in_port1: endpoint { | |
111 | slave-mode; | |
112 | remote-endpoint = <&ptm1_out_port>; | |
113 | }; | |
114 | }; | |
115 | }; | |
116 | }; | |
117 | ||
118 | replicator { | |
119 | compatible = "arm,coresight-replicator"; | |
120 | clocks = <&prcmu_clk PRCMU_APEATCLK>; | |
121 | clock-names = "atclk"; | |
122 | ||
123 | ports { | |
124 | #address-cells = <1>; | |
125 | #size-cells = <0>; | |
126 | ||
127 | /* replicator output ports */ | |
128 | port@0 { | |
129 | reg = <0>; | |
130 | replicator_out_port0: endpoint { | |
131 | remote-endpoint = <&tpiu_in_port>; | |
132 | }; | |
133 | }; | |
134 | port@1 { | |
135 | reg = <1>; | |
136 | replicator_out_port1: endpoint { | |
137 | remote-endpoint = <&etb_in_port>; | |
138 | }; | |
139 | }; | |
140 | ||
141 | /* replicator input port */ | |
142 | port@2 { | |
143 | reg = <0>; | |
144 | replicator_in_port0: endpoint { | |
145 | slave-mode; | |
146 | remote-endpoint = <&funnel_out_port>; | |
147 | }; | |
148 | }; | |
149 | }; | |
150 | }; | |
151 | ||
152 | tpiu@80190000 { | |
153 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
154 | reg = <0x80190000 0x1000>; | |
155 | ||
156 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
157 | clock-names = "apb_pclk", "atclk"; | |
158 | port { | |
159 | tpiu_in_port: endpoint { | |
160 | slave-mode; | |
161 | remote-endpoint = <&replicator_out_port0>; | |
162 | }; | |
163 | }; | |
164 | }; | |
165 | ||
166 | etb@801a4000 { | |
167 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
168 | reg = <0x801a4000 0x1000>; | |
169 | ||
170 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
171 | clock-names = "apb_pclk", "atclk"; | |
172 | port { | |
173 | etb_in_port: endpoint { | |
174 | slave-mode; | |
175 | remote-endpoint = <&replicator_out_port1>; | |
176 | }; | |
177 | }; | |
178 | }; | |
179 | ||
dab6487e LJ |
180 | intc: interrupt-controller@a0411000 { |
181 | compatible = "arm,cortex-a9-gic"; | |
182 | #interrupt-cells = <3>; | |
183 | #address-cells = <1>; | |
184 | interrupt-controller; | |
dab6487e LJ |
185 | reg = <0xa0411000 0x1000>, |
186 | <0xa0410100 0x100>; | |
187 | }; | |
188 | ||
48793410 LW |
189 | scu@a04100000 { |
190 | compatible = "arm,cortex-a9-scu"; | |
191 | reg = <0xa0410000 0x100>; | |
192 | }; | |
193 | ||
724814b4 LW |
194 | /* |
195 | * The backup RAM is used for retention during sleep | |
196 | * and various things like spin tables | |
197 | */ | |
198 | backupram@80150000 { | |
199 | compatible = "ste,dbx500-backupram"; | |
200 | reg = <0x80150000 0x2000>; | |
201 | }; | |
202 | ||
f1949ea0 LJ |
203 | L2: l2-cache { |
204 | compatible = "arm,pl310-cache"; | |
205 | reg = <0xa0412000 0x1000>; | |
90c40257 | 206 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; |
f1949ea0 LJ |
207 | cache-unified; |
208 | cache-level = <2>; | |
209 | }; | |
210 | ||
7e0ce270 LJ |
211 | pmu { |
212 | compatible = "arm,cortex-a9-pmu"; | |
90c40257 | 213 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 LJ |
214 | }; |
215 | ||
6c669359 UH |
216 | pm_domains: pm_domains0 { |
217 | compatible = "stericsson,ux500-pm-domains"; | |
218 | #power-domain-cells = <1>; | |
219 | }; | |
8132ed1b | 220 | |
841cd0c0 LJ |
221 | clocks { |
222 | compatible = "stericsson,u8500-clks"; | |
5dc0fe19 LW |
223 | /* |
224 | * Registers for the CLKRST block on peripheral | |
225 | * groups 1, 2, 3, 5, 6, | |
226 | */ | |
227 | reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, | |
228 | <0x8000f000 0x1000>, <0xa03ff000 0x1000>, | |
229 | <0xa03cf000 0x1000>; | |
841cd0c0 LJ |
230 | |
231 | prcmu_clk: prcmu-clock { | |
232 | #clock-cells = <1>; | |
233 | }; | |
fcbe5e90 LJ |
234 | |
235 | prcc_pclk: prcc-periph-clock { | |
236 | #clock-cells = <2>; | |
237 | }; | |
2588fea6 LJ |
238 | |
239 | prcc_kclk: prcc-kernel-clock { | |
240 | #clock-cells = <2>; | |
241 | }; | |
589d9839 LJ |
242 | |
243 | rtc_clk: rtc32k-clock { | |
244 | #clock-cells = <0>; | |
245 | }; | |
309012d7 LJ |
246 | |
247 | smp_twd_clk: smp-twd-clock { | |
248 | #clock-cells = <0>; | |
249 | }; | |
841cd0c0 LJ |
250 | }; |
251 | ||
8132ed1b LJ |
252 | mtu@a03c6000 { |
253 | /* Nomadik System Timer */ | |
254 | compatible = "st,nomadik-mtu"; | |
255 | reg = <0xa03c6000 0x1000>; | |
256 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | |
257 | ||
258 | clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; | |
259 | clock-names = "timclk", "apb_pclk"; | |
260 | }; | |
261 | ||
71de5c46 LJ |
262 | timer@a0410600 { |
263 | compatible = "arm,cortex-a9-twd-timer"; | |
264 | reg = <0xa0410600 0x20>; | |
90c40257 | 265 | interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ |
a8acb1ec LJ |
266 | |
267 | clocks = <&smp_twd_clk>; | |
71de5c46 LJ |
268 | }; |
269 | ||
48793410 LW |
270 | watchdog@a0410620 { |
271 | compatible = "arm,cortex-a9-twd-wdt"; | |
272 | reg = <0xa0410620 0x20>; | |
273 | interrupts = <1 14 0x304>; | |
274 | clocks = <&smp_twd_clk>; | |
275 | }; | |
276 | ||
7e0ce270 | 277 | rtc@80154000 { |
ddb3b99c | 278 | compatible = "arm,rtc-pl031", "arm,primecell"; |
7e0ce270 | 279 | reg = <0x80154000 0x1000>; |
90c40257 | 280 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
d299b5a5 LJ |
281 | |
282 | clocks = <&rtc_clk>; | |
283 | clock-names = "apb_pclk"; | |
7e0ce270 LJ |
284 | }; |
285 | ||
286 | gpio0: gpio@8012e000 { | |
287 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 288 | "st,nomadik-gpio"; |
7e0ce270 | 289 | reg = <0x8012e000 0x80>; |
90c40257 | 290 | interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
291 | interrupt-controller; |
292 | #interrupt-cells = <2>; | |
61be4981 | 293 | st,supports-sleepmode; |
7e0ce270 | 294 | gpio-controller; |
c0b133bd LJ |
295 | #gpio-cells = <2>; |
296 | gpio-bank = <0>; | |
9d891073 LJ |
297 | |
298 | clocks = <&prcc_pclk 1 9>; | |
7e0ce270 LJ |
299 | }; |
300 | ||
301 | gpio1: gpio@8012e080 { | |
302 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 303 | "st,nomadik-gpio"; |
7e0ce270 | 304 | reg = <0x8012e080 0x80>; |
90c40257 | 305 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
306 | interrupt-controller; |
307 | #interrupt-cells = <2>; | |
61be4981 | 308 | st,supports-sleepmode; |
7e0ce270 | 309 | gpio-controller; |
c0b133bd LJ |
310 | #gpio-cells = <2>; |
311 | gpio-bank = <1>; | |
9d891073 LJ |
312 | |
313 | clocks = <&prcc_pclk 1 9>; | |
7e0ce270 LJ |
314 | }; |
315 | ||
316 | gpio2: gpio@8000e000 { | |
317 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 318 | "st,nomadik-gpio"; |
7e0ce270 | 319 | reg = <0x8000e000 0x80>; |
90c40257 | 320 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
321 | interrupt-controller; |
322 | #interrupt-cells = <2>; | |
61be4981 | 323 | st,supports-sleepmode; |
7e0ce270 | 324 | gpio-controller; |
c0b133bd LJ |
325 | #gpio-cells = <2>; |
326 | gpio-bank = <2>; | |
9d891073 LJ |
327 | |
328 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
329 | }; |
330 | ||
331 | gpio3: gpio@8000e080 { | |
332 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 333 | "st,nomadik-gpio"; |
7e0ce270 | 334 | reg = <0x8000e080 0x80>; |
90c40257 | 335 | interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
336 | interrupt-controller; |
337 | #interrupt-cells = <2>; | |
61be4981 | 338 | st,supports-sleepmode; |
7e0ce270 | 339 | gpio-controller; |
c0b133bd LJ |
340 | #gpio-cells = <2>; |
341 | gpio-bank = <3>; | |
9d891073 LJ |
342 | |
343 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
344 | }; |
345 | ||
346 | gpio4: gpio@8000e100 { | |
347 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 348 | "st,nomadik-gpio"; |
7e0ce270 | 349 | reg = <0x8000e100 0x80>; |
90c40257 | 350 | interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
351 | interrupt-controller; |
352 | #interrupt-cells = <2>; | |
61be4981 | 353 | st,supports-sleepmode; |
7e0ce270 | 354 | gpio-controller; |
c0b133bd LJ |
355 | #gpio-cells = <2>; |
356 | gpio-bank = <4>; | |
9d891073 LJ |
357 | |
358 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
359 | }; |
360 | ||
361 | gpio5: gpio@8000e180 { | |
362 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 363 | "st,nomadik-gpio"; |
7e0ce270 | 364 | reg = <0x8000e180 0x80>; |
90c40257 | 365 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
366 | interrupt-controller; |
367 | #interrupt-cells = <2>; | |
61be4981 | 368 | st,supports-sleepmode; |
7e0ce270 | 369 | gpio-controller; |
c0b133bd LJ |
370 | #gpio-cells = <2>; |
371 | gpio-bank = <5>; | |
9d891073 LJ |
372 | |
373 | clocks = <&prcc_pclk 3 8>; | |
7e0ce270 LJ |
374 | }; |
375 | ||
376 | gpio6: gpio@8011e000 { | |
377 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 378 | "st,nomadik-gpio"; |
7e0ce270 | 379 | reg = <0x8011e000 0x80>; |
90c40257 | 380 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
381 | interrupt-controller; |
382 | #interrupt-cells = <2>; | |
61be4981 | 383 | st,supports-sleepmode; |
7e0ce270 | 384 | gpio-controller; |
c0b133bd LJ |
385 | #gpio-cells = <2>; |
386 | gpio-bank = <6>; | |
9d891073 | 387 | |
d591640a | 388 | clocks = <&prcc_pclk 2 11>; |
7e0ce270 LJ |
389 | }; |
390 | ||
391 | gpio7: gpio@8011e080 { | |
392 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 393 | "st,nomadik-gpio"; |
7e0ce270 | 394 | reg = <0x8011e080 0x80>; |
90c40257 | 395 | interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
396 | interrupt-controller; |
397 | #interrupt-cells = <2>; | |
61be4981 | 398 | st,supports-sleepmode; |
7e0ce270 | 399 | gpio-controller; |
c0b133bd LJ |
400 | #gpio-cells = <2>; |
401 | gpio-bank = <7>; | |
9d891073 | 402 | |
d591640a | 403 | clocks = <&prcc_pclk 2 11>; |
7e0ce270 LJ |
404 | }; |
405 | ||
406 | gpio8: gpio@a03fe000 { | |
407 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 408 | "st,nomadik-gpio"; |
7e0ce270 | 409 | reg = <0xa03fe000 0x80>; |
90c40257 | 410 | interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
411 | interrupt-controller; |
412 | #interrupt-cells = <2>; | |
61be4981 | 413 | st,supports-sleepmode; |
7e0ce270 | 414 | gpio-controller; |
c0b133bd LJ |
415 | #gpio-cells = <2>; |
416 | gpio-bank = <8>; | |
9d891073 | 417 | |
84873cb7 | 418 | clocks = <&prcc_pclk 5 1>; |
7e0ce270 LJ |
419 | }; |
420 | ||
8979cfef | 421 | pinctrl { |
818d99a9 | 422 | compatible = "stericsson,db8500-pinctrl"; |
8979cfef | 423 | prcm = <&prcmu>; |
5910de9e LJ |
424 | }; |
425 | ||
b32dc865 | 426 | usb_per5@a03e0000 { |
4a6cd43f | 427 | compatible = "stericsson,db8500-musb"; |
7e0ce270 | 428 | reg = <0xa03e0000 0x10000>; |
90c40257 | 429 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
b32dc865 LJ |
430 | interrupt-names = "mc"; |
431 | ||
432 | dr_mode = "otg"; | |
433 | ||
434 | dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ | |
435 | <&dma 38 0 0x0>, /* Logical - MemToDev */ | |
436 | <&dma 37 0 0x2>, /* Logical - DevToMem */ | |
437 | <&dma 37 0 0x0>, /* Logical - MemToDev */ | |
438 | <&dma 36 0 0x2>, /* Logical - DevToMem */ | |
439 | <&dma 36 0 0x0>, /* Logical - MemToDev */ | |
440 | <&dma 19 0 0x2>, /* Logical - DevToMem */ | |
441 | <&dma 19 0 0x0>, /* Logical - MemToDev */ | |
442 | <&dma 18 0 0x2>, /* Logical - DevToMem */ | |
443 | <&dma 18 0 0x0>, /* Logical - MemToDev */ | |
444 | <&dma 17 0 0x2>, /* Logical - DevToMem */ | |
445 | <&dma 17 0 0x0>, /* Logical - MemToDev */ | |
446 | <&dma 16 0 0x2>, /* Logical - DevToMem */ | |
447 | <&dma 16 0 0x0>, /* Logical - MemToDev */ | |
448 | <&dma 39 0 0x2>, /* Logical - DevToMem */ | |
449 | <&dma 39 0 0x0>; /* Logical - MemToDev */ | |
450 | ||
451 | dma-names = "iep_1_9", "oep_1_9", | |
452 | "iep_2_10", "oep_2_10", | |
453 | "iep_3_11", "oep_3_11", | |
454 | "iep_4_12", "oep_4_12", | |
455 | "iep_5_13", "oep_5_13", | |
456 | "iep_6_14", "oep_6_14", | |
457 | "iep_7_15", "oep_7_15", | |
458 | "iep_8", "oep_8"; | |
e47339ff LJ |
459 | |
460 | clocks = <&prcc_pclk 5 0>; | |
7e0ce270 LJ |
461 | }; |
462 | ||
ba074aec LJ |
463 | dma: dma-controller@801C0000 { |
464 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | |
7e0ce270 | 465 | reg = <0x801C0000 0x1000 0x40010000 0x800>; |
70d39a8d | 466 | reg-names = "base", "lcpa"; |
90c40257 | 467 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
ba074aec LJ |
468 | |
469 | #dma-cells = <3>; | |
d37fcdb6 | 470 | memcpy-channels = <56 57 58 59 60>; |
e064cb24 LJ |
471 | |
472 | clocks = <&prcmu_clk PRCMU_DMACLK>; | |
7e0ce270 LJ |
473 | }; |
474 | ||
8979cfef | 475 | prcmu: prcmu@80157000 { |
7e0ce270 | 476 | compatible = "stericsson,db8500-prcmu"; |
4d26aa30 | 477 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; |
e73081d9 | 478 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; |
90c40257 | 479 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 | 480 | #address-cells = <1>; |
3de3d749 | 481 | #size-cells = <1>; |
c09090bb LJ |
482 | interrupt-controller; |
483 | #interrupt-cells = <2>; | |
3de3d749 LJ |
484 | ranges; |
485 | ||
ccf74f76 | 486 | prcmu-timer-4@80157450 { |
3de3d749 LJ |
487 | compatible = "stericsson,db8500-prcmu-timer-4"; |
488 | reg = <0x80157450 0xC>; | |
489 | }; | |
7e0ce270 | 490 | |
98585616 LJ |
491 | cpufreq { |
492 | compatible = "stericsson,cpufreq-ux500"; | |
493 | clocks = <&prcmu_clk PRCMU_ARMSS>; | |
494 | clock-names = "armss"; | |
495 | status = "disabled"; | |
496 | }; | |
497 | ||
dc1956b5 | 498 | thermal@801573c0 { |
499 | compatible = "stericsson,db8500-thermal"; | |
500 | reg = <0x801573c0 0x40>; | |
90c40257 LW |
501 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, |
502 | <22 IRQ_TYPE_LEVEL_HIGH>; | |
dc1956b5 | 503 | interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; |
504 | status = "disabled"; | |
1d3f99f5 | 505 | }; |
dc1956b5 | 506 | |
e5999f28 LJ |
507 | db8500-prcmu-regulators { |
508 | compatible = "stericsson,db8500-prcmu-regulator"; | |
509 | ||
510 | // DB8500_REGULATOR_VAPE | |
511 | db8500_vape_reg: db8500_vape { | |
da26848a | 512 | regulator-compatible = "db8500_vape"; |
e5999f28 LJ |
513 | regulator-always-on; |
514 | }; | |
515 | ||
516 | // DB8500_REGULATOR_VARM | |
517 | db8500_varm_reg: db8500_varm { | |
da26848a | 518 | regulator-compatible = "db8500_varm"; |
e5999f28 LJ |
519 | }; |
520 | ||
521 | // DB8500_REGULATOR_VMODEM | |
522 | db8500_vmodem_reg: db8500_vmodem { | |
da26848a | 523 | regulator-compatible = "db8500_vmodem"; |
e5999f28 LJ |
524 | }; |
525 | ||
526 | // DB8500_REGULATOR_VPLL | |
527 | db8500_vpll_reg: db8500_vpll { | |
da26848a | 528 | regulator-compatible = "db8500_vpll"; |
e5999f28 LJ |
529 | }; |
530 | ||
531 | // DB8500_REGULATOR_VSMPS1 | |
532 | db8500_vsmps1_reg: db8500_vsmps1 { | |
da26848a | 533 | regulator-compatible = "db8500_vsmps1"; |
e5999f28 LJ |
534 | }; |
535 | ||
536 | // DB8500_REGULATOR_VSMPS2 | |
537 | db8500_vsmps2_reg: db8500_vsmps2 { | |
da26848a | 538 | regulator-compatible = "db8500_vsmps2"; |
e5999f28 LJ |
539 | }; |
540 | ||
541 | // DB8500_REGULATOR_VSMPS3 | |
542 | db8500_vsmps3_reg: db8500_vsmps3 { | |
da26848a | 543 | regulator-compatible = "db8500_vsmps3"; |
e5999f28 LJ |
544 | }; |
545 | ||
546 | // DB8500_REGULATOR_VRF1 | |
547 | db8500_vrf1_reg: db8500_vrf1 { | |
da26848a | 548 | regulator-compatible = "db8500_vrf1"; |
e5999f28 LJ |
549 | }; |
550 | ||
551 | // DB8500_REGULATOR_SWITCH_SVAMMDSP | |
552 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { | |
da26848a | 553 | regulator-compatible = "db8500_sva_mmdsp"; |
e5999f28 LJ |
554 | }; |
555 | ||
556 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET | |
557 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { | |
da26848a | 558 | regulator-compatible = "db8500_sva_mmdsp_ret"; |
e5999f28 LJ |
559 | }; |
560 | ||
561 | // DB8500_REGULATOR_SWITCH_SVAPIPE | |
562 | db8500_sva_pipe_reg: db8500_sva_pipe { | |
da26848a | 563 | regulator-compatible = "db8500_sva_pipe"; |
e5999f28 LJ |
564 | }; |
565 | ||
566 | // DB8500_REGULATOR_SWITCH_SIAMMDSP | |
567 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { | |
da26848a | 568 | regulator-compatible = "db8500_sia_mmdsp"; |
e5999f28 LJ |
569 | }; |
570 | ||
571 | // DB8500_REGULATOR_SWITCH_SIAMMDSPRET | |
572 | db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { | |
e5999f28 LJ |
573 | }; |
574 | ||
575 | // DB8500_REGULATOR_SWITCH_SIAPIPE | |
576 | db8500_sia_pipe_reg: db8500_sia_pipe { | |
da26848a | 577 | regulator-compatible = "db8500_sia_pipe"; |
e5999f28 LJ |
578 | }; |
579 | ||
580 | // DB8500_REGULATOR_SWITCH_SGA | |
581 | db8500_sga_reg: db8500_sga { | |
da26848a | 582 | regulator-compatible = "db8500_sga"; |
e5999f28 LJ |
583 | vin-supply = <&db8500_vape_reg>; |
584 | }; | |
585 | ||
586 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE | |
587 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { | |
da26848a | 588 | regulator-compatible = "db8500_b2r2_mcde"; |
e5999f28 LJ |
589 | vin-supply = <&db8500_vape_reg>; |
590 | }; | |
591 | ||
592 | // DB8500_REGULATOR_SWITCH_ESRAM12 | |
593 | db8500_esram12_reg: db8500_esram12 { | |
da26848a | 594 | regulator-compatible = "db8500_esram12"; |
e5999f28 LJ |
595 | }; |
596 | ||
597 | // DB8500_REGULATOR_SWITCH_ESRAM12RET | |
598 | db8500_esram12_ret_reg: db8500_esram12_ret { | |
da26848a | 599 | regulator-compatible = "db8500_esram12_ret"; |
e5999f28 LJ |
600 | }; |
601 | ||
602 | // DB8500_REGULATOR_SWITCH_ESRAM34 | |
603 | db8500_esram34_reg: db8500_esram34 { | |
da26848a | 604 | regulator-compatible = "db8500_esram34"; |
e5999f28 LJ |
605 | }; |
606 | ||
607 | // DB8500_REGULATOR_SWITCH_ESRAM34RET | |
608 | db8500_esram34_ret_reg: db8500_esram34_ret { | |
da26848a | 609 | regulator-compatible = "db8500_esram34_ret"; |
e5999f28 LJ |
610 | }; |
611 | }; | |
612 | ||
d52701d3 | 613 | ab8500 { |
7e0ce270 | 614 | compatible = "stericsson,ab8500"; |
8d4c6d45 | 615 | interrupt-parent = <&intc>; |
90c40257 | 616 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
732973c8 LJ |
617 | interrupt-controller; |
618 | #interrupt-cells = <2>; | |
4a85c7fa | 619 | |
348f3bc6 LJ |
620 | ab8500_gpio: ab8500-gpio { |
621 | gpio-controller; | |
622 | #gpio-cells = <2>; | |
623 | }; | |
624 | ||
d4b29ac1 LJ |
625 | ab8500-rtc { |
626 | compatible = "stericsson,ab8500-rtc"; | |
90c40257 LW |
627 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH |
628 | 18 IRQ_TYPE_LEVEL_HIGH>; | |
d4b29ac1 LJ |
629 | interrupt-names = "60S", "ALARM"; |
630 | }; | |
631 | ||
4eda9129 LJ |
632 | ab8500-gpadc { |
633 | compatible = "stericsson,ab8500-gpadc"; | |
90c40257 LW |
634 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH |
635 | 39 IRQ_TYPE_LEVEL_HIGH>; | |
4eda9129 LJ |
636 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; |
637 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
638 | }; | |
639 | ||
e0f1abeb R |
640 | ab8500_battery: ab8500_battery { |
641 | stericsson,battery-type = "LIPO"; | |
642 | thermistor-on-batctrl; | |
643 | }; | |
644 | ||
645 | ab8500_fg { | |
646 | compatible = "stericsson,ab8500-fg"; | |
647 | battery = <&ab8500_battery>; | |
648 | }; | |
649 | ||
bd9e8ab2 R |
650 | ab8500_btemp { |
651 | compatible = "stericsson,ab8500-btemp"; | |
652 | battery = <&ab8500_battery>; | |
653 | }; | |
654 | ||
4aef72db R |
655 | ab8500_charger { |
656 | compatible = "stericsson,ab8500-charger"; | |
657 | battery = <&ab8500_battery>; | |
658 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
659 | }; | |
660 | ||
a12810ab R |
661 | ab8500_chargalg { |
662 | compatible = "stericsson,ab8500-chargalg"; | |
663 | battery = <&ab8500_battery>; | |
664 | }; | |
665 | ||
e0f1abeb | 666 | ab8500_usb { |
ee189cef | 667 | compatible = "stericsson,ab8500-usb"; |
90c40257 LW |
668 | interrupts = < 90 IRQ_TYPE_LEVEL_HIGH |
669 | 96 IRQ_TYPE_LEVEL_HIGH | |
670 | 14 IRQ_TYPE_LEVEL_HIGH | |
671 | 15 IRQ_TYPE_LEVEL_HIGH | |
672 | 79 IRQ_TYPE_LEVEL_HIGH | |
673 | 74 IRQ_TYPE_LEVEL_HIGH | |
674 | 75 IRQ_TYPE_LEVEL_HIGH>; | |
ee189cef LJ |
675 | interrupt-names = "ID_WAKEUP_R", |
676 | "ID_WAKEUP_F", | |
677 | "VBUS_DET_F", | |
678 | "VBUS_DET_R", | |
679 | "USB_LINK_STATUS", | |
680 | "USB_ADP_PROBE_PLUG", | |
681 | "USB_ADP_PROBE_UNPLUG"; | |
99b38eef | 682 | vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; |
ee189cef LJ |
683 | v-ape-supply = <&db8500_vape_reg>; |
684 | musb_1v8-supply = <&db8500_vsmps2_reg>; | |
685 | }; | |
686 | ||
12cb7bd4 | 687 | ab8500-ponkey { |
74630706 | 688 | compatible = "stericsson,ab8500-poweron-key"; |
90c40257 LW |
689 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH |
690 | 7 IRQ_TYPE_LEVEL_HIGH>; | |
12cb7bd4 LJ |
691 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; |
692 | }; | |
693 | ||
401cd1b8 LJ |
694 | ab8500-sysctrl { |
695 | compatible = "stericsson,ab8500-sysctrl"; | |
696 | }; | |
697 | ||
78451de7 LJ |
698 | ab8500-pwm { |
699 | compatible = "stericsson,ab8500-pwm"; | |
700 | }; | |
701 | ||
215891ec LJ |
702 | ab8500-debugfs { |
703 | compatible = "stericsson,ab8500-debug"; | |
704 | }; | |
4a85c7fa | 705 | |
9c06af30 LJ |
706 | codec: ab8500-codec { |
707 | compatible = "stericsson,ab8500-codec"; | |
708 | ||
f99808a6 FB |
709 | V-AUD-supply = <&ab8500_ldo_audio_reg>; |
710 | V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; | |
711 | V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; | |
712 | V-DMIC-supply = <&ab8500_ldo_dmic_reg>; | |
713 | ||
9c06af30 LJ |
714 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ |
715 | }; | |
716 | ||
62ebfe6b LJ |
717 | ext_regulators: ab8500-ext-regulators { |
718 | compatible = "stericsson,ab8500-ext-regulator"; | |
719 | ||
720 | ab8500_ext1_reg: ab8500_ext1 { | |
721 | regulator-compatible = "ab8500_ext1"; | |
722 | regulator-min-microvolt = <1800000>; | |
723 | regulator-max-microvolt = <1800000>; | |
724 | regulator-boot-on; | |
725 | regulator-always-on; | |
726 | }; | |
727 | ||
728 | ab8500_ext2_reg: ab8500_ext2 { | |
729 | regulator-compatible = "ab8500_ext2"; | |
730 | regulator-min-microvolt = <1360000>; | |
731 | regulator-max-microvolt = <1360000>; | |
732 | regulator-boot-on; | |
733 | regulator-always-on; | |
734 | }; | |
735 | ||
736 | ab8500_ext3_reg: ab8500_ext3 { | |
737 | regulator-compatible = "ab8500_ext3"; | |
738 | regulator-min-microvolt = <3400000>; | |
739 | regulator-max-microvolt = <3400000>; | |
740 | regulator-boot-on; | |
741 | }; | |
742 | }; | |
743 | ||
4a85c7fa LJ |
744 | ab8500-regulators { |
745 | compatible = "stericsson,ab8500-regulator"; | |
75f0999a | 746 | vin-supply = <&ab8500_ext3_reg>; |
4a85c7fa LJ |
747 | |
748 | // supplies to the display/camera | |
749 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | |
da26848a | 750 | regulator-compatible = "ab8500_ldo_aux1"; |
4a85c7fa LJ |
751 | regulator-min-microvolt = <2500000>; |
752 | regulator-max-microvolt = <2900000>; | |
753 | regulator-boot-on; | |
754 | /* BUG: If turned off MMC will be affected. */ | |
755 | regulator-always-on; | |
756 | }; | |
757 | ||
758 | // supplies to the on-board eMMC | |
759 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { | |
da26848a | 760 | regulator-compatible = "ab8500_ldo_aux2"; |
4a85c7fa LJ |
761 | regulator-min-microvolt = <1100000>; |
762 | regulator-max-microvolt = <3300000>; | |
763 | }; | |
764 | ||
765 | // supply for VAUX3; SDcard slots | |
766 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { | |
da26848a | 767 | regulator-compatible = "ab8500_ldo_aux3"; |
4a85c7fa LJ |
768 | regulator-min-microvolt = <1100000>; |
769 | regulator-max-microvolt = <3300000>; | |
770 | }; | |
771 | ||
772 | // supply for v-intcore12; VINTCORE12 LDO | |
99b38eef FB |
773 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
774 | regulator-compatible = "ab8500_ldo_intcore"; | |
4a85c7fa LJ |
775 | }; |
776 | ||
777 | // supply for tvout; gpadc; TVOUT LDO | |
778 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { | |
da26848a | 779 | regulator-compatible = "ab8500_ldo_tvout"; |
4a85c7fa LJ |
780 | }; |
781 | ||
782 | // supply for ab8500-usb; USB LDO | |
783 | ab8500_ldo_usb_reg: ab8500_ldo_usb { | |
da26848a | 784 | regulator-compatible = "ab8500_ldo_usb"; |
4a85c7fa LJ |
785 | }; |
786 | ||
787 | // supply for ab8500-vaudio; VAUDIO LDO | |
788 | ab8500_ldo_audio_reg: ab8500_ldo_audio { | |
da26848a | 789 | regulator-compatible = "ab8500_ldo_audio"; |
4a85c7fa LJ |
790 | }; |
791 | ||
4aa44874 | 792 | // supply for v-anamic1 VAMIC1 LDO |
4a85c7fa | 793 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { |
da26848a | 794 | regulator-compatible = "ab8500_ldo_anamic1"; |
4a85c7fa LJ |
795 | }; |
796 | ||
797 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 | |
5510ed9f FB |
798 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
799 | regulator-compatible = "ab8500_ldo_anamic2"; | |
4a85c7fa LJ |
800 | }; |
801 | ||
802 | // supply for v-dmic; VDMIC LDO | |
803 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { | |
da26848a | 804 | regulator-compatible = "ab8500_ldo_dmic"; |
4a85c7fa LJ |
805 | }; |
806 | ||
807 | // supply for U8500 CSI/DSI; VANA LDO | |
808 | ab8500_ldo_ana_reg: ab8500_ldo_ana { | |
da26848a | 809 | regulator-compatible = "ab8500_ldo_ana"; |
4a85c7fa LJ |
810 | }; |
811 | }; | |
7e0ce270 LJ |
812 | }; |
813 | }; | |
814 | ||
815 | i2c@80004000 { | |
d524fa7f | 816 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 817 | reg = <0x80004000 0x1000>; |
90c40257 | 818 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 819 | |
7e0ce270 LJ |
820 | #address-cells = <1>; |
821 | #size-cells = <0>; | |
d524fa7f LJ |
822 | v-i2c-supply = <&db8500_vape_reg>; |
823 | ||
824 | clock-frequency = <400000>; | |
afd653e9 LJ |
825 | clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; |
826 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 827 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
828 | }; |
829 | ||
830 | i2c@80122000 { | |
d524fa7f | 831 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 832 | reg = <0x80122000 0x1000>; |
90c40257 | 833 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 834 | |
7e0ce270 LJ |
835 | #address-cells = <1>; |
836 | #size-cells = <0>; | |
d524fa7f LJ |
837 | v-i2c-supply = <&db8500_vape_reg>; |
838 | ||
839 | clock-frequency = <400000>; | |
afd653e9 LJ |
840 | |
841 | clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; | |
842 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 843 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
844 | }; |
845 | ||
846 | i2c@80128000 { | |
d524fa7f | 847 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 848 | reg = <0x80128000 0x1000>; |
90c40257 | 849 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 850 | |
7e0ce270 LJ |
851 | #address-cells = <1>; |
852 | #size-cells = <0>; | |
d524fa7f LJ |
853 | v-i2c-supply = <&db8500_vape_reg>; |
854 | ||
855 | clock-frequency = <400000>; | |
afd653e9 LJ |
856 | |
857 | clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; | |
858 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 859 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
860 | }; |
861 | ||
862 | i2c@80110000 { | |
d524fa7f | 863 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 864 | reg = <0x80110000 0x1000>; |
90c40257 | 865 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 866 | |
7e0ce270 LJ |
867 | #address-cells = <1>; |
868 | #size-cells = <0>; | |
d524fa7f LJ |
869 | v-i2c-supply = <&db8500_vape_reg>; |
870 | ||
871 | clock-frequency = <400000>; | |
afd653e9 LJ |
872 | |
873 | clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; | |
874 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 875 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
876 | }; |
877 | ||
878 | i2c@8012a000 { | |
d524fa7f | 879 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 880 | reg = <0x8012a000 0x1000>; |
90c40257 | 881 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 882 | |
7e0ce270 LJ |
883 | #address-cells = <1>; |
884 | #size-cells = <0>; | |
d524fa7f LJ |
885 | v-i2c-supply = <&db8500_vape_reg>; |
886 | ||
887 | clock-frequency = <400000>; | |
afd653e9 | 888 | |
72b3e249 | 889 | clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; |
afd653e9 | 890 | clock-names = "i2cclk", "apb_pclk"; |
29417fe8 | 891 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
892 | }; |
893 | ||
894 | ssp@80002000 { | |
895 | compatible = "arm,pl022", "arm,primecell"; | |
c164fa62 | 896 | reg = <0x80002000 0x1000>; |
90c40257 | 897 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 LJ |
898 | #address-cells = <1>; |
899 | #size-cells = <0>; | |
6e1484c2 | 900 | clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; |
80fbe30f | 901 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
902 | dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ |
903 | <&dma 8 0 0x0>; /* Logical - MemToDev */ | |
904 | dma-names = "rx", "tx"; | |
770e2f6b | 905 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
906 | }; |
907 | ||
908 | ssp@80003000 { | |
909 | compatible = "arm,pl022", "arm,primecell"; | |
910 | reg = <0x80003000 0x1000>; | |
911 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; | |
912 | #address-cells = <1>; | |
913 | #size-cells = <0>; | |
914 | clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; | |
80fbe30f | 915 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
916 | dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ |
917 | <&dma 9 0 0x0>; /* Logical - MemToDev */ | |
918 | dma-names = "rx", "tx"; | |
770e2f6b | 919 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
920 | }; |
921 | ||
922 | spi@8011a000 { | |
923 | compatible = "arm,pl022", "arm,primecell"; | |
924 | reg = <0x8011a000 0x1000>; | |
925 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | |
926 | #address-cells = <1>; | |
927 | #size-cells = <0>; | |
928 | /* Same clock wired to kernel and pclk */ | |
929 | clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; | |
80fbe30f | 930 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
931 | dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ |
932 | <&dma 0 0 0x0>; /* Logical - MemToDev */ | |
933 | dma-names = "rx", "tx"; | |
770e2f6b | 934 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
935 | }; |
936 | ||
937 | spi@80112000 { | |
938 | compatible = "arm,pl022", "arm,primecell"; | |
939 | reg = <0x80112000 0x1000>; | |
940 | interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
941 | #address-cells = <1>; | |
942 | #size-cells = <0>; | |
943 | /* Same clock wired to kernel and pclk */ | |
944 | clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; | |
80fbe30f | 945 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
946 | dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ |
947 | <&dma 35 0 0x0>; /* Logical - MemToDev */ | |
948 | dma-names = "rx", "tx"; | |
770e2f6b | 949 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
950 | }; |
951 | ||
952 | spi@80111000 { | |
953 | compatible = "arm,pl022", "arm,primecell"; | |
954 | reg = <0x80111000 0x1000>; | |
955 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | |
956 | #address-cells = <1>; | |
957 | #size-cells = <0>; | |
958 | /* Same clock wired to kernel and pclk */ | |
959 | clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; | |
80fbe30f | 960 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
961 | dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ |
962 | <&dma 33 0 0x0>; /* Logical - MemToDev */ | |
963 | dma-names = "rx", "tx"; | |
770e2f6b | 964 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
965 | }; |
966 | ||
967 | spi@80129000 { | |
968 | compatible = "arm,pl022", "arm,primecell"; | |
969 | reg = <0x80129000 0x1000>; | |
970 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; | |
971 | #address-cells = <1>; | |
972 | #size-cells = <0>; | |
973 | /* Same clock wired to kernel and pclk */ | |
974 | clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; | |
80fbe30f | 975 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
976 | dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ |
977 | <&dma 40 0 0x0>; /* Logical - MemToDev */ | |
978 | dma-names = "rx", "tx"; | |
770e2f6b | 979 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
980 | }; |
981 | ||
109978de | 982 | ux500_serial0: uart@80120000 { |
7e0ce270 LJ |
983 | compatible = "arm,pl011", "arm,primecell"; |
984 | reg = <0x80120000 0x1000>; | |
90c40257 | 985 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
986 | |
987 | dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ | |
988 | <&dma 13 0 0x0>; /* Logical - MemToDev */ | |
989 | dma-names = "rx", "tx"; | |
990 | ||
5a323fb4 LJ |
991 | clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; |
992 | clock-names = "uart", "apb_pclk"; | |
993 | ||
7e0ce270 LJ |
994 | status = "disabled"; |
995 | }; | |
fbff01cc | 996 | |
109978de | 997 | ux500_serial1: uart@80121000 { |
7e0ce270 LJ |
998 | compatible = "arm,pl011", "arm,primecell"; |
999 | reg = <0x80121000 0x1000>; | |
90c40257 | 1000 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
1001 | |
1002 | dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ | |
1003 | <&dma 12 0 0x0>; /* Logical - MemToDev */ | |
1004 | dma-names = "rx", "tx"; | |
1005 | ||
5a323fb4 LJ |
1006 | clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; |
1007 | clock-names = "uart", "apb_pclk"; | |
1008 | ||
7e0ce270 LJ |
1009 | status = "disabled"; |
1010 | }; | |
fbff01cc | 1011 | |
109978de | 1012 | ux500_serial2: uart@80007000 { |
7e0ce270 LJ |
1013 | compatible = "arm,pl011", "arm,primecell"; |
1014 | reg = <0x80007000 0x1000>; | |
90c40257 | 1015 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
1016 | |
1017 | dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ | |
1018 | <&dma 11 0 0x0>; /* Logical - MemToDev */ | |
1019 | dma-names = "rx", "tx"; | |
1020 | ||
5a323fb4 LJ |
1021 | clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; |
1022 | clock-names = "uart", "apb_pclk"; | |
1023 | ||
7e0ce270 LJ |
1024 | status = "disabled"; |
1025 | }; | |
1026 | ||
81bf8c2e | 1027 | sdi0_per1@80126000 { |
7e0ce270 LJ |
1028 | compatible = "arm,pl18x", "arm,primecell"; |
1029 | reg = <0x80126000 0x1000>; | |
90c40257 | 1030 | interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1031 | |
1032 | dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ | |
1033 | <&dma 29 0 0x0>; /* Logical - MemToDev */ | |
1034 | dma-names = "rx", "tx"; | |
1035 | ||
604be898 LJ |
1036 | clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; |
1037 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1038 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1039 | |
7e0ce270 LJ |
1040 | status = "disabled"; |
1041 | }; | |
76ff4e43 | 1042 | |
81bf8c2e | 1043 | sdi1_per2@80118000 { |
7e0ce270 LJ |
1044 | compatible = "arm,pl18x", "arm,primecell"; |
1045 | reg = <0x80118000 0x1000>; | |
90c40257 | 1046 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1047 | |
1048 | dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ | |
1049 | <&dma 32 0 0x0>; /* Logical - MemToDev */ | |
1050 | dma-names = "rx", "tx"; | |
1051 | ||
604be898 LJ |
1052 | clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; |
1053 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1054 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1055 | |
7e0ce270 LJ |
1056 | status = "disabled"; |
1057 | }; | |
76ff4e43 | 1058 | |
81bf8c2e | 1059 | sdi2_per3@80005000 { |
7e0ce270 LJ |
1060 | compatible = "arm,pl18x", "arm,primecell"; |
1061 | reg = <0x80005000 0x1000>; | |
90c40257 | 1062 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1063 | |
1064 | dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ | |
1065 | <&dma 28 0 0x0>; /* Logical - MemToDev */ | |
1066 | dma-names = "rx", "tx"; | |
1067 | ||
604be898 LJ |
1068 | clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; |
1069 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1070 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1071 | |
7e0ce270 LJ |
1072 | status = "disabled"; |
1073 | }; | |
76ff4e43 | 1074 | |
81bf8c2e | 1075 | sdi3_per2@80119000 { |
7e0ce270 LJ |
1076 | compatible = "arm,pl18x", "arm,primecell"; |
1077 | reg = <0x80119000 0x1000>; | |
90c40257 | 1078 | interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; |
604be898 | 1079 | |
14cdf8cb LW |
1080 | dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ |
1081 | <&dma 41 0 0x0>; /* Logical - MemToDev */ | |
1082 | dma-names = "rx", "tx"; | |
1083 | ||
604be898 LJ |
1084 | clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; |
1085 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1086 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1087 | |
7e0ce270 LJ |
1088 | status = "disabled"; |
1089 | }; | |
76ff4e43 | 1090 | |
81bf8c2e | 1091 | sdi4_per2@80114000 { |
7e0ce270 LJ |
1092 | compatible = "arm,pl18x", "arm,primecell"; |
1093 | reg = <0x80114000 0x1000>; | |
90c40257 | 1094 | interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1095 | |
1096 | dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ | |
1097 | <&dma 42 0 0x0>; /* Logical - MemToDev */ | |
1098 | dma-names = "rx", "tx"; | |
1099 | ||
604be898 LJ |
1100 | clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; |
1101 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1102 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1103 | |
7e0ce270 LJ |
1104 | status = "disabled"; |
1105 | }; | |
76ff4e43 | 1106 | |
81bf8c2e | 1107 | sdi5_per3@80008000 { |
7e0ce270 | 1108 | compatible = "arm,pl18x", "arm,primecell"; |
76ff4e43 | 1109 | reg = <0x80008000 0x1000>; |
90c40257 | 1110 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; |
604be898 | 1111 | |
14cdf8cb LW |
1112 | dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ |
1113 | <&dma 43 0 0x0>; /* Logical - MemToDev */ | |
1114 | dma-names = "rx", "tx"; | |
1115 | ||
604be898 LJ |
1116 | clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; |
1117 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1118 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1119 | |
7e0ce270 LJ |
1120 | status = "disabled"; |
1121 | }; | |
bf76e062 | 1122 | |
fe164529 LJ |
1123 | msp0: msp@80123000 { |
1124 | compatible = "stericsson,ux500-msp-i2s"; | |
1125 | reg = <0x80123000 0x1000>; | |
90c40257 | 1126 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1127 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1128 | |
618111ca LJ |
1129 | dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ |
1130 | <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ | |
1131 | dma-names = "rx", "tx"; | |
1132 | ||
133e6027 LJ |
1133 | clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; |
1134 | clock-names = "msp", "apb_pclk"; | |
1135 | ||
fe164529 LJ |
1136 | status = "disabled"; |
1137 | }; | |
1138 | ||
1139 | msp1: msp@80124000 { | |
1140 | compatible = "stericsson,ux500-msp-i2s"; | |
1141 | reg = <0x80124000 0x1000>; | |
90c40257 | 1142 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1143 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1144 | |
14cdf8cb | 1145 | /* This DMA channel only exist on DB8500 v1 */ |
618111ca LJ |
1146 | dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ |
1147 | dma-names = "tx"; | |
1148 | ||
133e6027 LJ |
1149 | clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; |
1150 | clock-names = "msp", "apb_pclk"; | |
1151 | ||
fe164529 LJ |
1152 | status = "disabled"; |
1153 | }; | |
1154 | ||
1155 | // HDMI sound | |
1156 | msp2: msp@80117000 { | |
1157 | compatible = "stericsson,ux500-msp-i2s"; | |
1158 | reg = <0x80117000 0x1000>; | |
90c40257 | 1159 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1160 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1161 | |
618111ca LJ |
1162 | dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ |
1163 | <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev | |
1164 | HighPrio - Fixed */ | |
1165 | dma-names = "rx", "tx"; | |
1166 | ||
133e6027 LJ |
1167 | clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; |
1168 | clock-names = "msp", "apb_pclk"; | |
1169 | ||
fe164529 LJ |
1170 | status = "disabled"; |
1171 | }; | |
1172 | ||
1173 | msp3: msp@80125000 { | |
1174 | compatible = "stericsson,ux500-msp-i2s"; | |
1175 | reg = <0x80125000 0x1000>; | |
90c40257 | 1176 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1177 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1178 | |
14cdf8cb | 1179 | /* This DMA channel only exist on DB8500 v2 */ |
618111ca LJ |
1180 | dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ |
1181 | dma-names = "rx"; | |
1182 | ||
133e6027 LJ |
1183 | clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; |
1184 | clock-names = "msp", "apb_pclk"; | |
1185 | ||
fe164529 LJ |
1186 | status = "disabled"; |
1187 | }; | |
1188 | ||
bf76e062 LJ |
1189 | external-bus@50000000 { |
1190 | compatible = "simple-bus"; | |
1191 | reg = <0x50000000 0x4000000>; | |
1192 | #address-cells = <1>; | |
1193 | #size-cells = <1>; | |
1194 | ranges = <0 0x50000000 0x4000000>; | |
1195 | status = "disabled"; | |
1196 | }; | |
dc1956b5 | 1197 | |
1198 | cpufreq-cooling { | |
1199 | compatible = "stericsson,db8500-cpufreq-cooling"; | |
1200 | status = "disabled"; | |
d460d28b | 1201 | }; |
dc1956b5 | 1202 | |
6e9a88a0 LW |
1203 | mcde@a0350000 { |
1204 | compatible = "stericsson,mcde"; | |
1205 | reg = <0xa0350000 0x1000>, /* MCDE */ | |
1206 | <0xa0351000 0x1000>, /* DSI link 1 */ | |
1207 | <0xa0352000 0x1000>, /* DSI link 2 */ | |
1208 | <0xa0353000 0x1000>; /* DSI link 3 */ | |
1209 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; | |
1210 | clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ | |
1211 | <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ | |
1212 | <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ | |
1213 | <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ | |
1214 | <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ | |
1215 | <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ | |
1216 | <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ | |
1217 | <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ | |
1218 | }; | |
1219 | ||
fe2e9f92 LJ |
1220 | cryp@a03cb000 { |
1221 | compatible = "stericsson,ux500-cryp"; | |
1222 | reg = <0xa03cb000 0x1000>; | |
90c40257 | 1223 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
fe2e9f92 LJ |
1224 | |
1225 | v-ape-supply = <&db8500_vape_reg>; | |
d2f898ce | 1226 | clocks = <&prcc_pclk 6 1>; |
fe2e9f92 | 1227 | }; |
61122cf2 LJ |
1228 | |
1229 | hash@a03c2000 { | |
1230 | compatible = "stericsson,ux500-hash"; | |
1231 | reg = <0xa03c2000 0x1000>; | |
1232 | ||
1233 | v-ape-supply = <&db8500_vape_reg>; | |
024cfe88 | 1234 | clocks = <&prcc_pclk 6 2>; |
61122cf2 | 1235 | }; |
5d0769f0 AB |
1236 | }; |
1237 | }; |