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Commit | Line | Data |
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dd06faff LJ |
1 | /* |
2 | * Copyright 2012 ST-Ericsson AB | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
01dc909f LW |
10 | * |
11 | * Device Tree for the HREF+ prior to the v60 variant. | |
dd06faff LJ |
12 | */ |
13 | ||
2ce05a14 | 14 | #include "ste-dbx5x0.dtsi" |
83200629 | 15 | #include "ste-href-ab8500.dtsi" |
2ce05a14 | 16 | #include "ste-href.dtsi" |
dd06faff LJ |
17 | |
18 | / { | |
6b8db132 LJ |
19 | gpio_keys { |
20 | button@1 { | |
1b1e8e02 | 21 | gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; |
6b8db132 LJ |
22 | }; |
23 | }; | |
24 | ||
b1ba1439 | 25 | soc { |
1d8aca9d LW |
26 | /* Enable UART1 on this board */ |
27 | uart@80121000 { | |
28 | status = "okay"; | |
29 | }; | |
30 | ||
dd06faff LJ |
31 | i2c@80004000 { |
32 | tps61052@33 { | |
33 | compatible = "tps61052"; | |
34 | reg = <0x33>; | |
35 | }; | |
d62407b0 | 36 | |
7e0a51a0 LW |
37 | tc35892@42 { |
38 | compatible = "toshiba,tc35892"; | |
d62407b0 LW |
39 | reg = <0x42>; |
40 | interrupt-parent = <&gpio6>; | |
41 | interrupts = <25 IRQ_TYPE_EDGE_RISING>; | |
a45cb698 LW |
42 | pinctrl-names = "default"; |
43 | pinctrl-0 = <&tc35892_hrefprev60_mode>; | |
d62407b0 LW |
44 | |
45 | interrupt-controller; | |
7e0a51a0 | 46 | #interrupt-cells = <1>; |
d62407b0 LW |
47 | |
48 | tc3589x_gpio: tc3589x_gpio { | |
49 | compatible = "tc3589x-gpio"; | |
7e0a51a0 | 50 | interrupts = <0>; |
d62407b0 LW |
51 | |
52 | interrupt-controller; | |
53 | #interrupt-cells = <2>; | |
54 | gpio-controller; | |
55 | #gpio-cells = <2>; | |
56 | }; | |
57 | }; | |
dd06faff | 58 | }; |
cbebba7d | 59 | |
38656820 LW |
60 | ssp@80002000 { |
61 | /* | |
62 | * On the first generation boards, this SSP/SPI port was connected | |
63 | * to the AB8500. | |
64 | */ | |
65 | pinctrl-names = "default"; | |
66 | pinctrl-0 = <&ssp0_hrefprev60_mode>; | |
67 | }; | |
68 | ||
a987a3ac UH |
69 | // External Micro SD slot |
70 | sdi0_per1@80126000 { | |
1b1e8e02 | 71 | cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; |
a987a3ac UH |
72 | }; |
73 | ||
8ad49c65 | 74 | vmmci: regulator-gpio { |
1b1e8e02 LW |
75 | gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; |
76 | enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; | |
adef953b | 77 | enable-active-high; |
8ad49c65 | 78 | }; |
1e662353 LW |
79 | |
80 | pinctrl { | |
3ae2750a LW |
81 | /* Set this up using hogs */ |
82 | pinctrl-names = "default"; | |
83 | pinctrl-0 = <&ipgpio_hrefprev60_mode>; | |
84 | ||
38656820 LW |
85 | ssp0 { |
86 | ssp0_hrefprev60_mode: ssp0_hrefprev60_default { | |
87 | hrefprev60_mux { | |
68d41f23 LW |
88 | function = "ssp0"; |
89 | groups = "ssp0_a_1"; | |
38656820 LW |
90 | }; |
91 | hrefprev60_cfg1 { | |
1637d480 | 92 | pins = "GPIO145_C13"; /* RXD */ |
38656820 LW |
93 | ste,config = <&in_pd>; |
94 | }; | |
95 | ||
96 | }; | |
97 | }; | |
1e662353 LW |
98 | sdi0 { |
99 | /* This additional pin needed on early MOP500 and HREFs previous to v60 */ | |
100 | sdi0_default_mode: sdi0_default { | |
101 | hrefprev60_mux { | |
68d41f23 LW |
102 | function = "mc0"; |
103 | groups = "mc0dat31dir_a_1"; | |
1e662353 LW |
104 | }; |
105 | hrefprev60_cfg1 { | |
1637d480 | 106 | pins = "GPIO21_AB3"; /* DAT31DIR */ |
1e662353 LW |
107 | ste,config = <&out_hi>; |
108 | }; | |
109 | ||
110 | }; | |
111 | }; | |
a45cb698 LW |
112 | tc35892 { |
113 | tc35892_hrefprev60_mode: tc35892_hrefprev60 { | |
114 | hrefprev60_cfg { | |
1637d480 | 115 | pins = "GPIO217_AH12"; |
a45cb698 LW |
116 | ste,config = <&gpio_in_pu>; |
117 | }; | |
118 | }; | |
119 | }; | |
3ae2750a LW |
120 | ipgpio { |
121 | ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { | |
122 | hrefprev60_mux { | |
68d41f23 LW |
123 | function = "ipgpio"; |
124 | groups = "ipgpio0_c_1", "ipgpio1_c_1"; | |
3ae2750a LW |
125 | }; |
126 | hrefprev60_cfg1 { | |
1637d480 | 127 | pins = "GPIO6_AF6", "GPIO7_AG5"; |
3ae2750a LW |
128 | ste,config = <&in_pu>; |
129 | }; | |
130 | }; | |
131 | }; | |
1e662353 | 132 | }; |
dd06faff LJ |
133 | }; |
134 | }; |