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Commit | Line | Data |
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dd06faff LJ |
1 | /* |
2 | * Copyright 2012 ST-Ericsson AB | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
01dc909f LW |
10 | * |
11 | * Device Tree for the HREF+ prior to the v60 variant. | |
dd06faff LJ |
12 | */ |
13 | ||
2ce05a14 | 14 | #include "ste-dbx5x0.dtsi" |
83200629 | 15 | #include "ste-href-ab8500.dtsi" |
2ce05a14 | 16 | #include "ste-href.dtsi" |
dd06faff LJ |
17 | |
18 | / { | |
6b8db132 LJ |
19 | gpio_keys { |
20 | button@1 { | |
21 | gpios = <&tc3589x_gpio 7 0x4>; | |
22 | }; | |
23 | }; | |
24 | ||
b1ba1439 | 25 | soc { |
dd06faff LJ |
26 | i2c@80004000 { |
27 | tps61052@33 { | |
28 | compatible = "tps61052"; | |
29 | reg = <0x33>; | |
30 | }; | |
d62407b0 | 31 | |
7e0a51a0 LW |
32 | tc35892@42 { |
33 | compatible = "toshiba,tc35892"; | |
d62407b0 LW |
34 | reg = <0x42>; |
35 | interrupt-parent = <&gpio6>; | |
36 | interrupts = <25 IRQ_TYPE_EDGE_RISING>; | |
a45cb698 LW |
37 | pinctrl-names = "default"; |
38 | pinctrl-0 = <&tc35892_hrefprev60_mode>; | |
d62407b0 LW |
39 | |
40 | interrupt-controller; | |
7e0a51a0 | 41 | #interrupt-cells = <1>; |
d62407b0 LW |
42 | |
43 | tc3589x_gpio: tc3589x_gpio { | |
44 | compatible = "tc3589x-gpio"; | |
7e0a51a0 | 45 | interrupts = <0>; |
d62407b0 LW |
46 | |
47 | interrupt-controller; | |
48 | #interrupt-cells = <2>; | |
49 | gpio-controller; | |
50 | #gpio-cells = <2>; | |
51 | }; | |
52 | }; | |
dd06faff | 53 | }; |
cbebba7d | 54 | |
38656820 LW |
55 | ssp@80002000 { |
56 | /* | |
57 | * On the first generation boards, this SSP/SPI port was connected | |
58 | * to the AB8500. | |
59 | */ | |
60 | pinctrl-names = "default"; | |
61 | pinctrl-0 = <&ssp0_hrefprev60_mode>; | |
62 | }; | |
63 | ||
a987a3ac UH |
64 | // External Micro SD slot |
65 | sdi0_per1@80126000 { | |
66 | cd-gpios = <&tc3589x_gpio 3 0x4>; | |
67 | }; | |
68 | ||
8ad49c65 LJ |
69 | vmmci: regulator-gpio { |
70 | gpios = <&tc3589x_gpio 18 0x4>; | |
75766003 | 71 | enable-gpio = <&tc3589x_gpio 17 0x4>; |
8ad49c65 | 72 | }; |
1e662353 LW |
73 | |
74 | pinctrl { | |
3ae2750a LW |
75 | /* Set this up using hogs */ |
76 | pinctrl-names = "default"; | |
77 | pinctrl-0 = <&ipgpio_hrefprev60_mode>; | |
78 | ||
38656820 LW |
79 | ssp0 { |
80 | ssp0_hrefprev60_mode: ssp0_hrefprev60_default { | |
81 | hrefprev60_mux { | |
82 | ste,function = "ssp0"; | |
83 | ste,pins = "ssp0_a_1"; | |
84 | }; | |
85 | hrefprev60_cfg1 { | |
86 | ste,pins = "GPIO145_C13"; /* RXD */ | |
87 | ste,config = <&in_pd>; | |
88 | }; | |
89 | ||
90 | }; | |
91 | }; | |
1e662353 LW |
92 | sdi0 { |
93 | /* This additional pin needed on early MOP500 and HREFs previous to v60 */ | |
94 | sdi0_default_mode: sdi0_default { | |
95 | hrefprev60_mux { | |
96 | ste,function = "mc0"; | |
97 | ste,pins = "mc0dat31dir_a_1"; | |
98 | }; | |
99 | hrefprev60_cfg1 { | |
100 | ste,pins = "GPIO21_AB3"; /* DAT31DIR */ | |
101 | ste,config = <&out_hi>; | |
102 | }; | |
103 | ||
104 | }; | |
105 | }; | |
a45cb698 LW |
106 | tc35892 { |
107 | tc35892_hrefprev60_mode: tc35892_hrefprev60 { | |
108 | hrefprev60_cfg { | |
109 | ste,pins = "GPIO217_AH12"; | |
110 | ste,config = <&gpio_in_pu>; | |
111 | }; | |
112 | }; | |
113 | }; | |
3ae2750a LW |
114 | ipgpio { |
115 | ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { | |
116 | hrefprev60_mux { | |
117 | ste,function = "ipgpio"; | |
118 | ste,pins = "ipgpio0_c_1", "ipgpio1_c_1"; | |
119 | }; | |
120 | hrefprev60_cfg1 { | |
121 | ste,pins = "GPIO6_AF6", "GPIO7_AG5"; | |
122 | ste,config = <&in_pu>; | |
123 | }; | |
124 | }; | |
125 | }; | |
1e662353 | 126 | }; |
dd06faff LJ |
127 | }; |
128 | }; |