[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / stih407-clock.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics R&D Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <dt-bindings/clock/stih407-clks.h>
/ {
	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * Fixed 30MHz oscillator inputs to SoC
		 */
		clk_sysin: clk-sysin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <30000000>;
		};

		/*
		 * ARM Peripheral clock for timers
		 */
		arm_periph_clk: clk-m-a9-periphs {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";

			clocks = <&clk_m_a9>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		/*
		 * A9 PLL.
		 */
		clockgen-a9@92b0000 {
			compatible = "st,clkgen-c32";
			reg = <0x92b0000 0xffff>;

			clockgen_a9_pll: clockgen-a9-pll {
				#clock-cells = <1>;
				compatible = "st,stih407-clkgen-plla9";

				clocks = <&clk_sysin>;

				clock-output-names = "clockgen-a9-pll-odf";
			};
		};

		/*
		 * ARM CPU related clocks.
		 */
		clk_m_a9: clk-m-a9@92b0000 {
			#clock-cells = <0>;
			compatible = "st,stih407-clkgen-a9-mux";
			reg = <0x92b0000 0x10000>;

			clocks = <&clockgen_a9_pll 0>,
				 <&clockgen_a9_pll 0>,
				 <&clk_s_c0_flexgen 13>,
				 <&clk_m_a9_ext2f_div2>;
		};

		/*
		 * ARM Peripheral clock for timers
		 */
		clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";

			clocks = <&clk_s_c0_flexgen 13>;

			clock-output-names = "clk-m-a9-ext2f-div2";

			clock-div = <2>;
			clock-mult = <1>;
		};

		/*
		 * Bootloader initialized system infrastructure clock for
		 * serial devices.
		 */
		clk_ext2f_a9: clockgen-c0@13 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
			clock-output-names = "clk-s-icn-reg-0";
		};

		clockgen-a@090ff000 {
			compatible = "st,clkgen-c32";
			reg = <0x90ff000 0x1000>;

			clk_s_a0_pll: clk-s-a0-pll {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll0";

				clocks = <&clk_sysin>;

				clock-output-names = "clk-s-a0-pll-ofd-0";
				clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
			};

			clk_s_a0_flexgen: clk-s-a0-flexgen {
				compatible = "st,flexgen";

				#clock-cells = <1>;

				clocks = <&clk_s_a0_pll 0>,
					 <&clk_sysin>;

				clock-output-names = "clk-ic-lmi0";
				clock-critical = <CLK_IC_LMI0>;
			};
		};

		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
			#clock-cells = <1>;
			compatible = "st,quadfs-pll";
			reg = <0x9103000 0x1000>;

			clocks = <&clk_sysin>;

			clock-output-names = "clk-s-c0-fs0-ch0",
					     "clk-s-c0-fs0-ch1",
					     "clk-s-c0-fs0-ch2",
					     "clk-s-c0-fs0-ch3";
			clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
		};

		clk_s_c0: clockgen-c@09103000 {
			compatible = "st,clkgen-c32";
			reg = <0x9103000 0x1000>;

			clk_s_c0_pll0: clk-s-c0-pll0 {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll0";

				clocks = <&clk_sysin>;

				clock-output-names = "clk-s-c0-pll0-odf-0";
				clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
			};

			clk_s_c0_pll1: clk-s-c0-pll1 {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll1";

				clocks = <&clk_sysin>;

				clock-output-names = "clk-s-c0-pll1-odf-0";
			};

			clk_s_c0_flexgen: clk-s-c0-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen";

				clocks = <&clk_s_c0_pll0 0>,
					 <&clk_s_c0_pll1 0>,
					 <&clk_s_c0_quadfs 0>,
					 <&clk_s_c0_quadfs 1>,
					 <&clk_s_c0_quadfs 2>,
					 <&clk_s_c0_quadfs 3>,
					 <&clk_sysin>;

				clock-output-names = "clk-icn-gpu",
						     "clk-fdma",
						     "clk-nand",
						     "clk-hva",
						     "clk-proc-stfe",
						     "clk-proc-tp",
						     "clk-rx-icn-dmu",
						     "clk-rx-icn-hva",
						     "clk-icn-cpu",
						     "clk-tx-icn-dmu",
						     "clk-mmc-0",
						     "clk-mmc-1",
						     "clk-jpegdec",
						     "clk-ext2fa9",
						     "clk-ic-bdisp-0",
						     "clk-ic-bdisp-1",
						     "clk-pp-dmu",
						     "clk-vid-dmu",
						     "clk-dss-lpc",
						     "clk-st231-aud-0",
						     "clk-st231-gp-1",
						     "clk-st231-dmu",
						     "clk-icn-lmi",
						     "clk-tx-icn-disp-1",
						     "clk-icn-sbc",
						     "clk-stfe-frc2",
						     "clk-eth-phy",
						     "clk-eth-ref-phyclk",
						     "clk-flash-promip",
						     "clk-main-disp",
						     "clk-aux-disp",
						     "clk-compo-dvp";
				clock-critical = <CLK_PROC_STFE>,
						 <CLK_ICN_CPU>,
						 <CLK_TX_ICN_DMU>,
						 <CLK_EXT2F_A9>,
						 <CLK_ICN_LMI>,
						 <CLK_ICN_SBC>;
			};
		};

		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
			#clock-cells = <1>;
			compatible = "st,quadfs";
			reg = <0x9104000 0x1000>;

			clocks = <&clk_sysin>;

			clock-output-names = "clk-s-d0-fs0-ch0",
					     "clk-s-d0-fs0-ch1",
					     "clk-s-d0-fs0-ch2",
					     "clk-s-d0-fs0-ch3";
		};

		clockgen-d0@09104000 {
			compatible = "st,clkgen-c32";
			reg = <0x9104000 0x1000>;

			clk_s_d0_flexgen: clk-s-d0-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen-audio", "st,flexgen";

				clocks = <&clk_s_d0_quadfs 0>,
					 <&clk_s_d0_quadfs 1>,
					 <&clk_s_d0_quadfs 2>,
					 <&clk_s_d0_quadfs 3>,
					 <&clk_sysin>;

				clock-output-names = "clk-pcm-0",
						     "clk-pcm-1",
						     "clk-pcm-2",
						     "clk-spdiff";
			};
		};

		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
			#clock-cells = <1>;
			compatible = "st,quadfs";
			reg = <0x9106000 0x1000>;

			clocks = <&clk_sysin>;

			clock-output-names = "clk-s-d2-fs0-ch0",
					     "clk-s-d2-fs0-ch1",
					     "clk-s-d2-fs0-ch2",
					     "clk-s-d2-fs0-ch3";
		};

		clk_tmdsout_hdmi: clk-tmdsout-hdmi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clockgen-d2@x9106000 {
			compatible = "st,clkgen-c32";
			reg = <0x9106000 0x1000>;

			clk_s_d2_flexgen: clk-s-d2-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen-video", "st,flexgen";

				clocks = <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>,
					 <&clk_s_d2_quadfs 2>,
					 <&clk_s_d2_quadfs 3>,
					 <&clk_sysin>,
					 <&clk_sysin>,
					 <&clk_tmdsout_hdmi>;

				clock-output-names = "clk-pix-main-disp",
						     "clk-pix-pip",
						     "clk-pix-gdp1",
						     "clk-pix-gdp2",
						     "clk-pix-gdp3",
						     "clk-pix-gdp4",
						     "clk-pix-aux-disp",
						     "clk-denc",
						     "clk-pix-hddac",
						     "clk-hddac",
						     "clk-sddac",
						     "clk-pix-dvo",
						     "clk-dvo",
						     "clk-pix-hdmi",
						     "clk-tmds-hdmi",
						     "clk-ref-hdmiphy";
						     };
		};

		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
			#clock-cells = <1>;
			compatible = "st,quadfs";
			reg = <0x9107000 0x1000>;

			clocks = <&clk_sysin>;

			clock-output-names = "clk-s-d3-fs0-ch0",
					     "clk-s-d3-fs0-ch1",
					     "clk-s-d3-fs0-ch2",
					     "clk-s-d3-fs0-ch3";
		};

		clockgen-d3@9107000 {
			compatible = "st,clkgen-c32";
			reg = <0x9107000 0x1000>;

			clk_s_d3_flexgen: clk-s-d3-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen";

				clocks = <&clk_s_d3_quadfs 0>,
					 <&clk_s_d3_quadfs 1>,
					 <&clk_s_d3_quadfs 2>,
					 <&clk_s_d3_quadfs 3>,
					 <&clk_sysin>;

				clock-output-names = "clk-stfe-frc1",
						     "clk-tsout-0",
						     "clk-tsout-1",
						     "clk-mchi",
						     "clk-vsens-compo",
						     "clk-frc1-remote",
						     "clk-lpc-0",
						     "clk-lpc-1";
			};
		};
	};
};
Commit	Line	Data
f563a571 MC	1	/*
	2	* Copyright (C) 2014 STMicroelectronics R&D Limited
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
1befe7e4	8	#include <dt-bindings/clock/stih407-clks.h>
f563a571 MC	9	/ {
f563a571 MC	10	clocks {
58a8d9be GF	11	#address-cells = <1>;
	12	#size-cells = <1>;
	13	ranges;
	14
f563a571 MC	15	/*
	16	* Fixed 30MHz oscillator inputs to SoC
	17	*/
	18	clk_sysin: clk-sysin {
	19	#clock-cells = <0>;
	20	compatible = "fixed-clock";
	21	clock-frequency = <30000000>;
	22	};
	23
	24	/*
	25	* ARM Peripheral clock for timers
	26	*/
89e5c085	27	arm_periph_clk: clk-m-a9-periphs {
f563a571	28	#clock-cells = <0>;
89e5c085 GF	29	compatible = "fixed-factor-clock";
	30
	31	clocks = <&clk_m_a9>;
	32	clock-div = <2>;
	33	clock-mult = <1>;
	34	};
	35
	36	/*
	37	* A9 PLL.
	38	*/
	39	clockgen-a9@92b0000 {
	40	compatible = "st,clkgen-c32";
	41	reg = <0x92b0000 0xffff>;
	42
	43	clockgen_a9_pll: clockgen-a9-pll {
	44	#clock-cells = <1>;
665c8ec1	45	compatible = "st,stih407-clkgen-plla9";
89e5c085 GF	46
	47	clocks = <&clk_sysin>;
	48
	49	clock-output-names = "clockgen-a9-pll-odf";
	50	};
	51	};
	52
	53	/*
	54	* ARM CPU related clocks.
	55	*/
	56	clk_m_a9: clk-m-a9@92b0000 {
	57	#clock-cells = <0>;
665c8ec1	58	compatible = "st,stih407-clkgen-a9-mux";
89e5c085 GF	59	reg = <0x92b0000 0x10000>;
	60
	61	clocks = <&clockgen_a9_pll 0>,
	62	<&clockgen_a9_pll 0>,
	63	<&clk_s_c0_flexgen 13>,
	64	<&clk_m_a9_ext2f_div2>;
	65	};
	66
	67	/*
	68	* ARM Peripheral clock for timers
	69	*/
	70	clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
	71	#clock-cells = <0>;
	72	compatible = "fixed-factor-clock";
	73
	74	clocks = <&clk_s_c0_flexgen 13>;
	75
	76	clock-output-names = "clk-m-a9-ext2f-div2";
	77
	78	clock-div = <2>;
	79	clock-mult = <1>;
f563a571 MC	80	};
	81
	82	/*
	83	* Bootloader initialized system infrastructure clock for
	84	* serial devices.
	85	*/
	86	clk_ext2f_a9: clockgen-c0@13 {
	87	#clock-cells = <0>;
	88	compatible = "fixed-clock";
	89	clock-frequency = <200000000>;
	90	clock-output-names = "clk-s-icn-reg-0";
	91	};
58a8d9be GF	92
	93	clockgen-a@090ff000 {
	94	compatible = "st,clkgen-c32";
	95	reg = <0x90ff000 0x1000>;
	96
	97	clk_s_a0_pll: clk-s-a0-pll {
	98	#clock-cells = <1>;
665c8ec1	99	compatible = "st,clkgen-pll0";
58a8d9be GF	100
	101	clocks = <&clk_sysin>;
	102
	103	clock-output-names = "clk-s-a0-pll-ofd-0";
e614a121	104	clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
58a8d9be GF	105	};
	106
	107	clk_s_a0_flexgen: clk-s-a0-flexgen {
	108	compatible = "st,flexgen";
	109
	110	#clock-cells = <1>;
	111
	112	clocks = <&clk_s_a0_pll 0>,
	113	<&clk_sysin>;
	114
	115	clock-output-names = "clk-ic-lmi0";
e614a121	116	clock-critical = <CLK_IC_LMI0>;
58a8d9be GF	117	};
58a8d9be GF	118	};
1befe7e4 GF	119
	120	clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
	121	#clock-cells = <1>;
665c8ec1	122	compatible = "st,quadfs-pll";
1befe7e4 GF	123	reg = <0x9103000 0x1000>;
	124
	125	clocks = <&clk_sysin>;
	126
	127	clock-output-names = "clk-s-c0-fs0-ch0",
	128	"clk-s-c0-fs0-ch1",
	129	"clk-s-c0-fs0-ch2",
	130	"clk-s-c0-fs0-ch3";
e614a121	131	clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
1befe7e4 GF	132	};
	133
	134	clk_s_c0: clockgen-c@09103000 {
	135	compatible = "st,clkgen-c32";
	136	reg = <0x9103000 0x1000>;
	137
	138	clk_s_c0_pll0: clk-s-c0-pll0 {
	139	#clock-cells = <1>;
665c8ec1	140	compatible = "st,clkgen-pll0";
1befe7e4 GF	141
	142	clocks = <&clk_sysin>;
	143
	144	clock-output-names = "clk-s-c0-pll0-odf-0";
e614a121	145	clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
1befe7e4 GF	146	};
	147
	148	clk_s_c0_pll1: clk-s-c0-pll1 {
	149	#clock-cells = <1>;
665c8ec1	150	compatible = "st,clkgen-pll1";
1befe7e4 GF	151
	152	clocks = <&clk_sysin>;
	153
	154	clock-output-names = "clk-s-c0-pll1-odf-0";
	155	};
	156
	157	clk_s_c0_flexgen: clk-s-c0-flexgen {
	158	#clock-cells = <1>;
	159	compatible = "st,flexgen";
	160
	161	clocks = <&clk_s_c0_pll0 0>,
	162	<&clk_s_c0_pll1 0>,
	163	<&clk_s_c0_quadfs 0>,
	164	<&clk_s_c0_quadfs 1>,
	165	<&clk_s_c0_quadfs 2>,
	166	<&clk_s_c0_quadfs 3>,
	167	<&clk_sysin>;
	168
	169	clock-output-names = "clk-icn-gpu",
	170	"clk-fdma",
	171	"clk-nand",
	172	"clk-hva",
	173	"clk-proc-stfe",
	174	"clk-proc-tp",
	175	"clk-rx-icn-dmu",
	176	"clk-rx-icn-hva",
	177	"clk-icn-cpu",
	178	"clk-tx-icn-dmu",
	179	"clk-mmc-0",
	180	"clk-mmc-1",
	181	"clk-jpegdec",
	182	"clk-ext2fa9",
	183	"clk-ic-bdisp-0",
	184	"clk-ic-bdisp-1",
	185	"clk-pp-dmu",
	186	"clk-vid-dmu",
	187	"clk-dss-lpc",
	188	"clk-st231-aud-0",
	189	"clk-st231-gp-1",
	190	"clk-st231-dmu",
	191	"clk-icn-lmi",
	192	"clk-tx-icn-disp-1",
	193	"clk-icn-sbc",
	194	"clk-stfe-frc2",
	195	"clk-eth-phy",
	196	"clk-eth-ref-phyclk",
	197	"clk-flash-promip",
	198	"clk-main-disp",
	199	"clk-aux-disp",
	200	"clk-compo-dvp";
e614a121 PG	201	clock-critical = <CLK_PROC_STFE>,
	202	<CLK_ICN_CPU>,
	203	<CLK_TX_ICN_DMU>,
	204	<CLK_EXT2F_A9>,
	205	<CLK_ICN_LMI>,
	206	<CLK_ICN_SBC>;
1befe7e4 GF	207	};
1befe7e4 GF	208	};
6e67a510 GF	209
	210	clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
	211	#clock-cells = <1>;
665c8ec1	212	compatible = "st,quadfs";
6e67a510 GF	213	reg = <0x9104000 0x1000>;
	214
	215	clocks = <&clk_sysin>;
	216
	217	clock-output-names = "clk-s-d0-fs0-ch0",
	218	"clk-s-d0-fs0-ch1",
	219	"clk-s-d0-fs0-ch2",
	220	"clk-s-d0-fs0-ch3";
	221	};
	222
	223	clockgen-d0@09104000 {
	224	compatible = "st,clkgen-c32";
	225	reg = <0x9104000 0x1000>;
	226
	227	clk_s_d0_flexgen: clk-s-d0-flexgen {
	228	#clock-cells = <1>;
ee7ff1b4	229	compatible = "st,flexgen-audio", "st,flexgen";
6e67a510 GF	230
	231	clocks = <&clk_s_d0_quadfs 0>,
	232	<&clk_s_d0_quadfs 1>,
	233	<&clk_s_d0_quadfs 2>,
	234	<&clk_s_d0_quadfs 3>,
	235	<&clk_sysin>;
	236
	237	clock-output-names = "clk-pcm-0",
	238	"clk-pcm-1",
	239	"clk-pcm-2",
	240	"clk-spdiff";
	241	};
	242	};
	243
	244	clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
	245	#clock-cells = <1>;
665c8ec1	246	compatible = "st,quadfs";
6e67a510 GF	247	reg = <0x9106000 0x1000>;
	248
	249	clocks = <&clk_sysin>;
	250
	251	clock-output-names = "clk-s-d2-fs0-ch0",
	252	"clk-s-d2-fs0-ch1",
	253	"clk-s-d2-fs0-ch2",
	254	"clk-s-d2-fs0-ch3";
	255	};
	256
	257	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
	258	#clock-cells = <0>;
	259	compatible = "fixed-clock";
	260	clock-frequency = <0>;
	261	};
	262
	263	clockgen-d2@x9106000 {
	264	compatible = "st,clkgen-c32";
	265	reg = <0x9106000 0x1000>;
	266
	267	clk_s_d2_flexgen: clk-s-d2-flexgen {
	268	#clock-cells = <1>;
295971d0	269	compatible = "st,flexgen-video", "st,flexgen";
6e67a510 GF	270
	271	clocks = <&clk_s_d2_quadfs 0>,
	272	<&clk_s_d2_quadfs 1>,
	273	<&clk_s_d2_quadfs 2>,
	274	<&clk_s_d2_quadfs 3>,
	275	<&clk_sysin>,
	276	<&clk_sysin>,
	277	<&clk_tmdsout_hdmi>;
	278
	279	clock-output-names = "clk-pix-main-disp",
	280	"clk-pix-pip",
	281	"clk-pix-gdp1",
	282	"clk-pix-gdp2",
	283	"clk-pix-gdp3",
	284	"clk-pix-gdp4",
	285	"clk-pix-aux-disp",
	286	"clk-denc",
	287	"clk-pix-hddac",
	288	"clk-hddac",
	289	"clk-sddac",
	290	"clk-pix-dvo",
	291	"clk-dvo",
	292	"clk-pix-hdmi",
43ca480c	293	"clk-tmds-hdmi",
6e67a510 GF	294	"clk-ref-hdmiphy";
	295	};
	296	};
	297
	298	clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
	299	#clock-cells = <1>;
665c8ec1	300	compatible = "st,quadfs";
6e67a510 GF	301	reg = <0x9107000 0x1000>;
	302
	303	clocks = <&clk_sysin>;
	304
	305	clock-output-names = "clk-s-d3-fs0-ch0",
	306	"clk-s-d3-fs0-ch1",
	307	"clk-s-d3-fs0-ch2",
	308	"clk-s-d3-fs0-ch3";
	309	};
	310
	311	clockgen-d3@9107000 {
	312	compatible = "st,clkgen-c32";
	313	reg = <0x9107000 0x1000>;
	314
	315	clk_s_d3_flexgen: clk-s-d3-flexgen {
	316	#clock-cells = <1>;
	317	compatible = "st,flexgen";
	318
	319	clocks = <&clk_s_d3_quadfs 0>,
	320	<&clk_s_d3_quadfs 1>,
	321	<&clk_s_d3_quadfs 2>,
	322	<&clk_s_d3_quadfs 3>,
	323	<&clk_sysin>;
	324
	325	clock-output-names = "clk-stfe-frc1",
	326	"clk-tsout-0",
	327	"clk-tsout-1",
	328	"clk-mchi",
	329	"clk-vsens-compo",
	330	"clk-frc1-remote",
	331	"clk-lpc-0",
	332	"clk-lpc-1";
	333	};
	334	};
f563a571 MC	335	};
f563a571 MC	336	};