[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / stih407-family.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/reset-controller/stih407-resets.h>
/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	intc: interrupt-controller@08761000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x08761000 0x1000>, <0x08760100 0x100>;
	};

	scu@08760000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x08760000 0x1000>;
	};

	timer@08760200 {
		interrupt-parent = <&intc>;
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x08760200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&arm_periph_clk>;
	};

	l2: cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x08762000 0x1000>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		cache-unified;
		cache-level = <2>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;
		compatible = "simple-bus";

		powerdown: powerdown-controller {
			compatible = "st,stih407-powerdown";
			#reset-cells = <1>;
		};

		softreset: softreset-controller {
			compatible = "st,stih407-softreset";
			#reset-cells = <1>;
		};

		picophyreset: picophyreset-controller {
			compatible = "st,stih407-picophyreset";
			#reset-cells = <1>;
		};

		syscfg_sbc: sbc-syscfg@9620000 {
			compatible = "st,stih407-sbc-syscfg", "syscon";
			reg = <0x9620000 0x1000>;
		};

		syscfg_front: front-syscfg@9280000 {
			compatible = "st,stih407-front-syscfg", "syscon";
			reg = <0x9280000 0x1000>;
		};

		syscfg_rear: rear-syscfg@9290000 {
			compatible = "st,stih407-rear-syscfg", "syscon";
			reg = <0x9290000 0x1000>;
		};

		syscfg_flash: flash-syscfg@92a0000 {
			compatible = "st,stih407-flash-syscfg", "syscon";
			reg = <0x92a0000 0x1000>;
		};

		syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
			compatible = "st,stih407-sbc-reg-syscfg", "syscon";
			reg = <0x9600000 0x1000>;
		};

		syscfg_core: core-syscfg@92b0000 {
			compatible = "st,stih407-core-syscfg", "syscon";
			reg = <0x92b0000 0x1000>;
		};

		syscfg_lpm: lpm-syscfg@94b5100 {
			compatible = "st,stih407-lpm-syscfg", "syscon";
			reg = <0x94b5100 0x1000>;
		};

		serial@9830000 {
			compatible = "st,asc";
			reg = <0x9830000 0x2c>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial0>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		serial@9831000 {
			compatible = "st,asc";
			reg = <0x9831000 0x2c>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial1>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		serial@9832000 {
			compatible = "st,asc";
			reg = <0x9832000 0x2c>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial2>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		/* SBC_ASC0 - UART10 */
		sbc_serial0: serial@9530000 {
			compatible = "st,asc";
			reg = <0x9530000 0x2c>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sbc_serial0>;
			clocks = <&clk_sysin>;

			status = "disabled";
		};

		serial@9531000 {
			compatible = "st,asc";
			reg = <0x9531000 0x2c>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sbc_serial1>;
			clocks = <&clk_sysin>;

			status = "disabled";
		};

		i2c@9840000 {
			compatible = "st,comms-ssc4-i2c";
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x9840000 0x110>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0_default>;

			status = "disabled";
		};

		i2c@9841000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9841000 0x110>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1_default>;

			status = "disabled";
		};

		i2c@9842000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9842000 0x110>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2_default>;

			status = "disabled";
		};

		i2c@9843000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9843000 0x110>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3_default>;

			status = "disabled";
		};

		i2c@9844000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9844000 0x110>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4_default>;

			status = "disabled";
		};

		i2c@9845000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9845000 0x110>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c5_default>;

			status = "disabled";
		};


		/* SSCs on SBC */
		i2c@9540000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9540000 0x110>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c10_default>;

			status = "disabled";
		};

		i2c@9541000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9541000 0x110>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c11_default>;

			status = "disabled";
		};

		usb2_picophy0: phy1 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0x100 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY0_RESET>;
			reset-names = "global", "port";
		};

		miphy28lp_phy: miphy28lp@9b22000 {
			compatible = "st,miphy28lp-phy";
			st,syscfg = <&syscfg_core>;
			#address-cells	= <1>;
			#size-cells	= <1>;
			ranges;

			phy_port0: port@9b22000 {
				reg = <0x9b22000 0xff>,
				      <0x9b09000 0xff>,
				      <0x9b04000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x114 0x818 0xe0 0xec>;
				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
			};

			phy_port1: port@9b2a000 {
				reg = <0x9b2a000 0xff>,
				      <0x9b19000 0xff>,
				      <0x9b14000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x118 0x81c 0xe4 0xf0>;

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
			};

			phy_port2: port@8f95000 {
				reg = <0x8f95000 0xff>,
				      <0x8f90000 0xff>;
				reg-names = "pipew",
					    "usb3-up";

				st,syscfg = <0x11c 0x820>;

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
			};
		};

		spi@9840000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9840000 0x110>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-0 = <&pinctrl_spi0_default>;
			pinctrl-names = "default";
			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};

		spi@9841000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9841000 0x110>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9842000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9842000 0x110>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9843000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9843000 0x110>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9844000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9844000 0x110>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		/* SBC SSC */
		spi@9540000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9540000 0x110>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9541000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9541000 0x110>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9542000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9542000 0x110>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";

			status = "disabled";
		};
	};
};
Commit	Line	Data
f563a571 MC	1	/*
	2	* Copyright (C) 2014 STMicroelectronics Limited.
	3	* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
f563a571	9	#include "stih407-pinctrl.dtsi"
b864a0b9	10	#include <dt-bindings/reset-controller/stih407-resets.h>
f563a571 MC	11	/ {
	12	#address-cells = <1>;
	13	#size-cells = <1>;
	14
	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
	18	cpu@0 {
	19	device_type = "cpu";
	20	compatible = "arm,cortex-a9";
	21	reg = <0>;
	22	};
	23	cpu@1 {
	24	device_type = "cpu";
	25	compatible = "arm,cortex-a9";
	26	reg = <1>;
	27	};
	28	};
	29
	30	intc: interrupt-controller@08761000 {
	31	compatible = "arm,cortex-a9-gic";
	32	#interrupt-cells = <3>;
	33	interrupt-controller;
	34	reg = <0x08761000 0x1000>, <0x08760100 0x100>;
	35	};
	36
	37	scu@08760000 {
	38	compatible = "arm,cortex-a9-scu";
	39	reg = <0x08760000 0x1000>;
	40	};
	41
	42	timer@08760200 {
	43	interrupt-parent = <&intc>;
	44	compatible = "arm,cortex-a9-global-timer";
	45	reg = <0x08760200 0x100>;
	46	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	47	clocks = <&arm_periph_clk>;
	48	};
	49
	50	l2: cache-controller {
	51	compatible = "arm,pl310-cache";
	52	reg = <0x08762000 0x1000>;
	53	arm,data-latency = <3 3 3>;
	54	arm,tag-latency = <2 2 2>;
	55	cache-unified;
	56	cache-level = <2>;
	57	};
	58
	59	soc {
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62	interrupt-parent = <&intc>;
	63	ranges;
	64	compatible = "simple-bus";
	65
b864a0b9 PG	66	powerdown: powerdown-controller {
	67	compatible = "st,stih407-powerdown";
	68	#reset-cells = <1>;
	69	};
	70
	71	softreset: softreset-controller {
	72	compatible = "st,stih407-softreset";
	73	#reset-cells = <1>;
	74	};
	75
	76	picophyreset: picophyreset-controller {
	77	compatible = "st,stih407-picophyreset";
	78	#reset-cells = <1>;
	79	};
	80
f563a571 MC	81	syscfg_sbc: sbc-syscfg@9620000 {
	82	compatible = "st,stih407-sbc-syscfg", "syscon";
	83	reg = <0x9620000 0x1000>;
	84	};
	85
	86	syscfg_front: front-syscfg@9280000 {
	87	compatible = "st,stih407-front-syscfg", "syscon";
	88	reg = <0x9280000 0x1000>;
	89	};
	90
	91	syscfg_rear: rear-syscfg@9290000 {
	92	compatible = "st,stih407-rear-syscfg", "syscon";
	93	reg = <0x9290000 0x1000>;
	94	};
	95
	96	syscfg_flash: flash-syscfg@92a0000 {
	97	compatible = "st,stih407-flash-syscfg", "syscon";
	98	reg = <0x92a0000 0x1000>;
	99	};
	100
	101	syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
	102	compatible = "st,stih407-sbc-reg-syscfg", "syscon";
	103	reg = <0x9600000 0x1000>;
	104	};
	105
	106	syscfg_core: core-syscfg@92b0000 {
	107	compatible = "st,stih407-core-syscfg", "syscon";
	108	reg = <0x92b0000 0x1000>;
	109	};
	110
	111	syscfg_lpm: lpm-syscfg@94b5100 {
	112	compatible = "st,stih407-lpm-syscfg", "syscon";
	113	reg = <0x94b5100 0x1000>;
	114	};
	115
	116	serial@9830000 {
	117	compatible = "st,asc";
	118	reg = <0x9830000 0x2c>;
	119	interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
	120	pinctrl-names = "default";
	121	pinctrl-0 = <&pinctrl_serial0>;
1befe7e4	122	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	123
	124	status = "disabled";
	125	};
	126
	127	serial@9831000 {
	128	compatible = "st,asc";
	129	reg = <0x9831000 0x2c>;
	130	interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
	131	pinctrl-names = "default";
	132	pinctrl-0 = <&pinctrl_serial1>;
1befe7e4	133	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	134
	135	status = "disabled";
	136	};
	137
	138	serial@9832000 {
	139	compatible = "st,asc";
	140	reg = <0x9832000 0x2c>;
	141	interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
	142	pinctrl-names = "default";
	143	pinctrl-0 = <&pinctrl_serial2>;
1befe7e4	144	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	145
	146	status = "disabled";
	147	};
	148
	149	/* SBC_ASC0 - UART10 */
	150	sbc_serial0: serial@9530000 {
	151	compatible = "st,asc";
	152	reg = <0x9530000 0x2c>;
	153	interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
	154	pinctrl-names = "default";
	155	pinctrl-0 = <&pinctrl_sbc_serial0>;
	156	clocks = <&clk_sysin>;
	157
	158	status = "disabled";
	159	};
	160
	161	serial@9531000 {
	162	compatible = "st,asc";
	163	reg = <0x9531000 0x2c>;
	164	interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
	165	pinctrl-names = "default";
	166	pinctrl-0 = <&pinctrl_sbc_serial1>;
	167	clocks = <&clk_sysin>;
	168
	169	status = "disabled";
	170	};
	171
	172	i2c@9840000 {
	173	compatible = "st,comms-ssc4-i2c";
	174	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	175	reg = <0x9840000 0x110>;
1befe7e4	176	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	177	clock-names = "ssc";
	178	clock-frequency = <400000>;
	179	pinctrl-names = "default";
	180	pinctrl-0 = <&pinctrl_i2c0_default>;
	181
	182	status = "disabled";
	183	};
	184
	185	i2c@9841000 {
	186	compatible = "st,comms-ssc4-i2c";
	187	reg = <0x9841000 0x110>;
	188	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	189	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	190	clock-names = "ssc";
	191	clock-frequency = <400000>;
	192	pinctrl-names = "default";
	193	pinctrl-0 = <&pinctrl_i2c1_default>;
	194
	195	status = "disabled";
	196	};
	197
	198	i2c@9842000 {
	199	compatible = "st,comms-ssc4-i2c";
	200	reg = <0x9842000 0x110>;
	201	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	202	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	203	clock-names = "ssc";
	204	clock-frequency = <400000>;
	205	pinctrl-names = "default";
	206	pinctrl-0 = <&pinctrl_i2c2_default>;
	207
	208	status = "disabled";
	209	};
	210
	211	i2c@9843000 {
	212	compatible = "st,comms-ssc4-i2c";
	213	reg = <0x9843000 0x110>;
	214	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	215	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	216	clock-names = "ssc";
	217	clock-frequency = <400000>;
	218	pinctrl-names = "default";
	219	pinctrl-0 = <&pinctrl_i2c3_default>;
	220
	221	status = "disabled";
	222	};
	223
	224	i2c@9844000 {
	225	compatible = "st,comms-ssc4-i2c";
	226	reg = <0x9844000 0x110>;
	227	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	228	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	229	clock-names = "ssc";
	230	clock-frequency = <400000>;
	231	pinctrl-names = "default";
	232	pinctrl-0 = <&pinctrl_i2c4_default>;
	233
	234	status = "disabled";
	235	};
	236
	237	i2c@9845000 {
	238	compatible = "st,comms-ssc4-i2c";
	239	reg = <0x9845000 0x110>;
	240	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	241	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	242	clock-names = "ssc";
	243	clock-frequency = <400000>;
	244	pinctrl-names = "default";
	245	pinctrl-0 = <&pinctrl_i2c5_default>;
	246
	247	status = "disabled";
	248	};
	249
	250
	251	/* SSCs on SBC */
	252	i2c@9540000 {
	253	compatible = "st,comms-ssc4-i2c";
	254	reg = <0x9540000 0x110>;
	255	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	256	clocks = <&clk_sysin>;
	257	clock-names = "ssc";
	258	clock-frequency = <400000>;
	259	pinctrl-names = "default";
	260	pinctrl-0 = <&pinctrl_i2c10_default>;
	261
	262	status = "disabled";
	263	};
	264
	265	i2c@9541000 {
	266	compatible = "st,comms-ssc4-i2c";
	267	reg = <0x9541000 0x110>;
	268	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	269	clocks = <&clk_sysin>;
	270	clock-names = "ssc";
	271	clock-frequency = <400000>;
	272	pinctrl-names = "default";
	273	pinctrl-0 = <&pinctrl_i2c11_default>;
	274
	275	status = "disabled";
	276	};
8facce13 PG	277
	278	usb2_picophy0: phy1 {
	279	compatible = "st,stih407-usb2-phy";
	280	#phy-cells = <0>;
	281	st,syscfg = <&syscfg_core 0x100 0xf4>;
	282	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	283	<&picophyreset STIH407_PICOPHY0_RESET>;
	284	reset-names = "global", "port";
	285	};
b26373c0 GF	286
	287	miphy28lp_phy: miphy28lp@9b22000 {
	288	compatible = "st,miphy28lp-phy";
	289	st,syscfg = <&syscfg_core>;
	290	#address-cells = <1>;
	291	#size-cells = <1>;
	292	ranges;
	293
	294	phy_port0: port@9b22000 {
	295	reg = <0x9b22000 0xff>,
	296	<0x9b09000 0xff>,
	297	<0x9b04000 0xff>;
	298	reg-names = "sata-up",
	299	"pcie-up",
	300	"pipew";
	301
	302	st,syscfg = <0x114 0x818 0xe0 0xec>;
	303	#phy-cells = <1>;
	304
	305	reset-names = "miphy-sw-rst";
	306	resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
	307	};
	308
	309	phy_port1: port@9b2a000 {
	310	reg = <0x9b2a000 0xff>,
	311	<0x9b19000 0xff>,
	312	<0x9b14000 0xff>;
	313	reg-names = "sata-up",
	314	"pcie-up",
	315	"pipew";
	316
	317	st,syscfg = <0x118 0x81c 0xe4 0xf0>;
	318
	319	#phy-cells = <1>;
	320
	321	reset-names = "miphy-sw-rst";
	322	resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
	323	};
	324
	325	phy_port2: port@8f95000 {
	326	reg = <0x8f95000 0xff>,
	327	<0x8f90000 0xff>;
	328	reg-names = "pipew",
	329	"usb3-up";
	330
	331	st,syscfg = <0x11c 0x820>;
	332
	333	#phy-cells = <1>;
	334
	335	reset-names = "miphy-sw-rst";
	336	resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
	337	};
	338	};
2c53c272 LJ	339
	340	spi@9840000 {
	341	compatible = "st,comms-ssc4-spi";
	342	reg = <0x9840000 0x110>;
	343	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	344	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	345	clock-names = "ssc";
	346	pinctrl-0 = <&pinctrl_spi0_default>;
	347	pinctrl-names = "default";
	348	#address-cells = <1>;
	349	#size-cells = <0>;
	350
	351	status = "disabled";
	352	};
	353
	354	spi@9841000 {
	355	compatible = "st,comms-ssc4-spi";
	356	reg = <0x9841000 0x110>;
	357	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	358	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	359	clock-names = "ssc";
	360
	361	status = "disabled";
	362	};
	363
	364	spi@9842000 {
	365	compatible = "st,comms-ssc4-spi";
	366	reg = <0x9842000 0x110>;
	367	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	368	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	369	clock-names = "ssc";
	370
	371	status = "disabled";
	372	};
	373
	374	spi@9843000 {
	375	compatible = "st,comms-ssc4-spi";
	376	reg = <0x9843000 0x110>;
	377	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	378	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	379	clock-names = "ssc";
	380
	381	status = "disabled";
	382	};
	383
	384	spi@9844000 {
	385	compatible = "st,comms-ssc4-spi";
	386	reg = <0x9844000 0x110>;
	387	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	388	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	389	clock-names = "ssc";
	390
	391	status = "disabled";
	392	};
b0bb2bae LJ	393
	394	/* SBC SSC */
	395	spi@9540000 {
	396	compatible = "st,comms-ssc4-spi";
	397	reg = <0x9540000 0x110>;
	398	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	399	clocks = <&clk_sysin>;
	400	clock-names = "ssc";
	401
	402	status = "disabled";
	403	};
	404
	405	spi@9541000 {
	406	compatible = "st,comms-ssc4-spi";
	407	reg = <0x9541000 0x110>;
	408	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	409	clocks = <&clk_sysin>;
	410	clock-names = "ssc";
	411
	412	status = "disabled";
	413	};
	414
	415	spi@9542000 {
	416	compatible = "st,comms-ssc4-spi";
	417	reg = <0x9542000 0x110>;
	418	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	419	clocks = <&clk_sysin>;
	420	clock-names = "ssc";
	421
	422	status = "disabled";
	423	};
f563a571 MC	424	};
f563a571 MC	425	};