[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / stih407-family.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/mfd/st-lpc.h>
#include <dt-bindings/reset-controller/stih407-resets.h>
/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	intc: interrupt-controller@08761000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x08761000 0x1000>, <0x08760100 0x100>;
	};

	scu@08760000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x08760000 0x1000>;
	};

	timer@08760200 {
		interrupt-parent = <&intc>;
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x08760200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&arm_periph_clk>;
	};

	l2: cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x08762000 0x1000>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		cache-unified;
		cache-level = <2>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;
		compatible = "simple-bus";

		powerdown: powerdown-controller {
			compatible = "st,stih407-powerdown";
			#reset-cells = <1>;
		};

		softreset: softreset-controller {
			compatible = "st,stih407-softreset";
			#reset-cells = <1>;
		};

		picophyreset: picophyreset-controller {
			compatible = "st,stih407-picophyreset";
			#reset-cells = <1>;
		};

		syscfg_sbc: sbc-syscfg@9620000 {
			compatible = "st,stih407-sbc-syscfg", "syscon";
			reg = <0x9620000 0x1000>;
		};

		syscfg_front: front-syscfg@9280000 {
			compatible = "st,stih407-front-syscfg", "syscon";
			reg = <0x9280000 0x1000>;
		};

		syscfg_rear: rear-syscfg@9290000 {
			compatible = "st,stih407-rear-syscfg", "syscon";
			reg = <0x9290000 0x1000>;
		};

		syscfg_flash: flash-syscfg@92a0000 {
			compatible = "st,stih407-flash-syscfg", "syscon";
			reg = <0x92a0000 0x1000>;
		};

		syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
			compatible = "st,stih407-sbc-reg-syscfg", "syscon";
			reg = <0x9600000 0x1000>;
		};

		syscfg_core: core-syscfg@92b0000 {
			compatible = "st,stih407-core-syscfg", "syscon";
			reg = <0x92b0000 0x1000>;
		};

		syscfg_lpm: lpm-syscfg@94b5100 {
			compatible = "st,stih407-lpm-syscfg", "syscon";
			reg = <0x94b5100 0x1000>;
		};

		serial@9830000 {
			compatible = "st,asc";
			reg = <0x9830000 0x2c>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial0>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		serial@9831000 {
			compatible = "st,asc";
			reg = <0x9831000 0x2c>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial1>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		serial@9832000 {
			compatible = "st,asc";
			reg = <0x9832000 0x2c>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial2>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		/* SBC_ASC0 - UART10 */
		sbc_serial0: serial@9530000 {
			compatible = "st,asc";
			reg = <0x9530000 0x2c>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sbc_serial0>;
			clocks = <&clk_sysin>;

			status = "disabled";
		};

		serial@9531000 {
			compatible = "st,asc";
			reg = <0x9531000 0x2c>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sbc_serial1>;
			clocks = <&clk_sysin>;

			status = "disabled";
		};

		i2c@9840000 {
			compatible = "st,comms-ssc4-i2c";
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x9840000 0x110>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0_default>;

			status = "disabled";
		};

		i2c@9841000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9841000 0x110>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1_default>;

			status = "disabled";
		};

		i2c@9842000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9842000 0x110>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2_default>;

			status = "disabled";
		};

		i2c@9843000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9843000 0x110>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3_default>;

			status = "disabled";
		};

		i2c@9844000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9844000 0x110>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4_default>;

			status = "disabled";
		};

		i2c@9845000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9845000 0x110>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c5_default>;

			status = "disabled";
		};


		/* SSCs on SBC */
		i2c@9540000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9540000 0x110>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c10_default>;

			status = "disabled";
		};

		i2c@9541000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9541000 0x110>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c11_default>;

			status = "disabled";
		};

		usb2_picophy0: phy1 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0x100 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY0_RESET>;
			reset-names = "global", "port";
		};

		miphy28lp_phy: miphy28lp@9b22000 {
			compatible = "st,miphy28lp-phy";
			st,syscfg = <&syscfg_core>;
			#address-cells	= <1>;
			#size-cells	= <1>;
			ranges;

			phy_port0: port@9b22000 {
				reg = <0x9b22000 0xff>,
				      <0x9b09000 0xff>,
				      <0x9b04000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x114 0x818 0xe0 0xec>;
				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
			};

			phy_port1: port@9b2a000 {
				reg = <0x9b2a000 0xff>,
				      <0x9b19000 0xff>,
				      <0x9b14000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x118 0x81c 0xe4 0xf0>;

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
			};

			phy_port2: port@8f95000 {
				reg = <0x8f95000 0xff>,
				      <0x8f90000 0xff>;
				reg-names = "pipew",
					    "usb3-up";

				st,syscfg = <0x11c 0x820>;

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
			};
		};

		spi@9840000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9840000 0x110>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-0 = <&pinctrl_spi0_default>;
			pinctrl-names = "default";
			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};

		spi@9841000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9841000 0x110>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9842000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9842000 0x110>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9843000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9843000 0x110>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9844000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9844000 0x110>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";

			status = "disabled";
		};

		/* SBC SSC */
		spi@9540000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9540000 0x110>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9541000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9541000 0x110>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";

			status = "disabled";
		};

		spi@9542000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9542000 0x110>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";

			status = "disabled";
		};

		mmc0: sdhci@09060000 {
			compatible = "st,sdhci-stih407", "st,sdhci";
			status = "disabled";
			reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
			reg-names = "mmc", "top-mmc-delay";
			interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
			interrupt-names = "mmcirq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_mmc0>;
			clock-names = "mmc";
			clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
			bus-width = <8>;
			non-removable;
		};

		mmc1: sdhci@09080000 {
			compatible = "st,sdhci-stih407", "st,sdhci";
			status = "disabled";
			reg = <0x09080000 0x7ff>;
			reg-names = "mmc";
			interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
			interrupt-names = "mmcirq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sd1>;
			clock-names = "mmc";
			clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
			resets = <&softreset STIH407_MMC1_SOFTRESET>;
			bus-width = <4>;
		};

		/* Watchdog and Real-Time Clock */
		lpc@8787000 {
			compatible = "st,stih407-lpc";
			reg = <0x8787000 0x1000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
			timeout-sec = <120>;
			st,syscfg = <&syscfg_core>;
			st,lpc-mode = <ST_LPC_MODE_WDT>;
		};

		lpc@8788000 {
			compatible = "st,stih407-lpc";
			reg = <0x8788000 0x1000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
			st,lpc-mode = <ST_LPC_MODE_RTC>;
		};
	};
};
Commit	Line	Data
f563a571 MC	1	/*
	2	* Copyright (C) 2014 STMicroelectronics Limited.
	3	* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
f563a571	9	#include "stih407-pinctrl.dtsi"
358764f3	10	#include <dt-bindings/mfd/st-lpc.h>
b864a0b9	11	#include <dt-bindings/reset-controller/stih407-resets.h>
f563a571 MC	12	/ {
	13	#address-cells = <1>;
	14	#size-cells = <1>;
	15
	16	cpus {
	17	#address-cells = <1>;
	18	#size-cells = <0>;
	19	cpu@0 {
	20	device_type = "cpu";
	21	compatible = "arm,cortex-a9";
	22	reg = <0>;
	23	};
	24	cpu@1 {
	25	device_type = "cpu";
	26	compatible = "arm,cortex-a9";
	27	reg = <1>;
	28	};
	29	};
	30
	31	intc: interrupt-controller@08761000 {
	32	compatible = "arm,cortex-a9-gic";
	33	#interrupt-cells = <3>;
	34	interrupt-controller;
	35	reg = <0x08761000 0x1000>, <0x08760100 0x100>;
	36	};
	37
	38	scu@08760000 {
	39	compatible = "arm,cortex-a9-scu";
	40	reg = <0x08760000 0x1000>;
	41	};
	42
	43	timer@08760200 {
	44	interrupt-parent = <&intc>;
	45	compatible = "arm,cortex-a9-global-timer";
	46	reg = <0x08760200 0x100>;
	47	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	48	clocks = <&arm_periph_clk>;
	49	};
	50
	51	l2: cache-controller {
	52	compatible = "arm,pl310-cache";
	53	reg = <0x08762000 0x1000>;
	54	arm,data-latency = <3 3 3>;
	55	arm,tag-latency = <2 2 2>;
	56	cache-unified;
	57	cache-level = <2>;
	58	};
	59
	60	soc {
	61	#address-cells = <1>;
	62	#size-cells = <1>;
	63	interrupt-parent = <&intc>;
	64	ranges;
	65	compatible = "simple-bus";
	66
b864a0b9 PG	67	powerdown: powerdown-controller {
	68	compatible = "st,stih407-powerdown";
	69	#reset-cells = <1>;
	70	};
	71
	72	softreset: softreset-controller {
	73	compatible = "st,stih407-softreset";
	74	#reset-cells = <1>;
	75	};
	76
	77	picophyreset: picophyreset-controller {
	78	compatible = "st,stih407-picophyreset";
	79	#reset-cells = <1>;
	80	};
	81
f563a571 MC	82	syscfg_sbc: sbc-syscfg@9620000 {
	83	compatible = "st,stih407-sbc-syscfg", "syscon";
	84	reg = <0x9620000 0x1000>;
	85	};
	86
	87	syscfg_front: front-syscfg@9280000 {
	88	compatible = "st,stih407-front-syscfg", "syscon";
	89	reg = <0x9280000 0x1000>;
	90	};
	91
	92	syscfg_rear: rear-syscfg@9290000 {
	93	compatible = "st,stih407-rear-syscfg", "syscon";
	94	reg = <0x9290000 0x1000>;
	95	};
	96
	97	syscfg_flash: flash-syscfg@92a0000 {
	98	compatible = "st,stih407-flash-syscfg", "syscon";
	99	reg = <0x92a0000 0x1000>;
	100	};
	101
	102	syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
	103	compatible = "st,stih407-sbc-reg-syscfg", "syscon";
	104	reg = <0x9600000 0x1000>;
	105	};
	106
	107	syscfg_core: core-syscfg@92b0000 {
	108	compatible = "st,stih407-core-syscfg", "syscon";
	109	reg = <0x92b0000 0x1000>;
	110	};
	111
	112	syscfg_lpm: lpm-syscfg@94b5100 {
	113	compatible = "st,stih407-lpm-syscfg", "syscon";
	114	reg = <0x94b5100 0x1000>;
	115	};
	116
	117	serial@9830000 {
	118	compatible = "st,asc";
	119	reg = <0x9830000 0x2c>;
	120	interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
	121	pinctrl-names = "default";
	122	pinctrl-0 = <&pinctrl_serial0>;
1befe7e4	123	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	124
	125	status = "disabled";
	126	};
	127
	128	serial@9831000 {
	129	compatible = "st,asc";
	130	reg = <0x9831000 0x2c>;
	131	interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
	132	pinctrl-names = "default";
	133	pinctrl-0 = <&pinctrl_serial1>;
1befe7e4	134	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	135
	136	status = "disabled";
	137	};
	138
	139	serial@9832000 {
	140	compatible = "st,asc";
	141	reg = <0x9832000 0x2c>;
	142	interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
	143	pinctrl-names = "default";
	144	pinctrl-0 = <&pinctrl_serial2>;
1befe7e4	145	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	146
	147	status = "disabled";
	148	};
	149
	150	/* SBC_ASC0 - UART10 */
	151	sbc_serial0: serial@9530000 {
	152	compatible = "st,asc";
	153	reg = <0x9530000 0x2c>;
	154	interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
	155	pinctrl-names = "default";
	156	pinctrl-0 = <&pinctrl_sbc_serial0>;
	157	clocks = <&clk_sysin>;
	158
	159	status = "disabled";
	160	};
	161
	162	serial@9531000 {
	163	compatible = "st,asc";
	164	reg = <0x9531000 0x2c>;
	165	interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
	166	pinctrl-names = "default";
	167	pinctrl-0 = <&pinctrl_sbc_serial1>;
	168	clocks = <&clk_sysin>;
	169
	170	status = "disabled";
	171	};
	172
	173	i2c@9840000 {
	174	compatible = "st,comms-ssc4-i2c";
	175	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	176	reg = <0x9840000 0x110>;
1befe7e4	177	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	178	clock-names = "ssc";
	179	clock-frequency = <400000>;
	180	pinctrl-names = "default";
	181	pinctrl-0 = <&pinctrl_i2c0_default>;
	182
	183	status = "disabled";
	184	};
	185
	186	i2c@9841000 {
	187	compatible = "st,comms-ssc4-i2c";
	188	reg = <0x9841000 0x110>;
	189	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	190	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	191	clock-names = "ssc";
	192	clock-frequency = <400000>;
	193	pinctrl-names = "default";
	194	pinctrl-0 = <&pinctrl_i2c1_default>;
	195
	196	status = "disabled";
	197	};
	198
	199	i2c@9842000 {
	200	compatible = "st,comms-ssc4-i2c";
	201	reg = <0x9842000 0x110>;
	202	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	203	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	204	clock-names = "ssc";
	205	clock-frequency = <400000>;
	206	pinctrl-names = "default";
	207	pinctrl-0 = <&pinctrl_i2c2_default>;
	208
	209	status = "disabled";
	210	};
	211
	212	i2c@9843000 {
	213	compatible = "st,comms-ssc4-i2c";
	214	reg = <0x9843000 0x110>;
	215	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	216	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	217	clock-names = "ssc";
	218	clock-frequency = <400000>;
	219	pinctrl-names = "default";
	220	pinctrl-0 = <&pinctrl_i2c3_default>;
	221
	222	status = "disabled";
	223	};
	224
	225	i2c@9844000 {
	226	compatible = "st,comms-ssc4-i2c";
	227	reg = <0x9844000 0x110>;
	228	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	229	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	230	clock-names = "ssc";
	231	clock-frequency = <400000>;
	232	pinctrl-names = "default";
	233	pinctrl-0 = <&pinctrl_i2c4_default>;
	234
	235	status = "disabled";
	236	};
	237
	238	i2c@9845000 {
	239	compatible = "st,comms-ssc4-i2c";
	240	reg = <0x9845000 0x110>;
	241	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	242	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	243	clock-names = "ssc";
	244	clock-frequency = <400000>;
	245	pinctrl-names = "default";
	246	pinctrl-0 = <&pinctrl_i2c5_default>;
	247
	248	status = "disabled";
	249	};
	250
	251
	252	/* SSCs on SBC */
	253	i2c@9540000 {
	254	compatible = "st,comms-ssc4-i2c";
	255	reg = <0x9540000 0x110>;
	256	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	257	clocks = <&clk_sysin>;
	258	clock-names = "ssc";
	259	clock-frequency = <400000>;
	260	pinctrl-names = "default";
	261	pinctrl-0 = <&pinctrl_i2c10_default>;
	262
	263	status = "disabled";
	264	};
	265
	266	i2c@9541000 {
	267	compatible = "st,comms-ssc4-i2c";
	268	reg = <0x9541000 0x110>;
	269	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	270	clocks = <&clk_sysin>;
	271	clock-names = "ssc";
	272	clock-frequency = <400000>;
	273	pinctrl-names = "default";
	274	pinctrl-0 = <&pinctrl_i2c11_default>;
	275
	276	status = "disabled";
	277	};
8facce13 PG	278
	279	usb2_picophy0: phy1 {
	280	compatible = "st,stih407-usb2-phy";
	281	#phy-cells = <0>;
	282	st,syscfg = <&syscfg_core 0x100 0xf4>;
	283	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	284	<&picophyreset STIH407_PICOPHY0_RESET>;
	285	reset-names = "global", "port";
	286	};
b26373c0 GF	287
	288	miphy28lp_phy: miphy28lp@9b22000 {
	289	compatible = "st,miphy28lp-phy";
	290	st,syscfg = <&syscfg_core>;
	291	#address-cells = <1>;
	292	#size-cells = <1>;
	293	ranges;
	294
	295	phy_port0: port@9b22000 {
	296	reg = <0x9b22000 0xff>,
	297	<0x9b09000 0xff>,
	298	<0x9b04000 0xff>;
	299	reg-names = "sata-up",
	300	"pcie-up",
	301	"pipew";
	302
	303	st,syscfg = <0x114 0x818 0xe0 0xec>;
	304	#phy-cells = <1>;
	305
	306	reset-names = "miphy-sw-rst";
	307	resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
	308	};
	309
	310	phy_port1: port@9b2a000 {
	311	reg = <0x9b2a000 0xff>,
	312	<0x9b19000 0xff>,
	313	<0x9b14000 0xff>;
	314	reg-names = "sata-up",
	315	"pcie-up",
	316	"pipew";
	317
	318	st,syscfg = <0x118 0x81c 0xe4 0xf0>;
	319
	320	#phy-cells = <1>;
	321
	322	reset-names = "miphy-sw-rst";
	323	resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
	324	};
	325
	326	phy_port2: port@8f95000 {
	327	reg = <0x8f95000 0xff>,
	328	<0x8f90000 0xff>;
	329	reg-names = "pipew",
	330	"usb3-up";
	331
	332	st,syscfg = <0x11c 0x820>;
	333
	334	#phy-cells = <1>;
	335
	336	reset-names = "miphy-sw-rst";
	337	resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
	338	};
	339	};
2c53c272 LJ	340
	341	spi@9840000 {
	342	compatible = "st,comms-ssc4-spi";
	343	reg = <0x9840000 0x110>;
	344	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	345	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	346	clock-names = "ssc";
	347	pinctrl-0 = <&pinctrl_spi0_default>;
	348	pinctrl-names = "default";
	349	#address-cells = <1>;
	350	#size-cells = <0>;
	351
	352	status = "disabled";
	353	};
	354
	355	spi@9841000 {
	356	compatible = "st,comms-ssc4-spi";
	357	reg = <0x9841000 0x110>;
	358	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	359	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	360	clock-names = "ssc";
	361
	362	status = "disabled";
	363	};
	364
	365	spi@9842000 {
	366	compatible = "st,comms-ssc4-spi";
	367	reg = <0x9842000 0x110>;
	368	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	369	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	370	clock-names = "ssc";
	371
	372	status = "disabled";
	373	};
	374
	375	spi@9843000 {
	376	compatible = "st,comms-ssc4-spi";
	377	reg = <0x9843000 0x110>;
	378	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	379	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	380	clock-names = "ssc";
	381
	382	status = "disabled";
	383	};
	384
	385	spi@9844000 {
	386	compatible = "st,comms-ssc4-spi";
	387	reg = <0x9844000 0x110>;
	388	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	389	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	390	clock-names = "ssc";
	391
	392	status = "disabled";
	393	};
b0bb2bae LJ	394
	395	/* SBC SSC */
	396	spi@9540000 {
	397	compatible = "st,comms-ssc4-spi";
	398	reg = <0x9540000 0x110>;
	399	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	400	clocks = <&clk_sysin>;
	401	clock-names = "ssc";
	402
	403	status = "disabled";
	404	};
	405
	406	spi@9541000 {
	407	compatible = "st,comms-ssc4-spi";
	408	reg = <0x9541000 0x110>;
	409	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	410	clocks = <&clk_sysin>;
	411	clock-names = "ssc";
	412
	413	status = "disabled";
	414	};
	415
	416	spi@9542000 {
	417	compatible = "st,comms-ssc4-spi";
	418	reg = <0x9542000 0x110>;
	419	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	420	clocks = <&clk_sysin>;
	421	clock-names = "ssc";
	422
	423	status = "disabled";
	424	};
9286ac48 PG	425
	426	mmc0: sdhci@09060000 {
	427	compatible = "st,sdhci-stih407", "st,sdhci";
	428	status = "disabled";
	429	reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
	430	reg-names = "mmc", "top-mmc-delay";
	431	interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
	432	interrupt-names = "mmcirq";
	433	pinctrl-names = "default";
	434	pinctrl-0 = <&pinctrl_mmc0>;
	435	clock-names = "mmc";
	436	clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
	437	bus-width = <8>;
	438	non-removable;
	439	};
	440
	441	mmc1: sdhci@09080000 {
	442	compatible = "st,sdhci-stih407", "st,sdhci";
	443	status = "disabled";
	444	reg = <0x09080000 0x7ff>;
	445	reg-names = "mmc";
	446	interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
	447	interrupt-names = "mmcirq";
	448	pinctrl-names = "default";
	449	pinctrl-0 = <&pinctrl_sd1>;
	450	clock-names = "mmc";
	451	clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
	452	resets = <&softreset STIH407_MMC1_SOFTRESET>;
	453	bus-width = <4>;
	454	};
358764f3 LJ	455
	456	/* Watchdog and Real-Time Clock */
	457	lpc@8787000 {
	458	compatible = "st,stih407-lpc";
	459	reg = <0x8787000 0x1000>;
	460	interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
	461	clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
	462	timeout-sec = <120>;
	463	st,syscfg = <&syscfg_core>;
	464	st,lpc-mode = <ST_LPC_MODE_WDT>;
	465	};
	466
	467	lpc@8788000 {
	468	compatible = "st,stih407-lpc";
	469	reg = <0x8788000 0x1000>;
	470	interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
	471	clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
	472	st,lpc-mode = <ST_LPC_MODE_RTC>;
	473	};
f563a571 MC	474	};
f563a571 MC	475	};