[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / stih407-family.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/mfd/st-lpc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/stih407-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;

			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
			cpu-release-addr = <0x94100A4>;

					 /* kHz     uV   */
			operating-points = <1500000 0
					    1200000 0
					    800000  0
					    500000  0>;

			clocks = <&clk_m_a9>;
			clock-names = "cpu";
			clock-latency = <100000>;
			cpu0-supply = <&pwm_regulator>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;

			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
			cpu-release-addr = <0x94100A4>;

					 /* kHz     uV   */
			operating-points = <1500000 0
					    1200000 0
					    800000  0
					    500000  0>;
		};
	};

	intc: interrupt-controller@08761000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x08761000 0x1000>, <0x08760100 0x100>;
	};

	scu@08760000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x08760000 0x1000>;
	};

	timer@08760200 {
		interrupt-parent = <&intc>;
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x08760200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&arm_periph_clk>;
	};

	l2: cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x08762000 0x1000>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		cache-unified;
		cache-level = <2>;
	};

	arm-pmu {
		interrupt-parent = <&intc>;
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	};

	pwm_regulator: pwm-regulator {
		compatible = "pwm-regulator";
		pwms = <&pwm1 3 8448>;
		regulator-name = "CPU_1V0_AVS";
		regulator-min-microvolt = <784000>;
		regulator-max-microvolt = <1299000>;
		regulator-always-on;
		max-duty-cycle = <255>;
		status = "okay";
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;
		compatible = "simple-bus";

		restart {
			compatible = "st,stih407-restart";
			st,syscfg = <&syscfg_sbc_reg>;
			status = "okay";
		};

		powerdown: powerdown-controller {
			compatible = "st,stih407-powerdown";
			#reset-cells = <1>;
		};

		softreset: softreset-controller {
			compatible = "st,stih407-softreset";
			#reset-cells = <1>;
		};

		picophyreset: picophyreset-controller {
			compatible = "st,stih407-picophyreset";
			#reset-cells = <1>;
		};

		syscfg_sbc: sbc-syscfg@9620000 {
			compatible = "st,stih407-sbc-syscfg", "syscon";
			reg = <0x9620000 0x1000>;
		};

		syscfg_front: front-syscfg@9280000 {
			compatible = "st,stih407-front-syscfg", "syscon";
			reg = <0x9280000 0x1000>;
		};

		syscfg_rear: rear-syscfg@9290000 {
			compatible = "st,stih407-rear-syscfg", "syscon";
			reg = <0x9290000 0x1000>;
		};

		syscfg_flash: flash-syscfg@92a0000 {
			compatible = "st,stih407-flash-syscfg", "syscon";
			reg = <0x92a0000 0x1000>;
		};

		syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
			compatible = "st,stih407-sbc-reg-syscfg", "syscon";
			reg = <0x9600000 0x1000>;
		};

		syscfg_core: core-syscfg@92b0000 {
			compatible = "st,stih407-core-syscfg", "syscon";
			reg = <0x92b0000 0x1000>;
		};

		syscfg_lpm: lpm-syscfg@94b5100 {
			compatible = "st,stih407-lpm-syscfg", "syscon";
			reg = <0x94b5100 0x1000>;
		};

		irq-syscfg {
			compatible    = "st,stih407-irq-syscfg";
			st,syscfg     = <&syscfg_core>;
			st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
					<ST_IRQ_SYSCFG_PMU_1>;
			st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
					<ST_IRQ_SYSCFG_DISABLED>;
		};

		/* Display */
		vtg_main: sti-vtg-main@8d02800 {
			compatible = "st,vtg";
			reg = <0x8d02800 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
		};

		vtg_aux: sti-vtg-aux@8d00200 {
			compatible = "st,vtg";
			reg = <0x8d00200 0x100>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
		};

		serial@9830000 {
			compatible = "st,asc";
			reg = <0x9830000 0x2c>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial0>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		serial@9831000 {
			compatible = "st,asc";
			reg = <0x9831000 0x2c>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial1>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		serial@9832000 {
			compatible = "st,asc";
			reg = <0x9832000 0x2c>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_serial2>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			status = "disabled";
		};

		/* SBC_ASC0 - UART10 */
		sbc_serial0: serial@9530000 {
			compatible = "st,asc";
			reg = <0x9530000 0x2c>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sbc_serial0>;
			clocks = <&clk_sysin>;

			status = "disabled";
		};

		serial@9531000 {
			compatible = "st,asc";
			reg = <0x9531000 0x2c>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sbc_serial1>;
			clocks = <&clk_sysin>;

			status = "disabled";
		};

		i2c@9840000 {
			compatible = "st,comms-ssc4-i2c";
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x9840000 0x110>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0_default>;

			status = "disabled";
		};

		i2c@9841000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9841000 0x110>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1_default>;

			status = "disabled";
		};

		i2c@9842000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9842000 0x110>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2_default>;

			status = "disabled";
		};

		i2c@9843000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9843000 0x110>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3_default>;

			status = "disabled";
		};

		i2c@9844000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9844000 0x110>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4_default>;

			status = "disabled";
		};

		i2c@9845000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9845000 0x110>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c5_default>;

			status = "disabled";
		};


		/* SSCs on SBC */
		i2c@9540000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9540000 0x110>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c10_default>;

			status = "disabled";
		};

		i2c@9541000 {
			compatible = "st,comms-ssc4-i2c";
			reg = <0x9541000 0x110>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			clock-frequency = <400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c11_default>;

			status = "disabled";
		};

		usb2_picophy0: phy1 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0x100 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY2_RESET>;
			reset-names = "global", "port";
		};

		miphy28lp_phy: miphy28lp@9b22000 {
			compatible = "st,miphy28lp-phy";
			st,syscfg = <&syscfg_core>;
			#address-cells	= <1>;
			#size-cells	= <1>;
			ranges;

			phy_port0: port@9b22000 {
				reg = <0x9b22000 0xff>,
				      <0x9b09000 0xff>,
				      <0x9b04000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x114 0x818 0xe0 0xec>;
				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
			};

			phy_port1: port@9b2a000 {
				reg = <0x9b2a000 0xff>,
				      <0x9b19000 0xff>,
				      <0x9b14000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x118 0x81c 0xe4 0xf0>;

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
			};

			phy_port2: port@8f95000 {
				reg = <0x8f95000 0xff>,
				      <0x8f90000 0xff>;
				reg-names = "pipew",
					    "usb3-up";

				st,syscfg = <0x11c 0x820>;

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
			};
		};

		spi@9840000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9840000 0x110>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-0 = <&pinctrl_spi0_default>;
			pinctrl-names = "default";
			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};

		spi@9841000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9841000 0x110>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi1_default>;

			status = "disabled";
		};

		spi@9842000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9842000 0x110>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi2_default>;

			status = "disabled";
		};

		spi@9843000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9843000 0x110>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi3_default>;

			status = "disabled";
		};

		spi@9844000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9844000 0x110>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi4_default>;

			status = "disabled";
		};

		/* SBC SSC */
		spi@9540000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9540000 0x110>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi10_default>;

			status = "disabled";
		};

		spi@9541000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9541000 0x110>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi11_default>;

			status = "disabled";
		};

		spi@9542000 {
			compatible = "st,comms-ssc4-spi";
			reg = <0x9542000 0x110>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_sysin>;
			clock-names = "ssc";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi12_default>;

			status = "disabled";
		};

		mmc0: sdhci@09060000 {
			compatible = "st,sdhci-stih407", "st,sdhci";
			status = "disabled";
			reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
			reg-names = "mmc", "top-mmc-delay";
			interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
			interrupt-names = "mmcirq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_mmc0>;
			clock-names = "mmc";
			clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
			bus-width = <8>;
			non-removable;
		};

		mmc1: sdhci@09080000 {
			compatible = "st,sdhci-stih407", "st,sdhci";
			status = "disabled";
			reg = <0x09080000 0x7ff>;
			reg-names = "mmc";
			interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
			interrupt-names = "mmcirq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sd1>;
			clock-names = "mmc";
			clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
			resets = <&softreset STIH407_MMC1_SOFTRESET>;
			bus-width = <4>;
		};

		/* Watchdog and Real-Time Clock */
		lpc@8787000 {
			compatible = "st,stih407-lpc";
			reg = <0x8787000 0x1000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
			timeout-sec = <120>;
			st,syscfg = <&syscfg_core>;
			st,lpc-mode = <ST_LPC_MODE_WDT>;
		};

		lpc@8788000 {
			compatible = "st,stih407-lpc";
			reg = <0x8788000 0x1000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
			st,lpc-mode = <ST_LPC_MODE_RTC>;
		};

		sata0: sata@9b20000 {
			compatible = "st,ahci";
			reg = <0x9b20000 0x1000>;

			interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
			interrupt-names = "hostc";

			phys = <&phy_port0 PHY_TYPE_SATA>;
			phy-names = "ahci_phy";

			resets = <&powerdown STIH407_SATA0_POWERDOWN>,
				 <&softreset STIH407_SATA0_SOFTRESET>,
				 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
			reset-names = "pwr-dwn", "sw-rst", "pwr-rst";

			clock-names = "ahci_clk";
			clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;

			status = "disabled";
		};

		sata1: sata@9b28000 {
			compatible = "st,ahci";
			reg = <0x9b28000 0x1000>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
			interrupt-names = "hostc";

			phys = <&phy_port1 PHY_TYPE_SATA>;
			phy-names = "ahci_phy";

			resets = <&powerdown STIH407_SATA1_POWERDOWN>,
				 <&softreset STIH407_SATA1_SOFTRESET>,
				 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
			reset-names = "pwr-dwn",
				      "sw-rst",
				      "pwr-rst";

			clock-names = "ahci_clk";
			clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;

			status = "disabled";
		};


		st_dwc3: dwc3@8f94000 {
			compatible	= "st,stih407-dwc3";
			reg		= <0x08f94000 0x1000>, <0x110 0x4>;
			reg-names	= "reg-glue", "syscfg-reg";
			st,syscfg	= <&syscfg_core>;
			resets		= <&powerdown STIH407_USB3_POWERDOWN>,
					  <&softreset STIH407_MIPHY2_SOFTRESET>;
			reset-names	= "powerdown", "softreset";
			#address-cells	= <1>;
			#size-cells	= <1>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_usb3>;
			ranges;

			status = "disabled";

			dwc3: dwc3@9900000 {
				compatible	= "snps,dwc3";
				reg		= <0x09900000 0x100000>;
				interrupts	= <GIC_SPI 155 IRQ_TYPE_NONE>;
				dr_mode		= "host";
				phy-names	= "usb2-phy", "usb3-phy";
				phys		= <&usb2_picophy0>,
						  <&phy_port2 PHY_TYPE_USB3>;
			};
		};

		/* COMMS PWM Module */
		pwm0: pwm@9810000 {
			compatible	= "st,sti-pwm";
			#pwm-cells	= <2>;
			reg		= <0x9810000 0x68>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_pwm0_chan0_default>;
			clock-names	= "pwm";
			clocks		= <&clk_sysin>;
			st,pwm-num-chan = <1>;

			status		= "disabled";
		};

		/* SBC PWM Module */
		pwm1: pwm@9510000 {
			compatible	= "st,sti-pwm";
			#pwm-cells	= <2>;
			reg		= <0x9510000 0x68>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_pwm1_chan0_default
					&pinctrl_pwm1_chan1_default
					&pinctrl_pwm1_chan2_default
					&pinctrl_pwm1_chan3_default>;
			clock-names	= "pwm";
			clocks		= <&clk_sysin>;
			st,pwm-num-chan = <4>;

			status		= "disabled";
		};

		rng10: rng@08a89000 {
			compatible      = "st,rng";
			reg		= <0x08a89000 0x1000>;
			clocks          = <&clk_sysin>;
			status		= "okay";
		};

		rng11: rng@08a8a000 {
			compatible      = "st,rng";
			reg		= <0x08a8a000 0x1000>;
			clocks          = <&clk_sysin>;
			status		= "okay";
		};

		ethernet0: dwmac@9630000 {
			device_type = "network";
			status = "disabled";
			compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
			reg = <0x9630000 0x8000>, <0x80 0x4>;
			reg-names = "stmmaceth", "sti-ethconf";

			st,syscon = <&syscfg_sbc_reg 0x80>;
			st,gmac_en;
			resets = <&softreset STIH407_ETH1_SOFTRESET>;
			reset-names = "stmmaceth";

			interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
				     <GIC_SPI 99 IRQ_TYPE_NONE>;
			interrupt-names = "macirq", "eth_wake_irq";

			/* DMA Bus Mode */
			snps,pbl = <8>;

			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_rgmii1>;

			clock-names = "stmmaceth", "sti-ethclk";
			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
				 <&clk_s_c0_flexgen CLK_ETH_PHY>;
		};

		rng10: rng@08a89000 {
			compatible      = "st,rng";
			reg		= <0x08a89000 0x1000>;
			clocks          = <&clk_sysin>;
			status		= "okay";
		};

		rng11: rng@08a8a000 {
			compatible      = "st,rng";
			reg		= <0x08a8a000 0x1000>;
			clocks          = <&clk_sysin>;
			status		= "okay";
		};
	};
};
Commit	Line	Data
f563a571 MC	1	/*
	2	* Copyright (C) 2014 STMicroelectronics Limited.
	3	* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
f563a571	9	#include "stih407-pinctrl.dtsi"
358764f3	10	#include <dt-bindings/mfd/st-lpc.h>
b3d37f92	11	#include <dt-bindings/phy/phy.h>
efdf5aa8	12	#include <dt-bindings/reset/stih407-resets.h>
107dea0c	13	#include <dt-bindings/interrupt-controller/irq-st.h>
f563a571 MC	14	/ {
	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
	21	cpu@0 {
	22	device_type = "cpu";
	23	compatible = "arm,cortex-a9";
	24	reg = <0>;
6fef7953	25
c1dc02da PG	26	/* u-boot puts hpen in SBC dmem at 0xa4 offset */
c1dc02da PG	27	cpu-release-addr = <0x94100A4>;
6fef7953 LJ	28
	29	/* kHz uV */
	30	operating-points = <1500000 0
	31	1200000 0
	32	800000 0
	33	500000 0>;
4ad8f3ac LJ	34
	35	clocks = <&clk_m_a9>;
	36	clock-names = "cpu";
	37	clock-latency = <100000>;
fe7de3c3	38	cpu0-supply = <&pwm_regulator>;
f563a571 MC	39	};
	40	cpu@1 {
	41	device_type = "cpu";
	42	compatible = "arm,cortex-a9";
	43	reg = <1>;
6fef7953	44
c1dc02da PG	45	/* u-boot puts hpen in SBC dmem at 0xa4 offset */
c1dc02da PG	46	cpu-release-addr = <0x94100A4>;
6fef7953 LJ	47
	48	/* kHz uV */
	49	operating-points = <1500000 0
	50	1200000 0
	51	800000 0
	52	500000 0>;
f563a571 MC	53	};
	54	};
	55
	56	intc: interrupt-controller@08761000 {
	57	compatible = "arm,cortex-a9-gic";
	58	#interrupt-cells = <3>;
	59	interrupt-controller;
	60	reg = <0x08761000 0x1000>, <0x08760100 0x100>;
	61	};
	62
	63	scu@08760000 {
	64	compatible = "arm,cortex-a9-scu";
	65	reg = <0x08760000 0x1000>;
	66	};
	67
	68	timer@08760200 {
	69	interrupt-parent = <&intc>;
	70	compatible = "arm,cortex-a9-global-timer";
	71	reg = <0x08760200 0x100>;
	72	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	73	clocks = <&arm_periph_clk>;
	74	};
	75
	76	l2: cache-controller {
	77	compatible = "arm,pl310-cache";
	78	reg = <0x08762000 0x1000>;
	79	arm,data-latency = <3 3 3>;
	80	arm,tag-latency = <2 2 2>;
	81	cache-unified;
	82	cache-level = <2>;
	83	};
	84
00133b91 LJ	85	arm-pmu {
	86	interrupt-parent = <&intc>;
	87	compatible = "arm,cortex-a9-pmu";
	88	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	89	};
	90
23155ffc LJ	91	pwm_regulator: pwm-regulator {
	92	compatible = "pwm-regulator";
	93	pwms = <&pwm1 3 8448>;
	94	regulator-name = "CPU_1V0_AVS";
	95	regulator-min-microvolt = <784000>;
	96	regulator-max-microvolt = <1299000>;
	97	regulator-always-on;
	98	max-duty-cycle = <255>;
	99	status = "okay";
	100	};
	101
f563a571 MC	102	soc {
	103	#address-cells = <1>;
	104	#size-cells = <1>;
	105	interrupt-parent = <&intc>;
	106	ranges;
	107	compatible = "simple-bus";
	108
48f3fe6b LJ	109	restart {
	110	compatible = "st,stih407-restart";
	111	st,syscfg = <&syscfg_sbc_reg>;
	112	status = "okay";
	113	};
	114
b864a0b9 PG	115	powerdown: powerdown-controller {
	116	compatible = "st,stih407-powerdown";
	117	#reset-cells = <1>;
	118	};
	119
	120	softreset: softreset-controller {
	121	compatible = "st,stih407-softreset";
	122	#reset-cells = <1>;
	123	};
	124
	125	picophyreset: picophyreset-controller {
	126	compatible = "st,stih407-picophyreset";
	127	#reset-cells = <1>;
	128	};
	129
f563a571 MC	130	syscfg_sbc: sbc-syscfg@9620000 {
	131	compatible = "st,stih407-sbc-syscfg", "syscon";
	132	reg = <0x9620000 0x1000>;
	133	};
	134
	135	syscfg_front: front-syscfg@9280000 {
	136	compatible = "st,stih407-front-syscfg", "syscon";
	137	reg = <0x9280000 0x1000>;
	138	};
	139
	140	syscfg_rear: rear-syscfg@9290000 {
	141	compatible = "st,stih407-rear-syscfg", "syscon";
	142	reg = <0x9290000 0x1000>;
	143	};
	144
	145	syscfg_flash: flash-syscfg@92a0000 {
	146	compatible = "st,stih407-flash-syscfg", "syscon";
	147	reg = <0x92a0000 0x1000>;
	148	};
	149
	150	syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
	151	compatible = "st,stih407-sbc-reg-syscfg", "syscon";
	152	reg = <0x9600000 0x1000>;
	153	};
	154
	155	syscfg_core: core-syscfg@92b0000 {
	156	compatible = "st,stih407-core-syscfg", "syscon";
	157	reg = <0x92b0000 0x1000>;
	158	};
	159
	160	syscfg_lpm: lpm-syscfg@94b5100 {
	161	compatible = "st,stih407-lpm-syscfg", "syscon";
	162	reg = <0x94b5100 0x1000>;
	163	};
	164
107dea0c LJ	165	irq-syscfg {
	166	compatible = "st,stih407-irq-syscfg";
	167	st,syscfg = <&syscfg_core>;
	168	st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
	169	<ST_IRQ_SYSCFG_PMU_1>;
	170	st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
	171	<ST_IRQ_SYSCFG_DISABLED>;
	172	};
	173
759742d1 MC	174	/* Display */
	175	vtg_main: sti-vtg-main@8d02800 {
	176	compatible = "st,vtg";
	177	reg = <0x8d02800 0x200>;
	178	interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
	179	};
	180
	181	vtg_aux: sti-vtg-aux@8d00200 {
	182	compatible = "st,vtg";
	183	reg = <0x8d00200 0x100>;
	184	interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
	185	};
	186
f563a571 MC	187	serial@9830000 {
	188	compatible = "st,asc";
	189	reg = <0x9830000 0x2c>;
	190	interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
	191	pinctrl-names = "default";
	192	pinctrl-0 = <&pinctrl_serial0>;
1befe7e4	193	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	194
	195	status = "disabled";
	196	};
	197
	198	serial@9831000 {
	199	compatible = "st,asc";
	200	reg = <0x9831000 0x2c>;
	201	interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
	202	pinctrl-names = "default";
	203	pinctrl-0 = <&pinctrl_serial1>;
1befe7e4	204	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	205
	206	status = "disabled";
	207	};
	208
	209	serial@9832000 {
	210	compatible = "st,asc";
	211	reg = <0x9832000 0x2c>;
	212	interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
	213	pinctrl-names = "default";
	214	pinctrl-0 = <&pinctrl_serial2>;
1befe7e4	215	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	216
	217	status = "disabled";
	218	};
	219
	220	/* SBC_ASC0 - UART10 */
	221	sbc_serial0: serial@9530000 {
	222	compatible = "st,asc";
	223	reg = <0x9530000 0x2c>;
	224	interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
	225	pinctrl-names = "default";
	226	pinctrl-0 = <&pinctrl_sbc_serial0>;
	227	clocks = <&clk_sysin>;
	228
	229	status = "disabled";
	230	};
	231
	232	serial@9531000 {
	233	compatible = "st,asc";
	234	reg = <0x9531000 0x2c>;
	235	interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
	236	pinctrl-names = "default";
	237	pinctrl-0 = <&pinctrl_sbc_serial1>;
	238	clocks = <&clk_sysin>;
	239
	240	status = "disabled";
	241	};
	242
	243	i2c@9840000 {
	244	compatible = "st,comms-ssc4-i2c";
	245	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	246	reg = <0x9840000 0x110>;
1befe7e4	247	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	248	clock-names = "ssc";
	249	clock-frequency = <400000>;
	250	pinctrl-names = "default";
	251	pinctrl-0 = <&pinctrl_i2c0_default>;
	252
	253	status = "disabled";
	254	};
	255
	256	i2c@9841000 {
	257	compatible = "st,comms-ssc4-i2c";
	258	reg = <0x9841000 0x110>;
	259	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	260	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	261	clock-names = "ssc";
	262	clock-frequency = <400000>;
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&pinctrl_i2c1_default>;
	265
	266	status = "disabled";
	267	};
	268
	269	i2c@9842000 {
	270	compatible = "st,comms-ssc4-i2c";
	271	reg = <0x9842000 0x110>;
	272	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	273	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	274	clock-names = "ssc";
	275	clock-frequency = <400000>;
	276	pinctrl-names = "default";
	277	pinctrl-0 = <&pinctrl_i2c2_default>;
	278
	279	status = "disabled";
	280	};
	281
	282	i2c@9843000 {
	283	compatible = "st,comms-ssc4-i2c";
	284	reg = <0x9843000 0x110>;
	285	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	286	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	287	clock-names = "ssc";
	288	clock-frequency = <400000>;
	289	pinctrl-names = "default";
	290	pinctrl-0 = <&pinctrl_i2c3_default>;
	291
	292	status = "disabled";
	293	};
	294
	295	i2c@9844000 {
	296	compatible = "st,comms-ssc4-i2c";
	297	reg = <0x9844000 0x110>;
	298	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	299	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	300	clock-names = "ssc";
	301	clock-frequency = <400000>;
	302	pinctrl-names = "default";
	303	pinctrl-0 = <&pinctrl_i2c4_default>;
	304
	305	status = "disabled";
	306	};
	307
	308	i2c@9845000 {
	309	compatible = "st,comms-ssc4-i2c";
	310	reg = <0x9845000 0x110>;
	311	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4	312	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571 MC	313	clock-names = "ssc";
	314	clock-frequency = <400000>;
	315	pinctrl-names = "default";
	316	pinctrl-0 = <&pinctrl_i2c5_default>;
	317
	318	status = "disabled";
	319	};
	320
	321
	322	/* SSCs on SBC */
	323	i2c@9540000 {
	324	compatible = "st,comms-ssc4-i2c";
	325	reg = <0x9540000 0x110>;
	326	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	327	clocks = <&clk_sysin>;
	328	clock-names = "ssc";
	329	clock-frequency = <400000>;
	330	pinctrl-names = "default";
	331	pinctrl-0 = <&pinctrl_i2c10_default>;
	332
	333	status = "disabled";
	334	};
	335
	336	i2c@9541000 {
	337	compatible = "st,comms-ssc4-i2c";
	338	reg = <0x9541000 0x110>;
	339	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	340	clocks = <&clk_sysin>;
	341	clock-names = "ssc";
	342	clock-frequency = <400000>;
	343	pinctrl-names = "default";
	344	pinctrl-0 = <&pinctrl_i2c11_default>;
	345
	346	status = "disabled";
	347	};
8facce13 PG	348
	349	usb2_picophy0: phy1 {
	350	compatible = "st,stih407-usb2-phy";
	351	#phy-cells = <0>;
	352	st,syscfg = <&syscfg_core 0x100 0xf4>;
	353	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
743ac9d2	354	<&picophyreset STIH407_PICOPHY2_RESET>;
8facce13 PG	355	reset-names = "global", "port";
8facce13 PG	356	};
b26373c0 GF	357
	358	miphy28lp_phy: miphy28lp@9b22000 {
	359	compatible = "st,miphy28lp-phy";
	360	st,syscfg = <&syscfg_core>;
	361	#address-cells = <1>;
	362	#size-cells = <1>;
	363	ranges;
	364
	365	phy_port0: port@9b22000 {
	366	reg = <0x9b22000 0xff>,
	367	<0x9b09000 0xff>,
	368	<0x9b04000 0xff>;
	369	reg-names = "sata-up",
	370	"pcie-up",
	371	"pipew";
	372
	373	st,syscfg = <0x114 0x818 0xe0 0xec>;
	374	#phy-cells = <1>;
	375
	376	reset-names = "miphy-sw-rst";
	377	resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
	378	};
	379
	380	phy_port1: port@9b2a000 {
	381	reg = <0x9b2a000 0xff>,
	382	<0x9b19000 0xff>,
	383	<0x9b14000 0xff>;
	384	reg-names = "sata-up",
	385	"pcie-up",
	386	"pipew";
	387
	388	st,syscfg = <0x118 0x81c 0xe4 0xf0>;
	389
	390	#phy-cells = <1>;
	391
	392	reset-names = "miphy-sw-rst";
	393	resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
	394	};
	395
	396	phy_port2: port@8f95000 {
	397	reg = <0x8f95000 0xff>,
	398	<0x8f90000 0xff>;
	399	reg-names = "pipew",
	400	"usb3-up";
	401
	402	st,syscfg = <0x11c 0x820>;
	403
	404	#phy-cells = <1>;
	405
	406	reset-names = "miphy-sw-rst";
	407	resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
	408	};
	409	};
2c53c272 LJ	410
	411	spi@9840000 {
	412	compatible = "st,comms-ssc4-spi";
	413	reg = <0x9840000 0x110>;
	414	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	415	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	416	clock-names = "ssc";
	417	pinctrl-0 = <&pinctrl_spi0_default>;
	418	pinctrl-names = "default";
	419	#address-cells = <1>;
	420	#size-cells = <0>;
	421
	422	status = "disabled";
	423	};
	424
	425	spi@9841000 {
	426	compatible = "st,comms-ssc4-spi";
	427	reg = <0x9841000 0x110>;
	428	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	429	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	430	clock-names = "ssc";
55fd9b18 PG	431	pinctrl-names = "default";
55fd9b18 PG	432	pinctrl-0 = <&pinctrl_spi1_default>;
2c53c272 LJ	433
	434	status = "disabled";
	435	};
	436
	437	spi@9842000 {
	438	compatible = "st,comms-ssc4-spi";
	439	reg = <0x9842000 0x110>;
	440	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	441	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	442	clock-names = "ssc";
55fd9b18 PG	443	pinctrl-names = "default";
55fd9b18 PG	444	pinctrl-0 = <&pinctrl_spi2_default>;
2c53c272 LJ	445
	446	status = "disabled";
	447	};
	448
	449	spi@9843000 {
	450	compatible = "st,comms-ssc4-spi";
	451	reg = <0x9843000 0x110>;
	452	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	453	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	454	clock-names = "ssc";
55fd9b18 PG	455	pinctrl-names = "default";
55fd9b18 PG	456	pinctrl-0 = <&pinctrl_spi3_default>;
2c53c272 LJ	457
	458	status = "disabled";
	459	};
	460
	461	spi@9844000 {
	462	compatible = "st,comms-ssc4-spi";
	463	reg = <0x9844000 0x110>;
	464	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	465	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
	466	clock-names = "ssc";
55fd9b18 PG	467	pinctrl-names = "default";
55fd9b18 PG	468	pinctrl-0 = <&pinctrl_spi4_default>;
2c53c272 LJ	469
	470	status = "disabled";
	471	};
b0bb2bae LJ	472
	473	/* SBC SSC */
	474	spi@9540000 {
	475	compatible = "st,comms-ssc4-spi";
	476	reg = <0x9540000 0x110>;
	477	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	478	clocks = <&clk_sysin>;
	479	clock-names = "ssc";
55fd9b18 PG	480	pinctrl-names = "default";
55fd9b18 PG	481	pinctrl-0 = <&pinctrl_spi10_default>;
b0bb2bae LJ	482
	483	status = "disabled";
	484	};
	485
	486	spi@9541000 {
	487	compatible = "st,comms-ssc4-spi";
	488	reg = <0x9541000 0x110>;
	489	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	490	clocks = <&clk_sysin>;
	491	clock-names = "ssc";
55fd9b18 PG	492	pinctrl-names = "default";
55fd9b18 PG	493	pinctrl-0 = <&pinctrl_spi11_default>;
b0bb2bae LJ	494
	495	status = "disabled";
	496	};
	497
	498	spi@9542000 {
	499	compatible = "st,comms-ssc4-spi";
	500	reg = <0x9542000 0x110>;
	501	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	502	clocks = <&clk_sysin>;
	503	clock-names = "ssc";
55fd9b18 PG	504	pinctrl-names = "default";
55fd9b18 PG	505	pinctrl-0 = <&pinctrl_spi12_default>;
b0bb2bae LJ	506
	507	status = "disabled";
	508	};
9286ac48 PG	509
	510	mmc0: sdhci@09060000 {
	511	compatible = "st,sdhci-stih407", "st,sdhci";
	512	status = "disabled";
	513	reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
	514	reg-names = "mmc", "top-mmc-delay";
	515	interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
	516	interrupt-names = "mmcirq";
	517	pinctrl-names = "default";
	518	pinctrl-0 = <&pinctrl_mmc0>;
	519	clock-names = "mmc";
	520	clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
	521	bus-width = <8>;
	522	non-removable;
	523	};
	524
	525	mmc1: sdhci@09080000 {
	526	compatible = "st,sdhci-stih407", "st,sdhci";
	527	status = "disabled";
	528	reg = <0x09080000 0x7ff>;
	529	reg-names = "mmc";
	530	interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
	531	interrupt-names = "mmcirq";
	532	pinctrl-names = "default";
	533	pinctrl-0 = <&pinctrl_sd1>;
	534	clock-names = "mmc";
	535	clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
	536	resets = <&softreset STIH407_MMC1_SOFTRESET>;
	537	bus-width = <4>;
	538	};
358764f3 LJ	539
	540	/* Watchdog and Real-Time Clock */
	541	lpc@8787000 {
	542	compatible = "st,stih407-lpc";
	543	reg = <0x8787000 0x1000>;
	544	interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
	545	clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
	546	timeout-sec = <120>;
	547	st,syscfg = <&syscfg_core>;
	548	st,lpc-mode = <ST_LPC_MODE_WDT>;
	549	};
	550
	551	lpc@8788000 {
	552	compatible = "st,stih407-lpc";
	553	reg = <0x8788000 0x1000>;
	554	interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
	555	clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
	556	st,lpc-mode = <ST_LPC_MODE_RTC>;
	557	};
b3d37f92 PG	558
	559	sata0: sata@9b20000 {
	560	compatible = "st,ahci";
	561	reg = <0x9b20000 0x1000>;
	562
	563	interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
	564	interrupt-names = "hostc";
	565
	566	phys = <&phy_port0 PHY_TYPE_SATA>;
	567	phy-names = "ahci_phy";
	568
	569	resets = <&powerdown STIH407_SATA0_POWERDOWN>,
	570	<&softreset STIH407_SATA0_SOFTRESET>,
	571	<&softreset STIH407_SATA0_PWR_SOFTRESET>;
	572	reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
	573
	574	clock-names = "ahci_clk";
	575	clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
	576
	577	status = "disabled";
	578	};
	579
	580	sata1: sata@9b28000 {
	581	compatible = "st,ahci";
	582	reg = <0x9b28000 0x1000>;
	583
	584	interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
	585	interrupt-names = "hostc";
	586
	587	phys = <&phy_port1 PHY_TYPE_SATA>;
	588	phy-names = "ahci_phy";
	589
	590	resets = <&powerdown STIH407_SATA1_POWERDOWN>,
	591	<&softreset STIH407_SATA1_SOFTRESET>,
	592	<&softreset STIH407_SATA1_PWR_SOFTRESET>;
	593	reset-names = "pwr-dwn",
	594	"sw-rst",
	595	"pwr-rst";
	596
	597	clock-names = "ahci_clk";
	598	clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
	599
	600	status = "disabled";
	601	};
fd555998	602
cd9f59ca	603
fd555998 PG	604	st_dwc3: dwc3@8f94000 {
	605	compatible = "st,stih407-dwc3";
	606	reg = <0x08f94000 0x1000>, <0x110 0x4>;
	607	reg-names = "reg-glue", "syscfg-reg";
	608	st,syscfg = <&syscfg_core>;
	609	resets = <&powerdown STIH407_USB3_POWERDOWN>,
	610	<&softreset STIH407_MIPHY2_SOFTRESET>;
	611	reset-names = "powerdown", "softreset";
	612	#address-cells = <1>;
	613	#size-cells = <1>;
	614	pinctrl-names = "default";
	615	pinctrl-0 = <&pinctrl_usb3>;
	616	ranges;
	617
	618	status = "disabled";
	619
	620	dwc3: dwc3@9900000 {
	621	compatible = "snps,dwc3";
	622	reg = <0x09900000 0x100000>;
	623	interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
	624	dr_mode = "host";
	625	phy-names = "usb2-phy", "usb3-phy";
	626	phys = <&usb2_picophy0>,
	627	<&phy_port2 PHY_TYPE_USB3>;
	628	};
	629	};
cd9f59ca LJ	630
	631	/* COMMS PWM Module */
	632	pwm0: pwm@9810000 {
	633	compatible = "st,sti-pwm";
cd9f59ca LJ	634	#pwm-cells = <2>;
	635	reg = <0x9810000 0x68>;
	636	pinctrl-names = "default";
	637	pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
	638	clock-names = "pwm";
	639	clocks = <&clk_sysin>;
	640	st,pwm-num-chan = <1>;
8aa5f09d MC	641
8aa5f09d MC	642	status = "disabled";
cd9f59ca LJ	643	};
	644
	645	/* SBC PWM Module */
	646	pwm1: pwm@9510000 {
	647	compatible = "st,sti-pwm";
cd9f59ca LJ	648	#pwm-cells = <2>;
	649	reg = <0x9510000 0x68>;
	650	pinctrl-names = "default";
	651	pinctrl-0 = <&pinctrl_pwm1_chan0_default
	652	&pinctrl_pwm1_chan1_default
	653	&pinctrl_pwm1_chan2_default
	654	&pinctrl_pwm1_chan3_default>;
	655	clock-names = "pwm";
	656	clocks = <&clk_sysin>;
	657	st,pwm-num-chan = <4>;
8aa5f09d MC	658
8aa5f09d MC	659	status = "disabled";
cd9f59ca	660	};
cae010a1 LJ	661
	662	rng10: rng@08a89000 {
	663	compatible = "st,rng";
	664	reg = <0x08a89000 0x1000>;
	665	clocks = <&clk_sysin>;
	666	status = "okay";
	667	};
	668
	669	rng11: rng@08a8a000 {
	670	compatible = "st,rng";
	671	reg = <0x08a8a000 0x1000>;
	672	clocks = <&clk_sysin>;
	673	status = "okay";
	674	};
ab511d7d MC	675
	676	ethernet0: dwmac@9630000 {
	677	device_type = "network";
	678	status = "disabled";
	679	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
	680	reg = <0x9630000 0x8000>, <0x80 0x4>;
	681	reg-names = "stmmaceth", "sti-ethconf";
	682
	683	st,syscon = <&syscfg_sbc_reg 0x80>;
	684	st,gmac_en;
	685	resets = <&softreset STIH407_ETH1_SOFTRESET>;
	686	reset-names = "stmmaceth";
	687
	688	interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
	689	<GIC_SPI 99 IRQ_TYPE_NONE>;
	690	interrupt-names = "macirq", "eth_wake_irq";
	691
	692	/* DMA Bus Mode */
	693	snps,pbl = <8>;
	694
	695	pinctrl-names = "default";
	696	pinctrl-0 = <&pinctrl_rgmii1>;
	697
	698	clock-names = "stmmaceth", "sti-ethclk";
	699	clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
	700	<&clk_s_c0_flexgen CLK_ETH_PHY>;
cd9f59ca	701	};
ba25d8b4 LJ	702
	703	rng10: rng@08a89000 {
	704	compatible = "st,rng";
	705	reg = <0x08a89000 0x1000>;
	706	clocks = <&clk_sysin>;
	707	status = "okay";
	708	};
	709
	710	rng11: rng@08a8a000 {
	711	compatible = "st,rng";
	712	reg = <0x08a8a000 0x1000>;
	713	clocks = <&clk_sysin>;
	714	status = "okay";
	715	};
f563a571 MC	716	};
f563a571 MC	717	};