projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| f563a571 MC |
1 | /* |
| 2 | * Copyright (C) 2014 STMicroelectronics Limited. | |
| 3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * publishhed by the Free Software Foundation. | |
| 8 | */ | |
| 9 | #include "st-pincfg.h" | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 11 | / { | |
| 12 | ||
| 13 | aliases { | |
| 14 | /* 0-5: PIO_SBC */ | |
| 15 | gpio0 = &pio0; | |
| 16 | gpio1 = &pio1; | |
| 17 | gpio2 = &pio2; | |
| 18 | gpio3 = &pio3; | |
| 19 | gpio4 = &pio4; | |
| 20 | gpio5 = &pio5; | |
| 21 | /* 10-19: PIO_FRONT0 */ | |
| 22 | gpio6 = &pio10; | |
| 23 | gpio7 = &pio11; | |
| 24 | gpio8 = &pio12; | |
| 25 | gpio9 = &pio13; | |
| 26 | gpio10 = &pio14; | |
| 27 | gpio11 = &pio15; | |
| 28 | gpio12 = &pio16; | |
| 29 | gpio13 = &pio17; | |
| 30 | gpio14 = &pio18; | |
| 31 | gpio15 = &pio19; | |
| 32 | /* 20: PIO_FRONT1 */ | |
| 33 | gpio16 = &pio20; | |
| 34 | /* 30-35: PIO_REAR */ | |
| 35 | gpio17 = &pio30; | |
| 36 | gpio18 = &pio31; | |
| 37 | gpio19 = &pio32; | |
| 38 | gpio20 = &pio33; | |
| 39 | gpio21 = &pio34; | |
| 40 | gpio22 = &pio35; | |
| 41 | /* 40-42: PIO_FLASH */ | |
| 42 | gpio23 = &pio40; | |
| 43 | gpio24 = &pio41; | |
| 44 | gpio25 = &pio42; | |
| 45 | }; | |
| 46 | ||
| 47 | soc { | |
| 48 | pin-controller-sbc { | |
| 49 | #address-cells = <1>; | |
| 50 | #size-cells = <1>; | |
| 51 | compatible = "st,stih407-sbc-pinctrl"; | |
| 52 | st,syscfg = <&syscfg_sbc>; | |
| 53 | reg = <0x0961f080 0x4>; | |
| 54 | reg-names = "irqmux"; | |
| 55 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
| 2bb1441f | 56 | interrupt-names = "irqmux"; |
| f563a571 MC |
57 | ranges = <0 0x09610000 0x6000>; |
| 58 | ||
| 59 | pio0: gpio@09610000 { | |
| 60 | gpio-controller; | |
| 4e6ee336 | 61 | #gpio-cells = <2>; |
| f563a571 MC |
62 | interrupt-controller; |
| 63 | #interrupt-cells = <2>; | |
| 64 | reg = <0x0 0x100>; | |
| 65 | st,bank-name = "PIO0"; | |
| 66 | }; | |
| 67 | pio1: gpio@09611000 { | |
| 68 | gpio-controller; | |
| 4e6ee336 | 69 | #gpio-cells = <2>; |
| f563a571 MC |
70 | interrupt-controller; |
| 71 | #interrupt-cells = <2>; | |
| 72 | reg = <0x1000 0x100>; | |
| 73 | st,bank-name = "PIO1"; | |
| 74 | }; | |
| 75 | pio2: gpio@09612000 { | |
| 76 | gpio-controller; | |
| 4e6ee336 | 77 | #gpio-cells = <2>; |
| f563a571 MC |
78 | interrupt-controller; |
| 79 | #interrupt-cells = <2>; | |
| 80 | reg = <0x2000 0x100>; | |
| 81 | st,bank-name = "PIO2"; | |
| 82 | }; | |
| 83 | pio3: gpio@09613000 { | |
| 84 | gpio-controller; | |
| 4e6ee336 | 85 | #gpio-cells = <2>; |
| f563a571 MC |
86 | interrupt-controller; |
| 87 | #interrupt-cells = <2>; | |
| 88 | reg = <0x3000 0x100>; | |
| 89 | st,bank-name = "PIO3"; | |
| 90 | }; | |
| 91 | pio4: gpio@09614000 { | |
| 92 | gpio-controller; | |
| 4e6ee336 | 93 | #gpio-cells = <2>; |
| f563a571 MC |
94 | interrupt-controller; |
| 95 | #interrupt-cells = <2>; | |
| 96 | reg = <0x4000 0x100>; | |
| 97 | st,bank-name = "PIO4"; | |
| 98 | }; | |
| 99 | ||
| 100 | pio5: gpio@09615000 { | |
| 101 | gpio-controller; | |
| 4e6ee336 | 102 | #gpio-cells = <2>; |
| f563a571 MC |
103 | interrupt-controller; |
| 104 | #interrupt-cells = <2>; | |
| 105 | reg = <0x5000 0x100>; | |
| 106 | st,bank-name = "PIO5"; | |
| d90accb9 | 107 | st,retime-pin-mask = <0x3f>; |
| f563a571 MC |
108 | }; |
| 109 | ||
| 0f38d5ad PG |
110 | cec0 { |
| 111 | pinctrl_cec0_default: cec0-default { | |
| 112 | st,pins { | |
| 113 | hdmi_cec = <&pio2 4 ALT1 BIDIR>; | |
| 114 | }; | |
| 115 | }; | |
| 116 | }; | |
| 117 | ||
| f563a571 MC |
118 | rc { |
| 119 | pinctrl_ir: ir0 { | |
| 120 | st,pins { | |
| 121 | ir = <&pio4 0 ALT2 IN>; | |
| 122 | }; | |
| 123 | }; | |
| 0252d863 PG |
124 | |
| 125 | pinctrl_uhf: uhf0 { | |
| 126 | st,pins { | |
| 127 | ir = <&pio4 1 ALT2 IN>; | |
| 128 | }; | |
| 129 | }; | |
| 130 | ||
| 131 | pinctrl_tx: tx0 { | |
| 132 | st,pins { | |
| 133 | tx = <&pio4 2 ALT2 OUT>; | |
| 134 | }; | |
| 135 | }; | |
| 136 | ||
| 137 | pinctrl_tx_od: tx_od0 { | |
| 138 | st,pins { | |
| 139 | tx_od = <&pio4 3 ALT2 OUT>; | |
| 140 | }; | |
| 141 | }; | |
| f563a571 MC |
142 | }; |
| 143 | ||
| 144 | /* SBC_ASC0 - UART10 */ | |
| 145 | sbc_serial0 { | |
| 146 | pinctrl_sbc_serial0: sbc_serial0-0 { | |
| 147 | st,pins { | |
| 148 | tx = <&pio3 4 ALT1 OUT>; | |
| 149 | rx = <&pio3 5 ALT1 IN>; | |
| 150 | }; | |
| 151 | }; | |
| 152 | }; | |
| 153 | /* SBC_ASC1 - UART11 */ | |
| 154 | sbc_serial1 { | |
| 155 | pinctrl_sbc_serial1: sbc_serial1-0 { | |
| 156 | st,pins { | |
| 157 | tx = <&pio2 6 ALT3 OUT>; | |
| 158 | rx = <&pio2 7 ALT3 IN>; | |
| 159 | }; | |
| 160 | }; | |
| 161 | }; | |
| 162 | ||
| 163 | i2c10 { | |
| 164 | pinctrl_i2c10_default: i2c10-default { | |
| 165 | st,pins { | |
| 166 | sda = <&pio4 6 ALT1 BIDIR>; | |
| 167 | scl = <&pio4 5 ALT1 BIDIR>; | |
| 168 | }; | |
| 169 | }; | |
| 170 | }; | |
| 171 | ||
| 172 | i2c11 { | |
| 173 | pinctrl_i2c11_default: i2c11-default { | |
| 174 | st,pins { | |
| 175 | sda = <&pio5 1 ALT1 BIDIR>; | |
| 176 | scl = <&pio5 0 ALT1 BIDIR>; | |
| 177 | }; | |
| 178 | }; | |
| 179 | }; | |
| 180 | ||
| 181 | keyscan { | |
| 182 | pinctrl_keyscan: keyscan { | |
| 183 | st,pins { | |
| 184 | keyin0 = <&pio4 0 ALT6 IN>; | |
| 185 | keyin1 = <&pio4 5 ALT4 IN>; | |
| 186 | keyin2 = <&pio0 4 ALT2 IN>; | |
| 187 | keyin3 = <&pio2 6 ALT2 IN>; | |
| 188 | ||
| 189 | keyout0 = <&pio4 6 ALT4 OUT>; | |
| 190 | keyout1 = <&pio1 7 ALT2 OUT>; | |
| 191 | keyout2 = <&pio0 6 ALT2 OUT>; | |
| 192 | keyout3 = <&pio2 7 ALT2 OUT>; | |
| 193 | }; | |
| 194 | }; | |
| 195 | }; | |
| 196 | ||
| 197 | gmac1 { | |
| 198 | /* | |
| 199 | * Almost all the boards based on STiH407 SoC have an embedded | |
| 200 | * switch where the mdio/mdc have been used for managing the SMI | |
| 201 | * iface via I2C. For this reason these lines can be allocated | |
| 202 | * by using dedicated configuration (in case of there will be a | |
| 203 | * standard PHY transceiver on-board). | |
| 204 | */ | |
| 205 | pinctrl_rgmii1: rgmii1-0 { | |
| 206 | st,pins { | |
| 207 | ||
| 208 | txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; | |
| 209 | txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; | |
| 210 | txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; | |
| 211 | txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; | |
| 212 | txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; | |
| 213 | txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; | |
| 214 | rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; | |
| 215 | rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; | |
| 216 | rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; | |
| 217 | rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; | |
| 218 | rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; | |
| b89c429c | 219 | rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; |
| f563a571 | 220 | clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; |
| b89c429c | 221 | phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; |
| f563a571 MC |
222 | }; |
| 223 | }; | |
| 224 | ||
| 225 | pinctrl_rgmii1_mdio: rgmii1-mdio { | |
| 226 | st,pins { | |
| 227 | mdio = <&pio1 0 ALT1 OUT BYPASS 0>; | |
| 228 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | |
| 229 | mdint = <&pio1 3 ALT1 IN BYPASS 0>; | |
| 230 | }; | |
| 231 | }; | |
| 232 | ||
| c3df8e21 PC |
233 | pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { |
| 234 | st,pins { | |
| 235 | mdio = <&pio1 0 ALT1 OUT BYPASS 0>; | |
| 236 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | |
| 237 | }; | |
| 238 | }; | |
| 239 | ||
| f563a571 MC |
240 | pinctrl_mii1: mii1 { |
| 241 | st,pins { | |
| 242 | txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 243 | txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 244 | txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 245 | txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 246 | txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 247 | txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 248 | txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; | |
| 249 | col = <&pio0 7 ALT1 IN BYPASS 1000>; | |
| 250 | ||
| 251 | mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; | |
| 252 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | |
| 253 | crs = <&pio1 2 ALT1 IN BYPASS 1000>; | |
| 254 | mdint = <&pio1 3 ALT1 IN BYPASS 0>; | |
| 255 | rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 256 | rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 257 | rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 258 | rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 259 | ||
| 260 | rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 261 | rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 262 | rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; | |
| 263 | phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; | |
| 264 | }; | |
| 265 | }; | |
| 9d6d736b PG |
266 | |
| 267 | pinctrl_rmii1: rmii1-0 { | |
| 268 | st,pins { | |
| 269 | txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 270 | txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 271 | txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 272 | mdio = <&pio1 0 ALT1 OUT BYPASS 0>; | |
| 273 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | |
| 274 | mdint = <&pio1 3 ALT1 IN BYPASS 0>; | |
| 275 | rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; | |
| 276 | rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; | |
| 277 | rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; | |
| 278 | rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 279 | }; | |
| 280 | }; | |
| 281 | ||
| 282 | pinctrl_rmii1_phyclk: rmii1_phyclk { | |
| 283 | st,pins { | |
| 284 | phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; | |
| 285 | }; | |
| 286 | }; | |
| 287 | ||
| 288 | pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { | |
| 289 | st,pins { | |
| 290 | phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; | |
| 291 | }; | |
| 292 | }; | |
| f563a571 MC |
293 | }; |
| 294 | ||
| 295 | pwm1 { | |
| 296 | pinctrl_pwm1_chan0_default: pwm1-0-default { | |
| 297 | st,pins { | |
| 298 | pwm-out = <&pio3 0 ALT1 OUT>; | |
| 30a2366c | 299 | pwm-capturein = <&pio3 2 ALT1 IN>; |
| f563a571 MC |
300 | }; |
| 301 | }; | |
| 302 | pinctrl_pwm1_chan1_default: pwm1-1-default { | |
| 303 | st,pins { | |
| 30a2366c | 304 | pwm-capturein = <&pio4 3 ALT1 IN>; |
| f563a571 MC |
305 | pwm-out = <&pio4 4 ALT1 OUT>; |
| 306 | }; | |
| 307 | }; | |
| 308 | pinctrl_pwm1_chan2_default: pwm1-2-default { | |
| 309 | st,pins { | |
| 310 | pwm-out = <&pio4 6 ALT3 OUT>; | |
| 311 | }; | |
| 312 | }; | |
| 313 | pinctrl_pwm1_chan3_default: pwm1-3-default { | |
| 314 | st,pins { | |
| 315 | pwm-out = <&pio4 7 ALT3 OUT>; | |
| 316 | }; | |
| 317 | }; | |
| 318 | }; | |
| 193bb623 PG |
319 | |
| 320 | spi10 { | |
| 321 | pinctrl_spi10_default: spi10-4w-alt1-0 { | |
| 322 | st,pins { | |
| 323 | mtsr = <&pio4 6 ALT1 OUT>; | |
| 324 | mrst = <&pio4 7 ALT1 IN>; | |
| 325 | scl = <&pio4 5 ALT1 OUT>; | |
| 326 | }; | |
| 327 | }; | |
| 328 | ||
| 329 | pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { | |
| 330 | st,pins { | |
| 331 | mtsr = <&pio4 6 ALT1 BIDIR_PU>; | |
| 332 | scl = <&pio4 5 ALT1 OUT>; | |
| 333 | }; | |
| 334 | }; | |
| 335 | }; | |
| 336 | ||
| 337 | spi11 { | |
| 338 | pinctrl_spi11_default: spi11-4w-alt2-0 { | |
| 339 | st,pins { | |
| 340 | mtsr = <&pio3 1 ALT2 OUT>; | |
| 341 | mrst = <&pio3 0 ALT2 IN>; | |
| 342 | scl = <&pio3 2 ALT2 OUT>; | |
| 343 | }; | |
| 344 | }; | |
| 345 | ||
| 346 | pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { | |
| 347 | st,pins { | |
| 348 | mtsr = <&pio3 1 ALT2 BIDIR_PU>; | |
| 349 | scl = <&pio3 2 ALT2 OUT>; | |
| 350 | }; | |
| 351 | }; | |
| 352 | }; | |
| 353 | ||
| 354 | spi12 { | |
| 355 | pinctrl_spi12_default: spi12-4w-alt2-0 { | |
| 356 | st,pins { | |
| 357 | mtsr = <&pio3 6 ALT2 OUT>; | |
| 358 | mrst = <&pio3 4 ALT2 IN>; | |
| 359 | scl = <&pio3 7 ALT2 OUT>; | |
| 360 | }; | |
| 361 | }; | |
| 362 | ||
| 363 | pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { | |
| 364 | st,pins { | |
| 365 | mtsr = <&pio3 6 ALT2 BIDIR_PU>; | |
| 366 | scl = <&pio3 7 ALT2 OUT>; | |
| 367 | }; | |
| 368 | }; | |
| 369 | }; | |
| f563a571 MC |
370 | }; |
| 371 | ||
| 372 | pin-controller-front0 { | |
| 373 | #address-cells = <1>; | |
| 374 | #size-cells = <1>; | |
| 375 | compatible = "st,stih407-front-pinctrl"; | |
| 376 | st,syscfg = <&syscfg_front>; | |
| 377 | reg = <0x0920f080 0x4>; | |
| 378 | reg-names = "irqmux"; | |
| 379 | interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>; | |
| 2bb1441f | 380 | interrupt-names = "irqmux"; |
| f563a571 MC |
381 | ranges = <0 0x09200000 0x10000>; |
| 382 | ||
| 383 | pio10: pio@09200000 { | |
| 384 | gpio-controller; | |
| 4e6ee336 | 385 | #gpio-cells = <2>; |
| f563a571 MC |
386 | interrupt-controller; |
| 387 | #interrupt-cells = <2>; | |
| 388 | reg = <0x0 0x100>; | |
| 389 | st,bank-name = "PIO10"; | |
| 390 | }; | |
| 391 | pio11: pio@09201000 { | |
| 392 | gpio-controller; | |
| 4e6ee336 | 393 | #gpio-cells = <2>; |
| f563a571 MC |
394 | interrupt-controller; |
| 395 | #interrupt-cells = <2>; | |
| 396 | reg = <0x1000 0x100>; | |
| 397 | st,bank-name = "PIO11"; | |
| 398 | }; | |
| 399 | pio12: pio@09202000 { | |
| 400 | gpio-controller; | |
| 4e6ee336 | 401 | #gpio-cells = <2>; |
| f563a571 MC |
402 | interrupt-controller; |
| 403 | #interrupt-cells = <2>; | |
| 404 | reg = <0x2000 0x100>; | |
| 405 | st,bank-name = "PIO12"; | |
| 406 | }; | |
| 407 | pio13: pio@09203000 { | |
| 408 | gpio-controller; | |
| 4e6ee336 | 409 | #gpio-cells = <2>; |
| f563a571 MC |
410 | interrupt-controller; |
| 411 | #interrupt-cells = <2>; | |
| 412 | reg = <0x3000 0x100>; | |
| 413 | st,bank-name = "PIO13"; | |
| 414 | }; | |
| 415 | pio14: pio@09204000 { | |
| 416 | gpio-controller; | |
| 4e6ee336 | 417 | #gpio-cells = <2>; |
| f563a571 MC |
418 | interrupt-controller; |
| 419 | #interrupt-cells = <2>; | |
| 420 | reg = <0x4000 0x100>; | |
| 421 | st,bank-name = "PIO14"; | |
| 422 | }; | |
| 423 | pio15: pio@09205000 { | |
| 424 | gpio-controller; | |
| 4e6ee336 | 425 | #gpio-cells = <2>; |
| f563a571 MC |
426 | interrupt-controller; |
| 427 | #interrupt-cells = <2>; | |
| 428 | reg = <0x5000 0x100>; | |
| 429 | st,bank-name = "PIO15"; | |
| 430 | }; | |
| 431 | pio16: pio@09206000 { | |
| 432 | gpio-controller; | |
| 4e6ee336 | 433 | #gpio-cells = <2>; |
| f563a571 MC |
434 | interrupt-controller; |
| 435 | #interrupt-cells = <2>; | |
| 436 | reg = <0x6000 0x100>; | |
| 437 | st,bank-name = "PIO16"; | |
| 438 | }; | |
| 439 | pio17: pio@09207000 { | |
| 440 | gpio-controller; | |
| 4e6ee336 | 441 | #gpio-cells = <2>; |
| f563a571 MC |
442 | interrupt-controller; |
| 443 | #interrupt-cells = <2>; | |
| 444 | reg = <0x7000 0x100>; | |
| 445 | st,bank-name = "PIO17"; | |
| 446 | }; | |
| 447 | pio18: pio@09208000 { | |
| 448 | gpio-controller; | |
| 4e6ee336 | 449 | #gpio-cells = <2>; |
| f563a571 MC |
450 | interrupt-controller; |
| 451 | #interrupt-cells = <2>; | |
| 452 | reg = <0x8000 0x100>; | |
| 453 | st,bank-name = "PIO18"; | |
| 454 | }; | |
| 455 | pio19: pio@09209000 { | |
| 456 | gpio-controller; | |
| 4e6ee336 | 457 | #gpio-cells = <2>; |
| f563a571 MC |
458 | interrupt-controller; |
| 459 | #interrupt-cells = <2>; | |
| 460 | reg = <0x9000 0x100>; | |
| 461 | st,bank-name = "PIO19"; | |
| 462 | }; | |
| 463 | ||
| 464 | /* Comms */ | |
| 465 | serial0 { | |
| 466 | pinctrl_serial0: serial0-0 { | |
| 467 | st,pins { | |
| 468 | tx = <&pio17 0 ALT1 OUT>; | |
| 469 | rx = <&pio17 1 ALT1 IN>; | |
| 470 | }; | |
| 471 | }; | |
| 472 | }; | |
| 473 | ||
| 474 | serial1 { | |
| 475 | pinctrl_serial1: serial1-0 { | |
| 476 | st,pins { | |
| 477 | tx = <&pio16 0 ALT1 OUT>; | |
| 478 | rx = <&pio16 1 ALT1 IN>; | |
| 479 | }; | |
| 480 | }; | |
| 481 | }; | |
| 482 | ||
| 483 | serial2 { | |
| 484 | pinctrl_serial2: serial2-0 { | |
| 485 | st,pins { | |
| 486 | tx = <&pio15 0 ALT1 OUT>; | |
| 487 | rx = <&pio15 1 ALT1 IN>; | |
| 488 | }; | |
| 489 | }; | |
| 490 | }; | |
| 491 | ||
| 492 | mmc1 { | |
| 493 | pinctrl_sd1: sd1-0 { | |
| 494 | st,pins { | |
| 495 | sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; | |
| 496 | sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; | |
| 497 | sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; | |
| 498 | sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; | |
| 499 | sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; | |
| 500 | sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; | |
| 501 | sd_led = <&pio16 6 ALT6 OUT>; | |
| 502 | sd_pwren = <&pio16 7 ALT6 OUT>; | |
| 503 | sd_cd = <&pio19 0 ALT6 IN>; | |
| 504 | sd_wp = <&pio19 1 ALT6 IN>; | |
| 505 | }; | |
| 506 | }; | |
| 507 | }; | |
| 508 | ||
| 509 | ||
| 510 | i2c0 { | |
| 511 | pinctrl_i2c0_default: i2c0-default { | |
| 512 | st,pins { | |
| 513 | sda = <&pio10 6 ALT2 BIDIR>; | |
| 514 | scl = <&pio10 5 ALT2 BIDIR>; | |
| 515 | }; | |
| 516 | }; | |
| 517 | }; | |
| 518 | ||
| 519 | i2c1 { | |
| 520 | pinctrl_i2c1_default: i2c1-default { | |
| 521 | st,pins { | |
| 522 | sda = <&pio11 1 ALT2 BIDIR>; | |
| 523 | scl = <&pio11 0 ALT2 BIDIR>; | |
| 524 | }; | |
| 525 | }; | |
| 526 | }; | |
| 527 | ||
| 528 | i2c2 { | |
| 529 | pinctrl_i2c2_default: i2c2-default { | |
| 530 | st,pins { | |
| 531 | sda = <&pio15 6 ALT2 BIDIR>; | |
| 532 | scl = <&pio15 5 ALT2 BIDIR>; | |
| 533 | }; | |
| 534 | }; | |
| d5f102ed PC |
535 | |
| 536 | pinctrl_i2c2_alt2_1: i2c2-alt2-1 { | |
| 537 | st,pins { | |
| 538 | sda = <&pio12 6 ALT2 BIDIR>; | |
| 539 | scl = <&pio12 5 ALT2 BIDIR>; | |
| 540 | }; | |
| 541 | }; | |
| f563a571 MC |
542 | }; |
| 543 | ||
| 544 | i2c3 { | |
| 38fc7859 | 545 | pinctrl_i2c3_default: i2c3-alt1-0 { |
| f563a571 MC |
546 | st,pins { |
| 547 | sda = <&pio18 6 ALT1 BIDIR>; | |
| 548 | scl = <&pio18 5 ALT1 BIDIR>; | |
| 549 | }; | |
| 550 | }; | |
| 38fc7859 PG |
551 | pinctrl_i2c3_alt1_1: i2c3-alt1-1 { |
| 552 | st,pins { | |
| 553 | sda = <&pio17 7 ALT1 BIDIR>; | |
| 554 | scl = <&pio17 6 ALT1 BIDIR>; | |
| 555 | }; | |
| 556 | }; | |
| 557 | pinctrl_i2c3_alt3_0: i2c3-alt3-0 { | |
| 558 | st,pins { | |
| 559 | sda = <&pio13 6 ALT3 BIDIR>; | |
| 560 | scl = <&pio13 5 ALT3 BIDIR>; | |
| 561 | }; | |
| 562 | }; | |
| f563a571 MC |
563 | }; |
| 564 | ||
| 565 | spi0 { | |
| 193bb623 PG |
566 | pinctrl_spi0_default: spi0-4w-alt2-0 { |
| 567 | st,pins { | |
| 568 | mtsr = <&pio10 6 ALT2 OUT>; | |
| 569 | mrst = <&pio10 7 ALT2 IN>; | |
| 570 | scl = <&pio10 5 ALT2 OUT>; | |
| 571 | }; | |
| 572 | }; | |
| 573 | ||
| 574 | pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { | |
| f563a571 | 575 | st,pins { |
| 193bb623 PG |
576 | mtsr = <&pio10 6 ALT2 BIDIR_PU>; |
| 577 | scl = <&pio10 5 ALT2 OUT>; | |
| 578 | }; | |
| 579 | }; | |
| 580 | ||
| 581 | pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { | |
| 582 | st,pins { | |
| 583 | mtsr = <&pio19 7 ALT1 OUT>; | |
| 584 | mrst = <&pio19 5 ALT1 IN>; | |
| 585 | scl = <&pio19 6 ALT1 OUT>; | |
| 586 | }; | |
| 587 | }; | |
| 588 | ||
| 589 | pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { | |
| 590 | st,pins { | |
| 591 | mtsr = <&pio19 7 ALT1 BIDIR_PU>; | |
| 592 | scl = <&pio19 6 ALT1 OUT>; | |
| 593 | }; | |
| 594 | }; | |
| 595 | }; | |
| 596 | ||
| 597 | spi1 { | |
| 598 | pinctrl_spi1_default: spi1-4w-alt2-0 { | |
| 599 | st,pins { | |
| 600 | mtsr = <&pio11 1 ALT2 OUT>; | |
| 601 | mrst = <&pio11 2 ALT2 IN>; | |
| 602 | scl = <&pio11 0 ALT2 OUT>; | |
| 603 | }; | |
| 604 | }; | |
| 605 | ||
| 606 | pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { | |
| 607 | st,pins { | |
| 608 | mtsr = <&pio11 1 ALT2 BIDIR_PU>; | |
| 609 | scl = <&pio11 0 ALT2 OUT>; | |
| 610 | }; | |
| 611 | }; | |
| 612 | ||
| 613 | pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { | |
| 614 | st,pins { | |
| 615 | mtsr = <&pio14 3 ALT1 OUT>; | |
| 616 | mrst = <&pio14 4 ALT1 IN>; | |
| 617 | scl = <&pio14 2 ALT1 OUT>; | |
| 618 | }; | |
| 619 | }; | |
| 620 | ||
| 621 | pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { | |
| 622 | st,pins { | |
| 623 | mtsr = <&pio14 3 ALT1 BIDIR_PU>; | |
| 624 | scl = <&pio14 2 ALT1 OUT>; | |
| 625 | }; | |
| 626 | }; | |
| 627 | }; | |
| 628 | ||
| 629 | spi2 { | |
| 630 | pinctrl_spi2_default: spi2-4w-alt2-0 { | |
| 631 | st,pins { | |
| 632 | mtsr = <&pio12 6 ALT2 OUT>; | |
| 633 | mrst = <&pio12 7 ALT2 IN>; | |
| 634 | scl = <&pio12 5 ALT2 OUT>; | |
| 635 | }; | |
| 636 | }; | |
| 637 | ||
| 638 | pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { | |
| 639 | st,pins { | |
| 640 | mtsr = <&pio12 6 ALT2 BIDIR_PU>; | |
| 641 | scl = <&pio12 5 ALT2 OUT>; | |
| 642 | }; | |
| 643 | }; | |
| 644 | ||
| 645 | pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { | |
| 646 | st,pins { | |
| 647 | mtsr = <&pio14 6 ALT1 OUT>; | |
| 648 | mrst = <&pio14 7 ALT1 IN>; | |
| 649 | scl = <&pio14 5 ALT1 OUT>; | |
| 650 | }; | |
| 651 | }; | |
| 652 | ||
| 653 | pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { | |
| 654 | st,pins { | |
| 655 | mtsr = <&pio14 6 ALT1 BIDIR_PU>; | |
| 656 | scl = <&pio14 5 ALT1 OUT>; | |
| 657 | }; | |
| 658 | }; | |
| 659 | ||
| 660 | pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { | |
| 661 | st,pins { | |
| 662 | mtsr = <&pio15 6 ALT2 OUT>; | |
| 663 | mrst = <&pio15 7 ALT2 IN>; | |
| 664 | scl = <&pio15 5 ALT2 OUT>; | |
| 665 | }; | |
| 666 | }; | |
| 667 | ||
| 668 | pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { | |
| 669 | st,pins { | |
| 670 | mtsr = <&pio15 6 ALT2 BIDIR_PU>; | |
| 671 | scl = <&pio15 5 ALT2 OUT>; | |
| 672 | }; | |
| 673 | }; | |
| 674 | }; | |
| 675 | ||
| 676 | spi3 { | |
| 677 | pinctrl_spi3_default: spi3-4w-alt3-0 { | |
| 678 | st,pins { | |
| 679 | mtsr = <&pio13 6 ALT3 OUT>; | |
| 680 | mrst = <&pio13 7 ALT3 IN>; | |
| 681 | scl = <&pio13 5 ALT3 OUT>; | |
| 682 | }; | |
| 683 | }; | |
| 684 | ||
| 685 | pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { | |
| 686 | st,pins { | |
| 687 | mtsr = <&pio13 6 ALT3 BIDIR_PU>; | |
| 688 | scl = <&pio13 5 ALT3 OUT>; | |
| 689 | }; | |
| 690 | }; | |
| 691 | ||
| 692 | pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { | |
| 693 | st,pins { | |
| 694 | mtsr = <&pio17 7 ALT1 OUT>; | |
| 695 | mrst = <&pio17 5 ALT1 IN>; | |
| 696 | scl = <&pio17 6 ALT1 OUT>; | |
| 697 | }; | |
| 698 | }; | |
| 699 | ||
| 700 | pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { | |
| 701 | st,pins { | |
| 702 | mtsr = <&pio17 7 ALT1 BIDIR_PU>; | |
| 703 | scl = <&pio17 6 ALT1 OUT>; | |
| 704 | }; | |
| 705 | }; | |
| 706 | ||
| 707 | pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { | |
| 708 | st,pins { | |
| 709 | mtsr = <&pio18 6 ALT1 OUT>; | |
| 710 | mrst = <&pio18 7 ALT1 IN>; | |
| 711 | scl = <&pio18 5 ALT1 OUT>; | |
| 712 | }; | |
| 713 | }; | |
| 714 | ||
| 715 | pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { | |
| 716 | st,pins { | |
| 717 | mtsr = <&pio18 6 ALT1 BIDIR_PU>; | |
| 718 | scl = <&pio18 5 ALT1 OUT>; | |
| f563a571 MC |
719 | }; |
| 720 | }; | |
| 721 | }; | |
| 747d7e6e PG |
722 | |
| 723 | tsin0 { | |
| 724 | pinctrl_tsin0_parallel: tsin0_parallel { | |
| 725 | st,pins { | |
| 726 | DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 727 | DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 728 | DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 729 | DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 730 | DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 731 | DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 732 | DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 733 | DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 734 | CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 735 | VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 736 | ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 737 | PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 738 | }; | |
| 739 | }; | |
| 740 | pinctrl_tsin0_serial: tsin0_serial { | |
| 741 | st,pins { | |
| 742 | DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 743 | CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 744 | VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 745 | ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 746 | PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 747 | }; | |
| 748 | }; | |
| 749 | }; | |
| 71cae849 PG |
750 | |
| 751 | tsin1 { | |
| 752 | pinctrl_tsin1_parallel: tsin1_parallel { | |
| 753 | st,pins { | |
| 754 | DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 755 | DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 756 | DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 757 | DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 758 | DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 759 | DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 760 | DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 761 | DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 762 | CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 763 | VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 764 | ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 765 | PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 766 | }; | |
| 767 | }; | |
| 768 | pinctrl_tsin1_serial: tsin1_serial { | |
| 769 | st,pins { | |
| 770 | DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 771 | CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 772 | VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 773 | ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 774 | PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 775 | }; | |
| 776 | }; | |
| 777 | }; | |
| 855617d6 PG |
778 | |
| 779 | tsin2 { | |
| 780 | pinctrl_tsin2_parallel: tsin2_parallel { | |
| 781 | st,pins { | |
| 782 | DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 783 | DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; | |
| 784 | DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; | |
| 785 | DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; | |
| 786 | DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 787 | DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; | |
| 788 | DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 789 | DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 790 | CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 791 | VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 792 | ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 793 | PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 794 | }; | |
| 795 | }; | |
| 796 | pinctrl_tsin2_serial: tsin2_serial { | |
| 797 | st,pins { | |
| 798 | DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 799 | CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 800 | VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 801 | ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 802 | PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 803 | }; | |
| 804 | }; | |
| 805 | }; | |
| 36cfc8c1 PG |
806 | |
| 807 | tsin3 { | |
| 808 | pinctrl_tsin3_serial: tsin3_serial { | |
| 809 | st,pins { | |
| 810 | DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 811 | CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 812 | VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 813 | ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 814 | PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 815 | }; | |
| 816 | }; | |
| 817 | }; | |
| af4d191e PG |
818 | |
| 819 | tsin4 { | |
| 820 | pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { | |
| 821 | st,pins { | |
| 822 | DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 823 | CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; | |
| 824 | VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; | |
| 825 | ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; | |
| 826 | PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 827 | }; | |
| 828 | }; | |
| 829 | }; | |
| dd72896f PG |
830 | |
| 831 | tsin5 { | |
| 832 | pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { | |
| 833 | st,pins { | |
| 834 | DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 835 | CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 836 | VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 837 | ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 838 | PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 839 | }; | |
| 840 | }; | |
| 841 | pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { | |
| 842 | st,pins { | |
| 843 | DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 844 | CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; | |
| 845 | VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 846 | ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 847 | PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
| 848 | }; | |
| 849 | }; | |
| 850 | }; | |
| 75d28b83 PG |
851 | |
| 852 | tsout0 { | |
| 853 | pinctrl_tsout0_parallel: tsout0_parallel { | |
| 854 | st,pins { | |
| 855 | DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 856 | DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 857 | DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 858 | DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 859 | DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 860 | DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 861 | DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 862 | DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 863 | CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; | |
| 864 | VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 865 | ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 866 | PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 867 | }; | |
| 868 | }; | |
| 869 | pinctrl_tsout0_serial: tsout0_serial { | |
| 870 | st,pins { | |
| 871 | DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 872 | CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; | |
| 873 | VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 874 | ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 875 | PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; | |
| 876 | }; | |
| 877 | }; | |
| 878 | }; | |
| e0decdd6 PG |
879 | |
| 880 | tsout1 { | |
| 881 | pinctrl_tsout1_serial: tsout1_serial { | |
| 882 | st,pins { | |
| 883 | DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 884 | CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; | |
| 885 | VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 886 | ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 887 | PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
| 888 | }; | |
| 889 | }; | |
| 890 | }; | |
| 810099f6 PG |
891 | |
| 892 | mtsin0 { | |
| 893 | pinctrl_mtsin0_parallel: mtsin0_parallel { | |
| 894 | st,pins { | |
| 895 | DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 896 | DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 897 | DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 898 | DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 899 | DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 900 | DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 901 | DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 902 | DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 903 | CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; | |
| 904 | VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 905 | ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 906 | PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; | |
| 907 | }; | |
| 908 | }; | |
| 909 | }; | |
| 0e602628 PG |
910 | |
| 911 | systrace { | |
| 912 | pinctrl_systrace_default: systrace-default { | |
| 913 | st,pins { | |
| 914 | trc_data0 = <&pio11 3 ALT5 OUT>; | |
| 915 | trc_data1 = <&pio11 4 ALT5 OUT>; | |
| 916 | trc_data2 = <&pio11 5 ALT5 OUT>; | |
| 917 | trc_data3 = <&pio11 6 ALT5 OUT>; | |
| 918 | trc_clk = <&pio11 7 ALT5 OUT>; | |
| 919 | }; | |
| 920 | }; | |
| 921 | }; | |
| f563a571 MC |
922 | }; |
| 923 | ||
| 924 | pin-controller-front1 { | |
| 925 | #address-cells = <1>; | |
| 926 | #size-cells = <1>; | |
| 927 | compatible = "st,stih407-front-pinctrl"; | |
| 928 | st,syscfg = <&syscfg_front>; | |
| 929 | reg = <0x0921f080 0x4>; | |
| 930 | reg-names = "irqmux"; | |
| 931 | interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; | |
| 2bb1441f | 932 | interrupt-names = "irqmux"; |
| f563a571 MC |
933 | ranges = <0 0x09210000 0x10000>; |
| 934 | ||
| 3b879a50 PC |
935 | pio20: pio@09210000 { |
| 936 | gpio-controller; | |
| 4e6ee336 | 937 | #gpio-cells = <2>; |
| 3b879a50 PC |
938 | interrupt-controller; |
| 939 | #interrupt-cells = <2>; | |
| 940 | reg = <0x0 0x100>; | |
| 941 | st,bank-name = "PIO20"; | |
| 942 | }; | |
| 943 | ||
| af4d191e PG |
944 | tsin4 { |
| 945 | pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { | |
| 946 | st,pins { | |
| 947 | DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 948 | CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; | |
| 949 | VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 950 | ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 951 | PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
| 952 | }; | |
| 953 | }; | |
| 954 | }; | |
| f563a571 MC |
955 | }; |
| 956 | ||
| 957 | pin-controller-rear { | |
| 958 | #address-cells = <1>; | |
| 959 | #size-cells = <1>; | |
| 960 | compatible = "st,stih407-rear-pinctrl"; | |
| 961 | st,syscfg = <&syscfg_rear>; | |
| 962 | reg = <0x0922f080 0x4>; | |
| 963 | reg-names = "irqmux"; | |
| 964 | interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>; | |
| 2bb1441f | 965 | interrupt-names = "irqmux"; |
| f563a571 MC |
966 | ranges = <0 0x09220000 0x6000>; |
| 967 | ||
| 968 | pio30: gpio@09220000 { | |
| 969 | gpio-controller; | |
| 4e6ee336 | 970 | #gpio-cells = <2>; |
| f563a571 MC |
971 | interrupt-controller; |
| 972 | #interrupt-cells = <2>; | |
| 973 | reg = <0x0 0x100>; | |
| 974 | st,bank-name = "PIO30"; | |
| 975 | }; | |
| 976 | pio31: gpio@09221000 { | |
| 977 | gpio-controller; | |
| 4e6ee336 | 978 | #gpio-cells = <2>; |
| f563a571 MC |
979 | interrupt-controller; |
| 980 | #interrupt-cells = <2>; | |
| 981 | reg = <0x1000 0x100>; | |
| 982 | st,bank-name = "PIO31"; | |
| 983 | }; | |
| 984 | pio32: gpio@09222000 { | |
| 985 | gpio-controller; | |
| 4e6ee336 | 986 | #gpio-cells = <2>; |
| f563a571 MC |
987 | interrupt-controller; |
| 988 | #interrupt-cells = <2>; | |
| 989 | reg = <0x2000 0x100>; | |
| 990 | st,bank-name = "PIO32"; | |
| 991 | }; | |
| 992 | pio33: gpio@09223000 { | |
| 993 | gpio-controller; | |
| 4e6ee336 | 994 | #gpio-cells = <2>; |
| f563a571 MC |
995 | interrupt-controller; |
| 996 | #interrupt-cells = <2>; | |
| 997 | reg = <0x3000 0x100>; | |
| 998 | st,bank-name = "PIO33"; | |
| 999 | }; | |
| 1000 | pio34: gpio@09224000 { | |
| 1001 | gpio-controller; | |
| 4e6ee336 | 1002 | #gpio-cells = <2>; |
| f563a571 MC |
1003 | interrupt-controller; |
| 1004 | #interrupt-cells = <2>; | |
| 1005 | reg = <0x4000 0x100>; | |
| 1006 | st,bank-name = "PIO34"; | |
| 1007 | }; | |
| 1008 | pio35: gpio@09225000 { | |
| 1009 | gpio-controller; | |
| 4e6ee336 | 1010 | #gpio-cells = <2>; |
| f563a571 MC |
1011 | interrupt-controller; |
| 1012 | #interrupt-cells = <2>; | |
| 1013 | reg = <0x5000 0x100>; | |
| 1014 | st,bank-name = "PIO35"; | |
| d90accb9 | 1015 | st,retime-pin-mask = <0x7f>; |
| f563a571 MC |
1016 | }; |
| 1017 | ||
| 1018 | i2c4 { | |
| 1019 | pinctrl_i2c4_default: i2c4-default { | |
| 1020 | st,pins { | |
| 1021 | sda = <&pio30 1 ALT1 BIDIR>; | |
| 1022 | scl = <&pio30 0 ALT1 BIDIR>; | |
| 1023 | }; | |
| 1024 | }; | |
| 1025 | }; | |
| 1026 | ||
| 1027 | i2c5 { | |
| 1028 | pinctrl_i2c5_default: i2c5-default { | |
| 1029 | st,pins { | |
| 1030 | sda = <&pio34 4 ALT1 BIDIR>; | |
| 1031 | scl = <&pio34 3 ALT1 BIDIR>; | |
| 1032 | }; | |
| 1033 | }; | |
| 1034 | }; | |
| 1035 | ||
| 1036 | usb3 { | |
| 1037 | pinctrl_usb3: usb3-2 { | |
| 1038 | st,pins { | |
| 1039 | usb-oc-detect = <&pio35 4 ALT1 IN>; | |
| 1040 | usb-pwr-enable = <&pio35 5 ALT1 OUT>; | |
| 1041 | usb-vbus-valid = <&pio35 6 ALT1 IN>; | |
| 1042 | }; | |
| 1043 | }; | |
| 1044 | }; | |
| 1045 | ||
| 1046 | pwm0 { | |
| 1047 | pinctrl_pwm0_chan0_default: pwm0-0-default { | |
| 1048 | st,pins { | |
| 30a2366c | 1049 | pwm-capturein = <&pio31 0 ALT1 IN>; |
| f563a571 MC |
1050 | pwm-out = <&pio31 1 ALT1 OUT>; |
| 1051 | }; | |
| 1052 | }; | |
| 1053 | }; | |
| 193bb623 PG |
1054 | |
| 1055 | spi4 { | |
| 1056 | pinctrl_spi4_default: spi4-4w-alt1-0 { | |
| 1057 | st,pins { | |
| 1058 | mtsr = <&pio30 1 ALT1 OUT>; | |
| 1059 | mrst = <&pio30 2 ALT1 IN>; | |
| 1060 | scl = <&pio30 0 ALT1 OUT>; | |
| 1061 | }; | |
| 1062 | }; | |
| 1063 | ||
| 1064 | pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { | |
| 1065 | st,pins { | |
| 1066 | mtsr = <&pio30 1 ALT1 BIDIR_PU>; | |
| 1067 | scl = <&pio30 0 ALT1 OUT>; | |
| 1068 | }; | |
| 1069 | }; | |
| 1070 | ||
| 1071 | pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { | |
| 1072 | st,pins { | |
| 1073 | mtsr = <&pio34 1 ALT3 OUT>; | |
| 1074 | mrst = <&pio34 2 ALT3 IN>; | |
| 1075 | scl = <&pio34 0 ALT3 OUT>; | |
| 1076 | }; | |
| 1077 | }; | |
| 1078 | ||
| 1079 | pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { | |
| 1080 | st,pins { | |
| 1081 | mtsr = <&pio34 1 ALT3 BIDIR_PU>; | |
| 1082 | scl = <&pio34 0 ALT3 OUT>; | |
| 1083 | }; | |
| 1084 | }; | |
| 1085 | }; | |
| d8036479 | 1086 | |
| 6548defe PG |
1087 | i2s_out { |
| 1088 | pinctrl_i2s_8ch_out: i2s_8ch_out{ | |
| 1089 | st,pins { | |
| 1090 | mclk = <&pio33 5 ALT1 OUT>; | |
| 1091 | lrclk = <&pio33 7 ALT1 OUT>; | |
| 1092 | sclk = <&pio33 6 ALT1 OUT>; | |
| 1093 | data0 = <&pio33 4 ALT1 OUT>; | |
| 1094 | data1 = <&pio34 0 ALT1 OUT>; | |
| 1095 | data2 = <&pio34 1 ALT1 OUT>; | |
| 1096 | data3 = <&pio34 2 ALT1 OUT>; | |
| 1097 | }; | |
| 1098 | }; | |
| 1099 | ||
| 1100 | pinctrl_i2s_2ch_out: i2s_2ch_out{ | |
| 1101 | st,pins { | |
| 1102 | mclk = <&pio33 5 ALT1 OUT>; | |
| 1103 | lrclk = <&pio33 7 ALT1 OUT>; | |
| 1104 | sclk = <&pio33 6 ALT1 OUT>; | |
| 1105 | data0 = <&pio33 4 ALT1 OUT>; | |
| 1106 | }; | |
| 1107 | }; | |
| 1108 | }; | |
| 1109 | ||
| d4fe226c PG |
1110 | i2s_in { |
| 1111 | pinctrl_i2s_8ch_in: i2s_8ch_in{ | |
| 1112 | st,pins { | |
| 1113 | mclk = <&pio32 5 ALT1 IN>; | |
| 1114 | lrclk = <&pio32 7 ALT1 IN>; | |
| 1115 | sclk = <&pio32 6 ALT1 IN>; | |
| 1116 | data0 = <&pio32 4 ALT1 IN>; | |
| 1117 | data1 = <&pio33 0 ALT1 IN>; | |
| 1118 | data2 = <&pio33 1 ALT1 IN>; | |
| 1119 | data3 = <&pio33 2 ALT1 IN>; | |
| 1120 | data4 = <&pio33 3 ALT1 IN>; | |
| 1121 | }; | |
| 1122 | }; | |
| 1123 | ||
| 1124 | pinctrl_i2s_2ch_in: i2s_2ch_in{ | |
| 1125 | st,pins { | |
| 1126 | mclk = <&pio32 5 ALT1 IN>; | |
| 1127 | lrclk = <&pio32 7 ALT1 IN>; | |
| 1128 | sclk = <&pio32 6 ALT1 IN>; | |
| 1129 | data0 = <&pio32 4 ALT1 IN>; | |
| 1130 | }; | |
| 1131 | }; | |
| 1132 | }; | |
| 1133 | ||
| 857d477f PG |
1134 | spdif_out { |
| 1135 | pinctrl_spdif_out: spdif_out{ | |
| 1136 | st,pins { | |
| 1137 | spdif_out = <&pio34 7 ALT1 OUT>; | |
| 1138 | }; | |
| 1139 | }; | |
| 1140 | }; | |
| 1141 | ||
| d8036479 PG |
1142 | serial3 { |
| 1143 | pinctrl_serial3: serial3-0 { | |
| 1144 | st,pins { | |
| 1145 | tx = <&pio31 3 ALT1 OUT>; | |
| 1146 | rx = <&pio31 4 ALT1 IN>; | |
| 1147 | }; | |
| 1148 | }; | |
| 1149 | }; | |
| f563a571 MC |
1150 | }; |
| 1151 | ||
| 1152 | pin-controller-flash { | |
| 1153 | #address-cells = <1>; | |
| 1154 | #size-cells = <1>; | |
| 1155 | compatible = "st,stih407-flash-pinctrl"; | |
| 1156 | st,syscfg = <&syscfg_flash>; | |
| 1157 | reg = <0x0923f080 0x4>; | |
| 1158 | reg-names = "irqmux"; | |
| 1159 | interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>; | |
| fd166a3e | 1160 | interrupt-names = "irqmux"; |
| f563a571 MC |
1161 | ranges = <0 0x09230000 0x3000>; |
| 1162 | ||
| 1163 | pio40: gpio@09230000 { | |
| 1164 | gpio-controller; | |
| 4e6ee336 | 1165 | #gpio-cells = <2>; |
| f563a571 MC |
1166 | interrupt-controller; |
| 1167 | #interrupt-cells = <2>; | |
| 1168 | reg = <0 0x100>; | |
| 1169 | st,bank-name = "PIO40"; | |
| 1170 | }; | |
| 1171 | pio41: gpio@09231000 { | |
| 1172 | gpio-controller; | |
| 4e6ee336 | 1173 | #gpio-cells = <2>; |
| f563a571 MC |
1174 | interrupt-controller; |
| 1175 | #interrupt-cells = <2>; | |
| 1176 | reg = <0x1000 0x100>; | |
| 1177 | st,bank-name = "PIO41"; | |
| 1178 | }; | |
| 1179 | pio42: gpio@09232000 { | |
| 1180 | gpio-controller; | |
| 4e6ee336 | 1181 | #gpio-cells = <2>; |
| f563a571 MC |
1182 | interrupt-controller; |
| 1183 | #interrupt-cells = <2>; | |
| 1184 | reg = <0x2000 0x100>; | |
| 1185 | st,bank-name = "PIO42"; | |
| 1186 | }; | |
| 1187 | ||
| 1188 | mmc0 { | |
| 1189 | pinctrl_mmc0: mmc0-0 { | |
| 1190 | st,pins { | |
| 1191 | emmc_clk = <&pio40 6 ALT1 BIDIR>; | |
| 1192 | emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; | |
| 1193 | emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; | |
| 1194 | emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; | |
| 1195 | emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; | |
| 1196 | emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; | |
| 1197 | emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; | |
| 1198 | emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; | |
| 1199 | emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; | |
| 1200 | emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; | |
| 1201 | }; | |
| 1202 | }; | |
| fab87669 PG |
1203 | pinctrl_sd0: sd0-0 { |
| 1204 | st,pins { | |
| 1205 | sd_clk = <&pio40 6 ALT1 BIDIR>; | |
| 1206 | sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; | |
| 1207 | sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; | |
| 1208 | sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; | |
| 1209 | sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; | |
| 1210 | sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; | |
| 1211 | sd_led = <&pio42 0 ALT2 OUT>; | |
| 1212 | sd_pwren = <&pio42 2 ALT2 OUT>; | |
| 1213 | sd_vsel = <&pio42 3 ALT2 OUT>; | |
| 1214 | sd_cd = <&pio42 4 ALT2 IN>; | |
| 1215 | sd_wp = <&pio42 5 ALT2 IN>; | |
| 1216 | }; | |
| 1217 | }; | |
| f563a571 | 1218 | }; |
| 9af0a7b5 PG |
1219 | |
| 1220 | fsm { | |
| 1221 | pinctrl_fsm: fsm { | |
| 1222 | st,pins { | |
| 1223 | spi-fsm-clk = <&pio40 1 ALT1 OUT>; | |
| 1224 | spi-fsm-cs = <&pio40 0 ALT1 OUT>; | |
| 1225 | spi-fsm-mosi = <&pio40 2 ALT1 OUT>; | |
| 1226 | spi-fsm-miso = <&pio40 3 ALT1 IN>; | |
| 1227 | spi-fsm-hol = <&pio40 5 ALT1 OUT>; | |
| 1228 | spi-fsm-wp = <&pio40 4 ALT1 OUT>; | |
| 1229 | }; | |
| 1230 | }; | |
| 1231 | }; | |
| 8eefa90f PG |
1232 | |
| 1233 | nand { | |
| 1234 | pinctrl_nand: nand { | |
| 1235 | st,pins { | |
| 1236 | nand_cs1 = <&pio40 6 ALT3 OUT>; | |
| 1237 | nand_cs0 = <&pio40 7 ALT3 OUT>; | |
| 1238 | nand_d0 = <&pio41 0 ALT3 BIDIR>; | |
| 1239 | nand_d1 = <&pio41 1 ALT3 BIDIR>; | |
| 1240 | nand_d2 = <&pio41 2 ALT3 BIDIR>; | |
| 1241 | nand_d3 = <&pio41 3 ALT3 BIDIR>; | |
| 1242 | nand_d4 = <&pio41 4 ALT3 BIDIR>; | |
| 1243 | nand_d5 = <&pio41 5 ALT3 BIDIR>; | |
| 1244 | nand_d6 = <&pio41 6 ALT3 BIDIR>; | |
| 1245 | nand_d7 = <&pio41 7 ALT3 BIDIR>; | |
| 1246 | nand_we = <&pio42 0 ALT3 OUT>; | |
| 1247 | nand_dqs = <&pio42 1 ALT3 OUT>; | |
| 1248 | nand_ale = <&pio42 2 ALT3 OUT>; | |
| 1249 | nand_cle = <&pio42 3 ALT3 OUT>; | |
| 1250 | nand_rnb = <&pio42 4 ALT3 IN>; | |
| 1251 | nand_oe = <&pio42 5 ALT3 OUT>; | |
| 1252 | }; | |
| 1253 | }; | |
| 1254 | }; | |
| f563a571 MC |
1255 | }; |
| 1256 | }; | |
| 1257 | }; |