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ARM: STi: DT: Add STiH407 family tsout1 pinctrl configuration
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / stih407-pinctrl.dtsi
CommitLineData
f563a571
MC		 1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12
13 aliases {
14 /* 0-5: PIO_SBC */
15 gpio0 = &pio0;
16 gpio1 = &pio1;
17 gpio2 = &pio2;
18 gpio3 = &pio3;
19 gpio4 = &pio4;
20 gpio5 = &pio5;
21 /* 10-19: PIO_FRONT0 */
22 gpio6 = &pio10;
23 gpio7 = &pio11;
24 gpio8 = &pio12;
25 gpio9 = &pio13;
26 gpio10 = &pio14;
27 gpio11 = &pio15;
28 gpio12 = &pio16;
29 gpio13 = &pio17;
30 gpio14 = &pio18;
31 gpio15 = &pio19;
32 /* 20: PIO_FRONT1 */
33 gpio16 = &pio20;
34 /* 30-35: PIO_REAR */
35 gpio17 = &pio30;
36 gpio18 = &pio31;
37 gpio19 = &pio32;
38 gpio20 = &pio33;
39 gpio21 = &pio34;
40 gpio22 = &pio35;
41 /* 40-42: PIO_FLASH */
42 gpio23 = &pio40;
43 gpio24 = &pio41;
44 gpio25 = &pio42;
45 };
46
47 soc {
48 pin-controller-sbc {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "st,stih407-sbc-pinctrl";
52 st,syscfg = <&syscfg_sbc>;
53 reg = <0x0961f080 0x4>;
54 reg-names = "irqmux";
55 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
56 interrupts-names = "irqmux";
57 ranges = <0 0x09610000 0x6000>;
58
59 pio0: gpio@09610000 {
60 gpio-controller;
61 #gpio-cells = <1>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
64 reg = <0x0 0x100>;
65 st,bank-name = "PIO0";
66 };
67 pio1: gpio@09611000 {
68 gpio-controller;
69 #gpio-cells = <1>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 reg = <0x1000 0x100>;
73 st,bank-name = "PIO1";
74 };
75 pio2: gpio@09612000 {
76 gpio-controller;
77 #gpio-cells = <1>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
80 reg = <0x2000 0x100>;
81 st,bank-name = "PIO2";
82 };
83 pio3: gpio@09613000 {
84 gpio-controller;
85 #gpio-cells = <1>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
88 reg = <0x3000 0x100>;
89 st,bank-name = "PIO3";
90 };
91 pio4: gpio@09614000 {
92 gpio-controller;
93 #gpio-cells = <1>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 reg = <0x4000 0x100>;
97 st,bank-name = "PIO4";
98 };
99
100 pio5: gpio@09615000 {
101 gpio-controller;
102 #gpio-cells = <1>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 reg = <0x5000 0x100>;
106 st,bank-name = "PIO5";
d90accb9 107 st,retime-pin-mask = <0x3f>;
f563a571
MC		 108 };
109
110 rc {
111 pinctrl_ir: ir0 {
112 st,pins {
113 ir = <&pio4 0 ALT2 IN>;
114 };
115 };
116 };
117
118 /* SBC_ASC0 - UART10 */
119 sbc_serial0 {
120 pinctrl_sbc_serial0: sbc_serial0-0 {
121 st,pins {
122 tx = <&pio3 4 ALT1 OUT>;
123 rx = <&pio3 5 ALT1 IN>;
124 };
125 };
126 };
127 /* SBC_ASC1 - UART11 */
128 sbc_serial1 {
129 pinctrl_sbc_serial1: sbc_serial1-0 {
130 st,pins {
131 tx = <&pio2 6 ALT3 OUT>;
132 rx = <&pio2 7 ALT3 IN>;
133 };
134 };
135 };
136
137 i2c10 {
138 pinctrl_i2c10_default: i2c10-default {
139 st,pins {
140 sda = <&pio4 6 ALT1 BIDIR>;
141 scl = <&pio4 5 ALT1 BIDIR>;
142 };
143 };
144 };
145
146 i2c11 {
147 pinctrl_i2c11_default: i2c11-default {
148 st,pins {
149 sda = <&pio5 1 ALT1 BIDIR>;
150 scl = <&pio5 0 ALT1 BIDIR>;
151 };
152 };
153 };
154
155 keyscan {
156 pinctrl_keyscan: keyscan {
157 st,pins {
158 keyin0 = <&pio4 0 ALT6 IN>;
159 keyin1 = <&pio4 5 ALT4 IN>;
160 keyin2 = <&pio0 4 ALT2 IN>;
161 keyin3 = <&pio2 6 ALT2 IN>;
162
163 keyout0 = <&pio4 6 ALT4 OUT>;
164 keyout1 = <&pio1 7 ALT2 OUT>;
165 keyout2 = <&pio0 6 ALT2 OUT>;
166 keyout3 = <&pio2 7 ALT2 OUT>;
167 };
168 };
169 };
170
171 gmac1 {
172 /*
173 * Almost all the boards based on STiH407 SoC have an embedded
174 * switch where the mdio/mdc have been used for managing the SMI
175 * iface via I2C. For this reason these lines can be allocated
176 * by using dedicated configuration (in case of there will be a
177 * standard PHY transceiver on-board).
178 */
179 pinctrl_rgmii1: rgmii1-0 {
180 st,pins {
181
182 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
183 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
184 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
185 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
186 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
187 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
188 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
189 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
190 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
191 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
192 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
193 rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
194 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
195 phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
196 };
197 };
198
199 pinctrl_rgmii1_mdio: rgmii1-mdio {
200 st,pins {
201 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
202 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
203 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
204 };
205 };
206
207 pinctrl_mii1: mii1 {
208 st,pins {
209 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
210 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
211 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
212 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
213 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
214 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
215 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
216 col = <&pio0 7 ALT1 IN BYPASS 1000>;
217
218 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
219 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
220 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
221 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
222 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
223 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
224 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
225 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
226
227 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
228 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
229 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
230 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
231 };
232 };
233 };
234
235 pwm1 {
236 pinctrl_pwm1_chan0_default: pwm1-0-default {
237 st,pins {
238 pwm-out = <&pio3 0 ALT1 OUT>;
239 };
240 };
241 pinctrl_pwm1_chan1_default: pwm1-1-default {
242 st,pins {
243 pwm-out = <&pio4 4 ALT1 OUT>;
244 };
245 };
246 pinctrl_pwm1_chan2_default: pwm1-2-default {
247 st,pins {
248 pwm-out = <&pio4 6 ALT3 OUT>;
249 };
250 };
251 pinctrl_pwm1_chan3_default: pwm1-3-default {
252 st,pins {
253 pwm-out = <&pio4 7 ALT3 OUT>;
254 };
255 };
256 };
257 };
258
259 pin-controller-front0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 compatible = "st,stih407-front-pinctrl";
263 st,syscfg = <&syscfg_front>;
264 reg = <0x0920f080 0x4>;
265 reg-names = "irqmux";
266 interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
267 interrupts-names = "irqmux";
268 ranges = <0 0x09200000 0x10000>;
269
270 pio10: pio@09200000 {
271 gpio-controller;
272 #gpio-cells = <1>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 reg = <0x0 0x100>;
276 st,bank-name = "PIO10";
277 };
278 pio11: pio@09201000 {
279 gpio-controller;
280 #gpio-cells = <1>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 reg = <0x1000 0x100>;
284 st,bank-name = "PIO11";
285 };
286 pio12: pio@09202000 {
287 gpio-controller;
288 #gpio-cells = <1>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
291 reg = <0x2000 0x100>;
292 st,bank-name = "PIO12";
293 };
294 pio13: pio@09203000 {
295 gpio-controller;
296 #gpio-cells = <1>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 reg = <0x3000 0x100>;
300 st,bank-name = "PIO13";
301 };
302 pio14: pio@09204000 {
303 gpio-controller;
304 #gpio-cells = <1>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 reg = <0x4000 0x100>;
308 st,bank-name = "PIO14";
309 };
310 pio15: pio@09205000 {
311 gpio-controller;
312 #gpio-cells = <1>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
315 reg = <0x5000 0x100>;
316 st,bank-name = "PIO15";
317 };
318 pio16: pio@09206000 {
319 gpio-controller;
320 #gpio-cells = <1>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 reg = <0x6000 0x100>;
324 st,bank-name = "PIO16";
325 };
326 pio17: pio@09207000 {
327 gpio-controller;
328 #gpio-cells = <1>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 reg = <0x7000 0x100>;
332 st,bank-name = "PIO17";
333 };
334 pio18: pio@09208000 {
335 gpio-controller;
336 #gpio-cells = <1>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 reg = <0x8000 0x100>;
340 st,bank-name = "PIO18";
341 };
342 pio19: pio@09209000 {
343 gpio-controller;
344 #gpio-cells = <1>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 reg = <0x9000 0x100>;
348 st,bank-name = "PIO19";
349 };
350
351 /* Comms */
352 serial0 {
353 pinctrl_serial0: serial0-0 {
354 st,pins {
355 tx = <&pio17 0 ALT1 OUT>;
356 rx = <&pio17 1 ALT1 IN>;
357 };
358 };
359 };
360
361 serial1 {
362 pinctrl_serial1: serial1-0 {
363 st,pins {
364 tx = <&pio16 0 ALT1 OUT>;
365 rx = <&pio16 1 ALT1 IN>;
366 };
367 };
368 };
369
370 serial2 {
371 pinctrl_serial2: serial2-0 {
372 st,pins {
373 tx = <&pio15 0 ALT1 OUT>;
374 rx = <&pio15 1 ALT1 IN>;
375 };
376 };
377 };
378
379 mmc1 {
380 pinctrl_sd1: sd1-0 {
381 st,pins {
382 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
383 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
384 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
385 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
386 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
387 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
388 sd_led = <&pio16 6 ALT6 OUT>;
389 sd_pwren = <&pio16 7 ALT6 OUT>;
390 sd_cd = <&pio19 0 ALT6 IN>;
391 sd_wp = <&pio19 1 ALT6 IN>;
392 };
393 };
394 };
395
396
397 i2c0 {
398 pinctrl_i2c0_default: i2c0-default {
399 st,pins {
400 sda = <&pio10 6 ALT2 BIDIR>;
401 scl = <&pio10 5 ALT2 BIDIR>;
402 };
403 };
404 };
405
406 i2c1 {
407 pinctrl_i2c1_default: i2c1-default {
408 st,pins {
409 sda = <&pio11 1 ALT2 BIDIR>;
410 scl = <&pio11 0 ALT2 BIDIR>;
411 };
412 };
413 };
414
415 i2c2 {
416 pinctrl_i2c2_default: i2c2-default {
417 st,pins {
418 sda = <&pio15 6 ALT2 BIDIR>;
419 scl = <&pio15 5 ALT2 BIDIR>;
420 };
421 };
422 };
423
424 i2c3 {
425 pinctrl_i2c3_default: i2c3-default {
426 st,pins {
427 sda = <&pio18 6 ALT1 BIDIR>;
428 scl = <&pio18 5 ALT1 BIDIR>;
429 };
430 };
431 };
432
433 spi0 {
434 pinctrl_spi0_default: spi0-default {
435 st,pins {
436 mtsr = <&pio12 6 ALT2 BIDIR>;
437 mrst = <&pio12 7 ALT2 BIDIR>;
438 scl = <&pio12 5 ALT2 BIDIR>;
439 };
440 };
441 };
747d7e6e
PG		 442
443 tsin0 {
444 pinctrl_tsin0_parallel: tsin0_parallel {
445 st,pins {
446 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
447 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
448 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
449 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
450 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
451 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
452 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
453 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
454 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
455 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
456 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
457 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
458 };
459 };
460 pinctrl_tsin0_serial: tsin0_serial {
461 st,pins {
462 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
463 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
464 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
465 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
466 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
467 };
468 };
469 };
71cae849
PG		 470
471 tsin1 {
472 pinctrl_tsin1_parallel: tsin1_parallel {
473 st,pins {
474 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
475 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
476 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
477 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
478 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
479 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
480 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
481 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
482 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
483 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
484 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
485 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
486 };
487 };
488 pinctrl_tsin1_serial: tsin1_serial {
489 st,pins {
490 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
491 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
492 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
493 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
494 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
495 };
496 };
497 };
855617d6
PG		 498
499 tsin2 {
500 pinctrl_tsin2_parallel: tsin2_parallel {
501 st,pins {
502 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
503 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
504 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
505 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
506 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
507 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
508 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
509 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
510 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
511 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
512 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
513 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
514 };
515 };
516 pinctrl_tsin2_serial: tsin2_serial {
517 st,pins {
518 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
519 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
520 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
521 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
522 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
523 };
524 };
525 };
36cfc8c1
PG		 526
527 tsin3 {
528 pinctrl_tsin3_serial: tsin3_serial {
529 st,pins {
530 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
531 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
532 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
533 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
534 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
535 };
536 };
537 };
af4d191e
PG		 538
539 tsin4 {
540 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
541 st,pins {
542 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
543 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
544 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
545 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
546 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
547 };
548 };
549 };
dd72896f
PG		 550
551 tsin5 {
552 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
553 st,pins {
554 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
555 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
556 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
557 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
558 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
559 };
560 };
561 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
562 st,pins {
563 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
564 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
565 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
566 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
567 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
568 };
569 };
570 };
75d28b83
PG		 571
572 tsout0 {
573 pinctrl_tsout0_parallel: tsout0_parallel {
574 st,pins {
575 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
576 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
577 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
578 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
579 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
580 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
581 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
582 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
583 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
584 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
585 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
586 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
587 };
588 };
589 pinctrl_tsout0_serial: tsout0_serial {
590 st,pins {
591 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
592 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
593 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
594 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
595 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
596 };
597 };
598 };
e0decdd6
PG		 599
600 tsout1 {
601 pinctrl_tsout1_serial: tsout1_serial {
602 st,pins {
603 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
604 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
605 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
606 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
607 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
608 };
609 };
610 };
f563a571
MC		 611 };
612
613 pin-controller-front1 {
614 #address-cells = <1>;
615 #size-cells = <1>;
616 compatible = "st,stih407-front-pinctrl";
617 st,syscfg = <&syscfg_front>;
618 reg = <0x0921f080 0x4>;
619 reg-names = "irqmux";
620 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
621 interrupts-names = "irqmux";
622 ranges = <0 0x09210000 0x10000>;
623
af4d191e
PG		 624 tsin4 {
625 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
626 st,pins {
627 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
628 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
629 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
630 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
631 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
632 };
633 };
634 };
635
f563a571
MC		 636 pio20: pio@09210000 {
637 gpio-controller;
638 #gpio-cells = <1>;
639 interrupt-controller;
640 #interrupt-cells = <2>;
641 reg = <0x0 0x100>;
642 st,bank-name = "PIO20";
643 };
644 };
645
646 pin-controller-rear {
647 #address-cells = <1>;
648 #size-cells = <1>;
649 compatible = "st,stih407-rear-pinctrl";
650 st,syscfg = <&syscfg_rear>;
651 reg = <0x0922f080 0x4>;
652 reg-names = "irqmux";
653 interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
654 interrupts-names = "irqmux";
655 ranges = <0 0x09220000 0x6000>;
656
657 pio30: gpio@09220000 {
658 gpio-controller;
659 #gpio-cells = <1>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
662 reg = <0x0 0x100>;
663 st,bank-name = "PIO30";
664 };
665 pio31: gpio@09221000 {
666 gpio-controller;
667 #gpio-cells = <1>;
668 interrupt-controller;
669 #interrupt-cells = <2>;
670 reg = <0x1000 0x100>;
671 st,bank-name = "PIO31";
672 };
673 pio32: gpio@09222000 {
674 gpio-controller;
675 #gpio-cells = <1>;
676 interrupt-controller;
677 #interrupt-cells = <2>;
678 reg = <0x2000 0x100>;
679 st,bank-name = "PIO32";
680 };
681 pio33: gpio@09223000 {
682 gpio-controller;
683 #gpio-cells = <1>;
684 interrupt-controller;
685 #interrupt-cells = <2>;
686 reg = <0x3000 0x100>;
687 st,bank-name = "PIO33";
688 };
689 pio34: gpio@09224000 {
690 gpio-controller;
691 #gpio-cells = <1>;
692 interrupt-controller;
693 #interrupt-cells = <2>;
694 reg = <0x4000 0x100>;
695 st,bank-name = "PIO34";
696 };
697 pio35: gpio@09225000 {
698 gpio-controller;
699 #gpio-cells = <1>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
702 reg = <0x5000 0x100>;
703 st,bank-name = "PIO35";
d90accb9 704 st,retime-pin-mask = <0x7f>;
f563a571
MC		 705 };
706
707 i2c4 {
708 pinctrl_i2c4_default: i2c4-default {
709 st,pins {
710 sda = <&pio30 1 ALT1 BIDIR>;
711 scl = <&pio30 0 ALT1 BIDIR>;
712 };
713 };
714 };
715
716 i2c5 {
717 pinctrl_i2c5_default: i2c5-default {
718 st,pins {
719 sda = <&pio34 4 ALT1 BIDIR>;
720 scl = <&pio34 3 ALT1 BIDIR>;
721 };
722 };
723 };
724
725 usb3 {
726 pinctrl_usb3: usb3-2 {
727 st,pins {
728 usb-oc-detect = <&pio35 4 ALT1 IN>;
729 usb-pwr-enable = <&pio35 5 ALT1 OUT>;
730 usb-vbus-valid = <&pio35 6 ALT1 IN>;
731 };
732 };
733 };
734
735 pwm0 {
736 pinctrl_pwm0_chan0_default: pwm0-0-default {
737 st,pins {
738 pwm-out = <&pio31 1 ALT1 OUT>;
739 };
740 };
741 };
742 };
743
744 pin-controller-flash {
745 #address-cells = <1>;
746 #size-cells = <1>;
747 compatible = "st,stih407-flash-pinctrl";
748 st,syscfg = <&syscfg_flash>;
749 reg = <0x0923f080 0x4>;
750 reg-names = "irqmux";
751 interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
752 interrupts-names = "irqmux";
753 ranges = <0 0x09230000 0x3000>;
754
755 pio40: gpio@09230000 {
756 gpio-controller;
757 #gpio-cells = <1>;
758 interrupt-controller;
759 #interrupt-cells = <2>;
760 reg = <0 0x100>;
761 st,bank-name = "PIO40";
762 };
763 pio41: gpio@09231000 {
764 gpio-controller;
765 #gpio-cells = <1>;
766 interrupt-controller;
767 #interrupt-cells = <2>;
768 reg = <0x1000 0x100>;
769 st,bank-name = "PIO41";
770 };
771 pio42: gpio@09232000 {
772 gpio-controller;
773 #gpio-cells = <1>;
774 interrupt-controller;
775 #interrupt-cells = <2>;
776 reg = <0x2000 0x100>;
777 st,bank-name = "PIO42";
778 };
779
780 mmc0 {
781 pinctrl_mmc0: mmc0-0 {
782 st,pins {
783 emmc_clk = <&pio40 6 ALT1 BIDIR>;
784 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
785 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
786 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
787 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
788 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
789 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
790 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
791 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
792 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
793 };
794 };
795 };
796 };
797 };
798};
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