[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / stih410.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	aliases {
		bdisp0 = &bdisp0;
	};

	soc {
		usb2_picophy1: phy2@0 {
			compatible = "st,stih407-usb2-phy";
			reg = <0 0>;
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xf8 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY0_RESET>;
			reset-names = "global", "port";

			status = "disabled";
		};

		usb2_picophy2: phy3@0 {
			compatible = "st,stih407-usb2-phy";
			reg = <0 0>;
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xfc 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY1_RESET>;
			reset-names = "global", "port";

			status = "disabled";
		};

		ohci0: usb@9a03c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a03c00 0x100>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci0: usb@9a03e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a03e00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ohci1: usb@9a83c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a83c00 0x100>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci1: usb@9a83e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a83e00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		sti-display-subsystem@0 {
			compatible = "st,sti-display-subsystem";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0 0>;
			assigned-clocks	= <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_quadfs 1>,
					  <&clk_s_c0_pll1 0>,
					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

			assigned-clock-parents = <0>,
						 <0>,
						 <0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>;

			assigned-clock-rates = <297000000>,
					       <297000000>,
					       <0>,
					       <400000000>,
					       <400000000>;

			ranges;

			sti-compositor@9d11000 {
				compatible = "st,stih407-compositor";
				reg = <0x9d11000 0x1000>;

				clock-names = "compo_main",
					      "compo_aux",
					      "pix_main",
					      "pix_aux",
					      "pix_gdp1",
					      "pix_gdp2",
					      "pix_gdp3",
					      "pix_gdp4",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				reset-names = "compo-main", "compo-aux";
				resets = <&softreset STIH407_COMPO_SOFTRESET>,
					 <&softreset STIH407_COMPO_SOFTRESET>;
				st,vtg = <&vtg_main>, <&vtg_aux>;
			};

			sti-tvout@8d08000 {
				compatible = "st,stih407-tvout";
				reg = <0x8d08000 0x1000>;
				reg-names = "tvout-reg";
				reset-names = "tvout";
				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
				#address-cells = <1>;
				#size-cells = <1>;
				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						  <&clk_s_d0_flexgen CLK_PCM_0>,
						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						  <&clk_s_d2_flexgen CLK_HDDAC>;

				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
							 <&clk_tmdsout_hdmi>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d0_quadfs 0>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d2_quadfs 0>;
			};

			sti_hdmi: sti-hdmi@8d04000 {
				compatible = "st,stih407-hdmi";
				reg = <0x8d04000 0x1000>;
				reg-names = "hdmi-reg";
				#sound-dai-cells = <0>;
				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "irq";
				clock-names = "pix",
					      "tmds",
					      "phy",
					      "audio",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
					 <&clk_s_d0_flexgen CLK_PCM_0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
				reset-names = "hdmi";
				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
				ddc = <&hdmiddc>;
			};

			sti-hda@8d02000 {
				compatible = "st,stih407-hda";
				status = "disabled";
				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
				reg-names = "hda-reg", "video-dacs-ctrl";
				clock-names = "pix",
					      "hddac",
					      "main_parent",
					      "aux_parent";
				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
					 <&clk_s_d2_flexgen CLK_HDDAC>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;
			};

			sti-hqvdp@9c00000 {
				compatible = "st,stih407-hqvdp";
				reg = <0x9C00000 0x100000>;
				clock-names = "hqvdp", "pix_main";
				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
				reset-names = "hqvdp";
				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
				st,vtg = <&vtg_main>;
			};
		};

		bdisp0:bdisp@9f10000 {
			compatible = "st,stih407-bdisp";
			reg = <0x9f10000 0x1000>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "bdisp";
			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
		};

		hva@8c85000 {
			compatible = "st,st-hva";
			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
			reg-names = "hva_registers", "hva_esram";
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "clk_hva";
			clocks = <&clk_s_c0_flexgen CLK_HVA>;
		};

		thermal@91a0000 {
			compatible = "st,stih407-thermal";
			reg = <0x91a0000 0x28>;
			clock-names = "thermal";
			clocks = <&clk_sysin>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
		};

		delta0@0 {
			compatible = "st,st-delta";
			clock-names = "delta",
				      "delta-st231",
				      "delta-flash-promip";
			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
				 <&clk_s_c0_flexgen CLK_ST231_DMU>,
				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
		};

		sti-cec@94a087c {
			compatible = "st,stih-cec";
			reg = <0x94a087c 0x64>;
			clocks = <&clk_sysin>;
			clock-names = "cec-clk";
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cec-irq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_cec0_default>;
			resets = <&softreset STIH407_LPM_SOFTRESET>;
			hdmi-phandle = <&sti_hdmi>;
		};
	};
};
Commit	Line	Data
1d0ea069	1	// SPDX-License-Identifier: GPL-2.0-only
b16b77a5 PG	2	/*
	3	* Copyright (C) 2014 STMicroelectronics Limited.
	4	* Author: Peter Griffin <peter.griffin@linaro.org>
b16b77a5 PG	5	*/
	6	#include "stih410-clock.dtsi"
	7	#include "stih407-family.dtsi"
	8	#include "stih410-pinctrl.dtsi"
7ac1f59c	9	#include <dt-bindings/gpio/gpio.h>
b16b77a5	10	/ {
79444509 FD	11	aliases {
	12	bdisp0 = &bdisp0;
	13	};
	14
9d9f65fc	15	soc {
1d91958f	16	usb2_picophy1: phy2@0 {
9d9f65fc	17	compatible = "st,stih407-usb2-phy";
1d91958f	18	reg = <0 0>;
9d9f65fc PG	19	#phy-cells = <0>;
	20	st,syscfg = <&syscfg_core 0xf8 0xf4>;
	21	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	22	<&picophyreset STIH407_PICOPHY0_RESET>;
	23	reset-names = "global", "port";
b771ae27 MC	24
b771ae27 MC	25	status = "disabled";
9d9f65fc	26	};
b16b77a5	27
1d91958f	28	usb2_picophy2: phy3@0 {
9d9f65fc	29	compatible = "st,stih407-usb2-phy";
1d91958f	30	reg = <0 0>;
9d9f65fc PG	31	#phy-cells = <0>;
	32	st,syscfg = <&syscfg_core 0xfc 0xf4>;
	33	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	34	<&picophyreset STIH407_PICOPHY1_RESET>;
	35	reset-names = "global", "port";
b771ae27 MC	36
b771ae27 MC	37	status = "disabled";
9d9f65fc	38	};
a59a4d96 PG	39
	40	ohci0: usb@9a03c00 {
	41	compatible = "st,st-ohci-300x";
	42	reg = <0x9a03c00 0x100>;
fd827d0e	43	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
7e9d2850 LJ	44	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	45	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	46	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	47	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	48	reset-names = "power", "softreset";
	49	phys = <&usb2_picophy1>;
	50	phy-names = "usb";
b771ae27 MC	51
b771ae27 MC	52	status = "disabled";
a59a4d96 PG	53	};
	54
	55	ehci0: usb@9a03e00 {
	56	compatible = "st,st-ehci-300x";
	57	reg = <0x9a03e00 0x100>;
fd827d0e	58	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
a59a4d96 PG	59	pinctrl-names = "default";
a59a4d96 PG	60	pinctrl-0 = <&pinctrl_usb0>;
7e9d2850 LJ	61	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	62	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	63	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	64	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	65	reset-names = "power", "softreset";
	66	phys = <&usb2_picophy1>;
	67	phy-names = "usb";
b771ae27 MC	68
b771ae27 MC	69	status = "disabled";
a59a4d96 PG	70	};
	71
	72	ohci1: usb@9a83c00 {
	73	compatible = "st,st-ohci-300x";
	74	reg = <0x9a83c00 0x100>;
fd827d0e	75	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
7e9d2850 LJ	76	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	77	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	78	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	79	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	80	reset-names = "power", "softreset";
	81	phys = <&usb2_picophy2>;
	82	phy-names = "usb";
b771ae27 MC	83
b771ae27 MC	84	status = "disabled";
a59a4d96 PG	85	};
	86
	87	ehci1: usb@9a83e00 {
	88	compatible = "st,st-ehci-300x";
	89	reg = <0x9a83e00 0x100>;
fd827d0e	90	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
a59a4d96 PG	91	pinctrl-names = "default";
a59a4d96 PG	92	pinctrl-0 = <&pinctrl_usb1>;
7e9d2850 LJ	93	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	94	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	95	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	96	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	97	reset-names = "power", "softreset";
	98	phys = <&usb2_picophy2>;
	99	phy-names = "usb";
956b42d1	100
b771ae27	101	status = "disabled";
956b42d1 GF	102	};
956b42d1 GF	103
0b09a91a	104	sti-display-subsystem@0 {
956b42d1 GF	105	compatible = "st,sti-display-subsystem";
	106	#address-cells = <1>;
	107	#size-cells = <1>;
	108
0b09a91a	109	reg = <0 0>;
956b42d1	110	assigned-clocks = <&clk_s_d2_quadfs 0>,
3a74152c GF	111	<&clk_s_d2_quadfs 1>,
	112	<&clk_s_c0_pll1 0>,
	113	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	114	<&clk_s_c0_flexgen CLK_MAIN_DISP>,
956b42d1 GF	115	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	116	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	117	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	118	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	119	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	120	<&clk_s_d2_flexgen CLK_PIX_GDP4>;
	121
	122	assigned-clock-parents = <0>,
	123	<0>,
3a74152c GF	124	<0>,
	125	<&clk_s_c0_pll1 0>,
	126	<&clk_s_c0_pll1 0>,
956b42d1	127	<&clk_s_d2_quadfs 0>,
3a74152c	128	<&clk_s_d2_quadfs 1>,
956b42d1 GF	129	<&clk_s_d2_quadfs 0>,
	130	<&clk_s_d2_quadfs 0>,
	131	<&clk_s_d2_quadfs 0>,
	132	<&clk_s_d2_quadfs 0>;
	133
3a74152c	134	assigned-clock-rates = <297000000>,
b9ec866d	135	<297000000>,
3a74152c GF	136	<0>,
	137	<400000000>,
	138	<400000000>;
956b42d1 GF	139
	140	ranges;
	141
	142	sti-compositor@9d11000 {
	143	compatible = "st,stih407-compositor";
	144	reg = <0x9d11000 0x1000>;
	145
	146	clock-names = "compo_main",
	147	"compo_aux",
	148	"pix_main",
	149	"pix_aux",
	150	"pix_gdp1",
	151	"pix_gdp2",
	152	"pix_gdp3",
	153	"pix_gdp4",
	154	"main_parent",
	155	"aux_parent";
	156
	157	clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
	158	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	159	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	160	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	161	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	162	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	163	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	164	<&clk_s_d2_flexgen CLK_PIX_GDP4>,
	165	<&clk_s_d2_quadfs 0>,
	166	<&clk_s_d2_quadfs 1>;
	167
	168	reset-names = "compo-main", "compo-aux";
	169	resets = <&softreset STIH407_COMPO_SOFTRESET>,
	170	<&softreset STIH407_COMPO_SOFTRESET>;
	171	st,vtg = <&vtg_main>, <&vtg_aux>;
	172	};
	173
	174	sti-tvout@8d08000 {
	175	compatible = "st,stih407-tvout";
	176	reg = <0x8d08000 0x1000>;
	177	reg-names = "tvout-reg";
	178	reset-names = "tvout";
	179	resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
	180	#address-cells = <1>;
	181	#size-cells = <1>;
	182	assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
	183	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
	184	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
	185	<&clk_s_d0_flexgen CLK_PCM_0>,
	186	<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
	187	<&clk_s_d2_flexgen CLK_HDDAC>;
	188
	189	assigned-clock-parents = <&clk_s_d2_quadfs 0>,
	190	<&clk_tmdsout_hdmi>,
	191	<&clk_s_d2_quadfs 0>,
	192	<&clk_s_d0_quadfs 0>,
	193	<&clk_s_d2_quadfs 0>,
	194	<&clk_s_d2_quadfs 0>;
79a313f5 BG	195	};
79a313f5 BG	196
24595472	197	sti_hdmi: sti-hdmi@8d04000 {
79a313f5 BG	198	compatible = "st,stih407-hdmi";
	199	reg = <0x8d04000 0x1000>;
	200	reg-names = "hdmi-reg";
4f21a120	201	#sound-dai-cells = <0>;
fd827d0e	202	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
79a313f5 BG	203	interrupt-names = "irq";
	204	clock-names = "pix",
	205	"tmds",
	206	"phy",
	207	"audio",
	208	"main_parent",
	209	"aux_parent";
	210
	211	clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
	212	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
	213	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
	214	<&clk_s_d0_flexgen CLK_PCM_0>,
	215	<&clk_s_d2_quadfs 0>,
	216	<&clk_s_d2_quadfs 1>;
	217
7ac1f59c	218	hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
79a313f5 BG	219	reset-names = "hdmi";
	220	resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
	221	ddc = <&hdmiddc>;
	222	};
	223
	224	sti-hda@8d02000 {
	225	compatible = "st,stih407-hda";
9d65f902	226	status = "disabled";
79a313f5 BG	227	reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
	228	reg-names = "hda-reg", "video-dacs-ctrl";
	229	clock-names = "pix",
	230	"hddac",
	231	"main_parent",
	232	"aux_parent";
	233	clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
	234	<&clk_s_d2_flexgen CLK_HDDAC>,
	235	<&clk_s_d2_quadfs 0>,
	236	<&clk_s_d2_quadfs 1>;
956b42d1	237	};
241a6878	238
d6d854cc	239	sti-hqvdp@9c00000 {
241a6878 PC	240	compatible = "st,stih407-hqvdp";
	241	reg = <0x9C00000 0x100000>;
	242	clock-names = "hqvdp", "pix_main";
	243	clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
	244	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
	245	reset-names = "hqvdp";
	246	resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
	247	st,vtg = <&vtg_main>;
	248	};
956b42d1	249	};
79444509 FD	250
	251	bdisp0:bdisp@9f10000 {
	252	compatible = "st,stih407-bdisp";
	253	reg = <0x9f10000 0x1000>;
fd827d0e	254	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
79444509 FD	255	clock-names = "bdisp";
	256	clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
	257	};
70bc0f3a	258
390aafe3 JCT	259	hva@8c85000 {
	260	compatible = "st,st-hva";
	261	reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
	262	reg-names = "hva_registers", "hva_esram";
fd827d0e PC	263	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
fd827d0e PC	264	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
390aafe3 JCT	265	clock-names = "clk_hva";
	266	clocks = <&clk_s_c0_flexgen CLK_HVA>;
	267	};
	268
70bc0f3a PC	269	thermal@91a0000 {
	270	compatible = "st,stih407-thermal";
	271	reg = <0x91a0000 0x28>;
	272	clock-names = "thermal";
	273	clocks = <&clk_sysin>;
	274	interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
	275	};
b005ebf9	276
5eccdffb	277	delta0@0 {
b005ebf9 HF	278	compatible = "st,st-delta";
	279	clock-names = "delta",
	280	"delta-st231",
	281	"delta-flash-promip";
	282	clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
	283	<&clk_s_c0_flexgen CLK_ST231_DMU>,
	284	<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
	285	};
ed3022de	286
8dccafaa	287	sti-cec@94a087c {
ed3022de BG	288	compatible = "st,stih-cec";
	289	reg = <0x94a087c 0x64>;
	290	clocks = <&clk_sysin>;
	291	clock-names = "cec-clk";
fd827d0e	292	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
ed3022de BG	293	interrupt-names = "cec-irq";
	294	pinctrl-names = "default";
	295	pinctrl-0 = <&pinctrl_cec0_default>;
	296	resets = <&softreset STIH407_LPM_SOFTRESET>;
	297	hdmi-phandle = <&sti_hdmi>;
	298	};
9d9f65fc	299	};
b16b77a5	300	};