[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / stih410.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
/ {
	aliases {
		bdisp0 = &bdisp0;
	};

	soc {
		usb2_picophy1: phy2 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xf8 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY0_RESET>;
			reset-names = "global", "port";
		};

		usb2_picophy2: phy3 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xfc 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY1_RESET>;
			reset-names = "global", "port";
		};

		ohci0: usb@9a03c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a03c00 0x100>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";
		};

		ehci0: usb@9a03e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a03e00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";
		};

		ohci1: usb@9a83c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a83c00 0x100>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";
		};

		ehci1: usb@9a83e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a83e00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";
		};

		sti-display-subsystem {
			compatible = "st,sti-display-subsystem";
			#address-cells = <1>;
			#size-cells = <1>;

			assigned-clocks	= <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

			assigned-clock-parents = <0>,
						 <0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>;

			assigned-clock-rates = <297000000>, <297000000>;

			ranges;

			sti-compositor@9d11000 {
				compatible = "st,stih407-compositor";
				reg = <0x9d11000 0x1000>;

				clock-names = "compo_main",
					      "compo_aux",
					      "pix_main",
					      "pix_aux",
					      "pix_gdp1",
					      "pix_gdp2",
					      "pix_gdp3",
					      "pix_gdp4",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				reset-names = "compo-main", "compo-aux";
				resets = <&softreset STIH407_COMPO_SOFTRESET>,
					 <&softreset STIH407_COMPO_SOFTRESET>;
				st,vtg = <&vtg_main>, <&vtg_aux>;
			};

			sti-tvout@8d08000 {
				compatible = "st,stih407-tvout";
				reg = <0x8d08000 0x1000>;
				reg-names = "tvout-reg";
				reset-names = "tvout";
				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
				#address-cells = <1>;
				#size-cells = <1>;
				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						  <&clk_s_d0_flexgen CLK_PCM_0>,
						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						  <&clk_s_d2_flexgen CLK_HDDAC>;

				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
							 <&clk_tmdsout_hdmi>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d0_quadfs 0>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d2_quadfs 0>;
				ranges;

				sti-hdmi@8d04000 {
					compatible = "st,stih407-hdmi";
					reg = <0x8d04000 0x1000>;
					reg-names = "hdmi-reg";
					interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
					interrupt-names	= "irq";
					clock-names = "pix",
						      "tmds",
						      "phy",
						      "audio",
						      "main_parent",
						      "aux_parent";

					clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						 <&clk_s_d0_flexgen CLK_PCM_0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>;

					hdmi,hpd-gpio = <&pio5 3>;
					reset-names = "hdmi";
					resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
					ddc = <&hdmiddc>;

				};

				sti-hda@8d02000 {
					compatible = "st,stih407-hda";
					reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
					reg-names = "hda-reg", "video-dacs-ctrl";
					clock-names = "pix",
						      "hddac",
						      "main_parent",
						      "aux_parent";
					clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						 <&clk_s_d2_flexgen CLK_HDDAC>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>;
				};
			};
		};

		bdisp0:bdisp@9f10000 {
			compatible = "st,stih407-bdisp";
			reg = <0x9f10000 0x1000>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
			clock-names = "bdisp";
			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
		};
	};
};
Commit	Line	Data
b16b77a5 PG	1	/*
	2	* Copyright (C) 2014 STMicroelectronics Limited.
	3	* Author: Peter Griffin <peter.griffin@linaro.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
	9	#include "stih410-clock.dtsi"
	10	#include "stih407-family.dtsi"
	11	#include "stih410-pinctrl.dtsi"
	12	/ {
79444509 FD	13	aliases {
	14	bdisp0 = &bdisp0;
	15	};
	16
9d9f65fc PG	17	soc {
	18	usb2_picophy1: phy2 {
	19	compatible = "st,stih407-usb2-phy";
	20	#phy-cells = <0>;
	21	st,syscfg = <&syscfg_core 0xf8 0xf4>;
	22	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	23	<&picophyreset STIH407_PICOPHY0_RESET>;
	24	reset-names = "global", "port";
	25	};
b16b77a5	26
9d9f65fc PG	27	usb2_picophy2: phy3 {
	28	compatible = "st,stih407-usb2-phy";
	29	#phy-cells = <0>;
	30	st,syscfg = <&syscfg_core 0xfc 0xf4>;
	31	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	32	<&picophyreset STIH407_PICOPHY1_RESET>;
	33	reset-names = "global", "port";
	34	};
a59a4d96 PG	35
	36	ohci0: usb@9a03c00 {
	37	compatible = "st,st-ohci-300x";
	38	reg = <0x9a03c00 0x100>;
	39	interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
	40	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
	41	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	42	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	43	reset-names = "power", "softreset";
	44	phys = <&usb2_picophy1>;
	45	phy-names = "usb";
	46	};
	47
	48	ehci0: usb@9a03e00 {
	49	compatible = "st,st-ehci-300x";
	50	reg = <0x9a03e00 0x100>;
	51	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	52	pinctrl-names = "default";
	53	pinctrl-0 = <&pinctrl_usb0>;
	54	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
	55	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	56	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	57	reset-names = "power", "softreset";
	58	phys = <&usb2_picophy1>;
	59	phy-names = "usb";
	60	};
	61
	62	ohci1: usb@9a83c00 {
	63	compatible = "st,st-ohci-300x";
	64	reg = <0x9a83c00 0x100>;
	65	interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
	66	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
	67	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	68	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	69	reset-names = "power", "softreset";
	70	phys = <&usb2_picophy2>;
	71	phy-names = "usb";
	72	};
	73
	74	ehci1: usb@9a83e00 {
	75	compatible = "st,st-ehci-300x";
	76	reg = <0x9a83e00 0x100>;
	77	interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
	78	pinctrl-names = "default";
	79	pinctrl-0 = <&pinctrl_usb1>;
	80	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
	81	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	82	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	83	reset-names = "power", "softreset";
	84	phys = <&usb2_picophy2>;
	85	phy-names = "usb";
	86	};
956b42d1	87
956b42d1 GF	88	sti-display-subsystem {
	89	compatible = "st,sti-display-subsystem";
	90	#address-cells = <1>;
	91	#size-cells = <1>;
	92
	93	assigned-clocks = <&clk_s_d2_quadfs 0>,
	94	<&clk_s_d2_quadfs 0>,
	95	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	96	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	97	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	98	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	99	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	100	<&clk_s_d2_flexgen CLK_PIX_GDP4>;
	101
	102	assigned-clock-parents = <0>,
	103	<0>,
	104	<&clk_s_d2_quadfs 0>,
	105	<&clk_s_d2_quadfs 0>,
	106	<&clk_s_d2_quadfs 0>,
	107	<&clk_s_d2_quadfs 0>,
	108	<&clk_s_d2_quadfs 0>,
	109	<&clk_s_d2_quadfs 0>;
	110
	111	assigned-clock-rates = <297000000>, <297000000>;
	112
	113	ranges;
	114
	115	sti-compositor@9d11000 {
	116	compatible = "st,stih407-compositor";
	117	reg = <0x9d11000 0x1000>;
	118
	119	clock-names = "compo_main",
	120	"compo_aux",
	121	"pix_main",
	122	"pix_aux",
	123	"pix_gdp1",
	124	"pix_gdp2",
	125	"pix_gdp3",
	126	"pix_gdp4",
	127	"main_parent",
	128	"aux_parent";
	129
	130	clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
	131	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	132	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	133	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	134	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	135	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	136	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	137	<&clk_s_d2_flexgen CLK_PIX_GDP4>,
	138	<&clk_s_d2_quadfs 0>,
	139	<&clk_s_d2_quadfs 1>;
	140
	141	reset-names = "compo-main", "compo-aux";
	142	resets = <&softreset STIH407_COMPO_SOFTRESET>,
	143	<&softreset STIH407_COMPO_SOFTRESET>;
	144	st,vtg = <&vtg_main>, <&vtg_aux>;
	145	};
	146
	147	sti-tvout@8d08000 {
	148	compatible = "st,stih407-tvout";
	149	reg = <0x8d08000 0x1000>;
	150	reg-names = "tvout-reg";
	151	reset-names = "tvout";
152	resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
153	#address-cells = <1>;
154	#size-cells = <1>;
155	assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
156	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
157	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
158	<&clk_s_d0_flexgen CLK_PCM_0>,
159	<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
160	<&clk_s_d2_flexgen CLK_HDDAC>;
161
162	assigned-clock-parents = <&clk_s_d2_quadfs 0>,
163	<&clk_tmdsout_hdmi>,
164	<&clk_s_d2_quadfs 0>,
165	<&clk_s_d0_quadfs 0>,
166	<&clk_s_d2_quadfs 0>,
167	<&clk_s_d2_quadfs 0>;
168	ranges;
169
170	sti-hdmi@8d04000 {
171	compatible = "st,stih407-hdmi";
172	reg = <0x8d04000 0x1000>;
173	reg-names = "hdmi-reg";
174	interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
175	interrupt-names = "irq";
176	clock-names = "pix",
177	"tmds",
178	"phy",
179	"audio",
180	"main_parent",
181	"aux_parent";
182
183	clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
184	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
185	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
186	<&clk_s_d0_flexgen CLK_PCM_0>,
187	<&clk_s_d2_quadfs 0>,
188	<&clk_s_d2_quadfs 1>;
189
190	hdmi,hpd-gpio = <&pio5 3>;
191	reset-names = "hdmi";
192	resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
193	ddc = <&hdmiddc>;
194
195	};
196
197	sti-hda@8d02000 {
198	compatible = "st,stih407-hda";
199	reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
200	reg-names = "hda-reg", "video-dacs-ctrl";
201	clock-names = "pix",
202	"hddac",
203	"main_parent",
204	"aux_parent";
205	clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
206	<&clk_s_d2_flexgen CLK_HDDAC>,
207	<&clk_s_d2_quadfs 0>,
208	<&clk_s_d2_quadfs 1>;
209	};
210	};
211	};
79444509 FD	212
	213	bdisp0:bdisp@9f10000 {
	214	compatible = "st,stih407-bdisp";
	215	reg = <0x9f10000 0x1000>;
	216	interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
	217	clock-names = "bdisp";
	218	clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
	219	};
9d9f65fc	220	};
b16b77a5	221	};