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b16b77a5 PG |
1 | /* |
2 | * Copyright (C) 2014 STMicroelectronics Limited. | |
3 | * Author: Peter Griffin <peter.griffin@linaro.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | #include "stih410-clock.dtsi" | |
10 | #include "stih407-family.dtsi" | |
11 | #include "stih410-pinctrl.dtsi" | |
12 | / { | |
79444509 FD |
13 | aliases { |
14 | bdisp0 = &bdisp0; | |
15 | }; | |
16 | ||
9d9f65fc PG |
17 | soc { |
18 | usb2_picophy1: phy2 { | |
19 | compatible = "st,stih407-usb2-phy"; | |
20 | #phy-cells = <0>; | |
21 | st,syscfg = <&syscfg_core 0xf8 0xf4>; | |
22 | resets = <&softreset STIH407_PICOPHY_SOFTRESET>, | |
23 | <&picophyreset STIH407_PICOPHY0_RESET>; | |
24 | reset-names = "global", "port"; | |
25 | }; | |
b16b77a5 | 26 | |
9d9f65fc PG |
27 | usb2_picophy2: phy3 { |
28 | compatible = "st,stih407-usb2-phy"; | |
29 | #phy-cells = <0>; | |
30 | st,syscfg = <&syscfg_core 0xfc 0xf4>; | |
31 | resets = <&softreset STIH407_PICOPHY_SOFTRESET>, | |
32 | <&picophyreset STIH407_PICOPHY1_RESET>; | |
33 | reset-names = "global", "port"; | |
34 | }; | |
a59a4d96 PG |
35 | |
36 | ohci0: usb@9a03c00 { | |
37 | compatible = "st,st-ohci-300x"; | |
38 | reg = <0x9a03c00 0x100>; | |
39 | interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>; | |
40 | clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; | |
41 | resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, | |
42 | <&softreset STIH407_USB2_PORT0_SOFTRESET>; | |
43 | reset-names = "power", "softreset"; | |
44 | phys = <&usb2_picophy1>; | |
45 | phy-names = "usb"; | |
46 | }; | |
47 | ||
48 | ehci0: usb@9a03e00 { | |
49 | compatible = "st,st-ehci-300x"; | |
50 | reg = <0x9a03e00 0x100>; | |
51 | interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; | |
52 | pinctrl-names = "default"; | |
53 | pinctrl-0 = <&pinctrl_usb0>; | |
54 | clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; | |
55 | resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, | |
56 | <&softreset STIH407_USB2_PORT0_SOFTRESET>; | |
57 | reset-names = "power", "softreset"; | |
58 | phys = <&usb2_picophy1>; | |
59 | phy-names = "usb"; | |
60 | }; | |
61 | ||
62 | ohci1: usb@9a83c00 { | |
63 | compatible = "st,st-ohci-300x"; | |
64 | reg = <0x9a83c00 0x100>; | |
65 | interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>; | |
66 | clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; | |
67 | resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, | |
68 | <&softreset STIH407_USB2_PORT1_SOFTRESET>; | |
69 | reset-names = "power", "softreset"; | |
70 | phys = <&usb2_picophy2>; | |
71 | phy-names = "usb"; | |
72 | }; | |
73 | ||
74 | ehci1: usb@9a83e00 { | |
75 | compatible = "st,st-ehci-300x"; | |
76 | reg = <0x9a83e00 0x100>; | |
77 | interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; | |
78 | pinctrl-names = "default"; | |
79 | pinctrl-0 = <&pinctrl_usb1>; | |
80 | clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; | |
81 | resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, | |
82 | <&softreset STIH407_USB2_PORT1_SOFTRESET>; | |
83 | reset-names = "power", "softreset"; | |
84 | phys = <&usb2_picophy2>; | |
85 | phy-names = "usb"; | |
86 | }; | |
956b42d1 GF |
87 | |
88 | /* Display */ | |
89 | vtg_main: sti-vtg-main@8d02800 { | |
90 | compatible = "st,vtg"; | |
91 | reg = <0x8d02800 0x200>; | |
92 | interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; | |
93 | }; | |
94 | ||
95 | vtg_aux: sti-vtg-aux@8d00200 { | |
96 | compatible = "st,vtg"; | |
97 | reg = <0x8d00200 0x100>; | |
98 | interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; | |
99 | }; | |
100 | ||
101 | sti-display-subsystem { | |
102 | compatible = "st,sti-display-subsystem"; | |
103 | #address-cells = <1>; | |
104 | #size-cells = <1>; | |
105 | ||
106 | assigned-clocks = <&clk_s_d2_quadfs 0>, | |
107 | <&clk_s_d2_quadfs 0>, | |
108 | <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, | |
109 | <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, | |
110 | <&clk_s_d2_flexgen CLK_PIX_GDP1>, | |
111 | <&clk_s_d2_flexgen CLK_PIX_GDP2>, | |
112 | <&clk_s_d2_flexgen CLK_PIX_GDP3>, | |
113 | <&clk_s_d2_flexgen CLK_PIX_GDP4>; | |
114 | ||
115 | assigned-clock-parents = <0>, | |
116 | <0>, | |
117 | <&clk_s_d2_quadfs 0>, | |
118 | <&clk_s_d2_quadfs 0>, | |
119 | <&clk_s_d2_quadfs 0>, | |
120 | <&clk_s_d2_quadfs 0>, | |
121 | <&clk_s_d2_quadfs 0>, | |
122 | <&clk_s_d2_quadfs 0>; | |
123 | ||
124 | assigned-clock-rates = <297000000>, <297000000>; | |
125 | ||
126 | ranges; | |
127 | ||
128 | sti-compositor@9d11000 { | |
129 | compatible = "st,stih407-compositor"; | |
130 | reg = <0x9d11000 0x1000>; | |
131 | ||
132 | clock-names = "compo_main", | |
133 | "compo_aux", | |
134 | "pix_main", | |
135 | "pix_aux", | |
136 | "pix_gdp1", | |
137 | "pix_gdp2", | |
138 | "pix_gdp3", | |
139 | "pix_gdp4", | |
140 | "main_parent", | |
141 | "aux_parent"; | |
142 | ||
143 | clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, | |
144 | <&clk_s_c0_flexgen CLK_COMPO_DVP>, | |
145 | <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, | |
146 | <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, | |
147 | <&clk_s_d2_flexgen CLK_PIX_GDP1>, | |
148 | <&clk_s_d2_flexgen CLK_PIX_GDP2>, | |
149 | <&clk_s_d2_flexgen CLK_PIX_GDP3>, | |
150 | <&clk_s_d2_flexgen CLK_PIX_GDP4>, | |
151 | <&clk_s_d2_quadfs 0>, | |
152 | <&clk_s_d2_quadfs 1>; | |
153 | ||
154 | reset-names = "compo-main", "compo-aux"; | |
155 | resets = <&softreset STIH407_COMPO_SOFTRESET>, | |
156 | <&softreset STIH407_COMPO_SOFTRESET>; | |
157 | st,vtg = <&vtg_main>, <&vtg_aux>; | |
158 | }; | |
159 | ||
160 | sti-tvout@8d08000 { | |
161 | compatible = "st,stih407-tvout"; | |
162 | reg = <0x8d08000 0x1000>; | |
163 | reg-names = "tvout-reg"; | |
164 | reset-names = "tvout"; | |
165 | resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <1>; | |
168 | assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, | |
169 | <&clk_s_d2_flexgen CLK_TMDS_HDMI>, | |
170 | <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, | |
171 | <&clk_s_d0_flexgen CLK_PCM_0>, | |
172 | <&clk_s_d2_flexgen CLK_PIX_HDDAC>, | |
173 | <&clk_s_d2_flexgen CLK_HDDAC>; | |
174 | ||
175 | assigned-clock-parents = <&clk_s_d2_quadfs 0>, | |
176 | <&clk_tmdsout_hdmi>, | |
177 | <&clk_s_d2_quadfs 0>, | |
178 | <&clk_s_d0_quadfs 0>, | |
179 | <&clk_s_d2_quadfs 0>, | |
180 | <&clk_s_d2_quadfs 0>; | |
181 | ranges; | |
182 | ||
183 | sti-hdmi@8d04000 { | |
184 | compatible = "st,stih407-hdmi"; | |
185 | reg = <0x8d04000 0x1000>; | |
186 | reg-names = "hdmi-reg"; | |
187 | interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>; | |
188 | interrupt-names = "irq"; | |
189 | clock-names = "pix", | |
190 | "tmds", | |
191 | "phy", | |
192 | "audio", | |
193 | "main_parent", | |
194 | "aux_parent"; | |
195 | ||
196 | clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, | |
197 | <&clk_s_d2_flexgen CLK_TMDS_HDMI>, | |
198 | <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, | |
199 | <&clk_s_d0_flexgen CLK_PCM_0>, | |
200 | <&clk_s_d2_quadfs 0>, | |
201 | <&clk_s_d2_quadfs 1>; | |
202 | ||
203 | hdmi,hpd-gpio = <&pio5 3>; | |
204 | reset-names = "hdmi"; | |
205 | resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; | |
206 | ddc = <&hdmiddc>; | |
207 | ||
208 | }; | |
209 | ||
210 | sti-hda@8d02000 { | |
211 | compatible = "st,stih407-hda"; | |
212 | reg = <0x8d02000 0x400>, <0x92b0120 0x4>; | |
213 | reg-names = "hda-reg", "video-dacs-ctrl"; | |
214 | clock-names = "pix", | |
215 | "hddac", | |
216 | "main_parent", | |
217 | "aux_parent"; | |
218 | clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, | |
219 | <&clk_s_d2_flexgen CLK_HDDAC>, | |
220 | <&clk_s_d2_quadfs 0>, | |
221 | <&clk_s_d2_quadfs 1>; | |
222 | }; | |
223 | }; | |
224 | }; | |
79444509 FD |
225 | |
226 | bdisp0:bdisp@9f10000 { | |
227 | compatible = "st,stih407-bdisp"; | |
228 | reg = <0x9f10000 0x1000>; | |
229 | interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>; | |
230 | clock-names = "bdisp"; | |
231 | clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; | |
232 | }; | |
9d9f65fc | 233 | }; |
b16b77a5 | 234 | }; |