[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / stih410.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
/ {
	aliases {
		bdisp0 = &bdisp0;
	};

	soc {
		usb2_picophy1: phy2 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xf8 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY0_RESET>;
			reset-names = "global", "port";

			status = "disabled";
		};

		usb2_picophy2: phy3 {
			compatible = "st,stih407-usb2-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xfc 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY1_RESET>;
			reset-names = "global", "port";

			status = "disabled";
		};

		ohci0: usb@9a03c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a03c00 0x100>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci0: usb@9a03e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a03e00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ohci1: usb@9a83c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a83c00 0x100>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci1: usb@9a83e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a83e00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		sti-display-subsystem {
			compatible = "st,sti-display-subsystem";
			#address-cells = <1>;
			#size-cells = <1>;

			assigned-clocks	= <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_quadfs 1>,
					  <&clk_s_c0_pll1 0>,
					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

			assigned-clock-parents = <0>,
						 <0>,
						 <0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>;

			assigned-clock-rates = <297000000>,
					       <297000000>,
					       <0>,
					       <400000000>,
					       <400000000>;

			ranges;

			sti-compositor@9d11000 {
				compatible = "st,stih407-compositor";
				reg = <0x9d11000 0x1000>;

				clock-names = "compo_main",
					      "compo_aux",
					      "pix_main",
					      "pix_aux",
					      "pix_gdp1",
					      "pix_gdp2",
					      "pix_gdp3",
					      "pix_gdp4",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				reset-names = "compo-main", "compo-aux";
				resets = <&softreset STIH407_COMPO_SOFTRESET>,
					 <&softreset STIH407_COMPO_SOFTRESET>;
				st,vtg = <&vtg_main>, <&vtg_aux>;
			};

			sti-tvout@8d08000 {
				compatible = "st,stih407-tvout";
				reg = <0x8d08000 0x1000>;
				reg-names = "tvout-reg";
				reset-names = "tvout";
				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
				#address-cells = <1>;
				#size-cells = <1>;
				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						  <&clk_s_d0_flexgen CLK_PCM_0>,
						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						  <&clk_s_d2_flexgen CLK_HDDAC>;

				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
							 <&clk_tmdsout_hdmi>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d0_quadfs 0>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d2_quadfs 0>;
			};

			sti_hdmi: sti-hdmi@8d04000 {
				compatible = "st,stih407-hdmi";
				reg = <0x8d04000 0x1000>;
				reg-names = "hdmi-reg";
				interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
				interrupt-names	= "irq";
				clock-names = "pix",
					      "tmds",
					      "phy",
					      "audio",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
					 <&clk_s_d0_flexgen CLK_PCM_0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				hdmi,hpd-gpio = <&pio5 3>;
				reset-names = "hdmi";
				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
				ddc = <&hdmiddc>;
			};

			sti-hda@8d02000 {
				compatible = "st,stih407-hda";
				status = "disabled";
				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
				reg-names = "hda-reg", "video-dacs-ctrl";
				clock-names = "pix",
					      "hddac",
					      "main_parent",
					      "aux_parent";
				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
					 <&clk_s_d2_flexgen CLK_HDDAC>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;
			};

			sti-hqvdp@9c000000 {
				compatible = "st,stih407-hqvdp";
				reg = <0x9C00000 0x100000>;
				clock-names = "hqvdp", "pix_main";
				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
				reset-names = "hqvdp";
				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
				st,vtg = <&vtg_main>;
			};
		};

		bdisp0:bdisp@9f10000 {
			compatible = "st,stih407-bdisp";
			reg = <0x9f10000 0x1000>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
			clock-names = "bdisp";
			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
		};

		hva@8c85000 {
			compatible = "st,st-hva";
			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
			reg-names = "hva_registers", "hva_esram";
			interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
				     <GIC_SPI 59 IRQ_TYPE_NONE>;
			clock-names = "clk_hva";
			clocks = <&clk_s_c0_flexgen CLK_HVA>;
		};

		thermal@91a0000 {
			compatible = "st,stih407-thermal";
			reg = <0x91a0000 0x28>;
			clock-names = "thermal";
			clocks = <&clk_sysin>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
		};

		delta0 {
			compatible = "st,st-delta";
			clock-names = "delta",
				      "delta-st231",
				      "delta-flash-promip";
			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
				 <&clk_s_c0_flexgen CLK_ST231_DMU>,
				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
		};

		sti-cec@094a087c {
			compatible = "st,stih-cec";
			reg = <0x94a087c 0x64>;
			clocks = <&clk_sysin>;
			clock-names = "cec-clk";
			interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
			interrupt-names = "cec-irq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_cec0_default>;
			resets = <&softreset STIH407_LPM_SOFTRESET>;
			hdmi-phandle = <&sti_hdmi>;
		};
	};
};
Commit	Line	Data
b16b77a5 PG	1	/*
	2	* Copyright (C) 2014 STMicroelectronics Limited.
	3	* Author: Peter Griffin <peter.griffin@linaro.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
	9	#include "stih410-clock.dtsi"
	10	#include "stih407-family.dtsi"
	11	#include "stih410-pinctrl.dtsi"
	12	/ {
79444509 FD	13	aliases {
	14	bdisp0 = &bdisp0;
	15	};
	16
9d9f65fc PG	17	soc {
	18	usb2_picophy1: phy2 {
	19	compatible = "st,stih407-usb2-phy";
	20	#phy-cells = <0>;
	21	st,syscfg = <&syscfg_core 0xf8 0xf4>;
	22	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	23	<&picophyreset STIH407_PICOPHY0_RESET>;
	24	reset-names = "global", "port";
b771ae27 MC	25
b771ae27 MC	26	status = "disabled";
9d9f65fc	27	};
b16b77a5	28
9d9f65fc PG	29	usb2_picophy2: phy3 {
	30	compatible = "st,stih407-usb2-phy";
	31	#phy-cells = <0>;
	32	st,syscfg = <&syscfg_core 0xfc 0xf4>;
	33	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	34	<&picophyreset STIH407_PICOPHY1_RESET>;
	35	reset-names = "global", "port";
b771ae27 MC	36
b771ae27 MC	37	status = "disabled";
9d9f65fc	38	};
a59a4d96 PG	39
	40	ohci0: usb@9a03c00 {
	41	compatible = "st,st-ohci-300x";
	42	reg = <0x9a03c00 0x100>;
	43	interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
7e9d2850 LJ	44	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	45	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	46	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	47	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	48	reset-names = "power", "softreset";
	49	phys = <&usb2_picophy1>;
	50	phy-names = "usb";
b771ae27 MC	51
b771ae27 MC	52	status = "disabled";
a59a4d96 PG	53	};
	54
	55	ehci0: usb@9a03e00 {
	56	compatible = "st,st-ehci-300x";
	57	reg = <0x9a03e00 0x100>;
	58	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	59	pinctrl-names = "default";
	60	pinctrl-0 = <&pinctrl_usb0>;
7e9d2850 LJ	61	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	62	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	63	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	64	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	65	reset-names = "power", "softreset";
	66	phys = <&usb2_picophy1>;
	67	phy-names = "usb";
b771ae27 MC	68
b771ae27 MC	69	status = "disabled";
a59a4d96 PG	70	};
	71
	72	ohci1: usb@9a83c00 {
	73	compatible = "st,st-ohci-300x";
	74	reg = <0x9a83c00 0x100>;
	75	interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
7e9d2850 LJ	76	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	77	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	78	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	79	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	80	reset-names = "power", "softreset";
	81	phys = <&usb2_picophy2>;
	82	phy-names = "usb";
b771ae27 MC	83
b771ae27 MC	84	status = "disabled";
a59a4d96 PG	85	};
	86
	87	ehci1: usb@9a83e00 {
	88	compatible = "st,st-ehci-300x";
	89	reg = <0x9a83e00 0x100>;
	90	interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
	91	pinctrl-names = "default";
	92	pinctrl-0 = <&pinctrl_usb1>;
7e9d2850 LJ	93	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	94	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	95	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	96	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	97	reset-names = "power", "softreset";
	98	phys = <&usb2_picophy2>;
	99	phy-names = "usb";
956b42d1	100
b771ae27	101	status = "disabled";
956b42d1 GF	102	};
	103
	104	sti-display-subsystem {
	105	compatible = "st,sti-display-subsystem";
	106	#address-cells = <1>;
	107	#size-cells = <1>;
	108
	109	assigned-clocks = <&clk_s_d2_quadfs 0>,
3a74152c GF	110	<&clk_s_d2_quadfs 1>,
	111	<&clk_s_c0_pll1 0>,
	112	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	113	<&clk_s_c0_flexgen CLK_MAIN_DISP>,
956b42d1 GF	114	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	115	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	116	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	117	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	118	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	119	<&clk_s_d2_flexgen CLK_PIX_GDP4>;
	120
	121	assigned-clock-parents = <0>,
	122	<0>,
3a74152c GF	123	<0>,
	124	<&clk_s_c0_pll1 0>,
	125	<&clk_s_c0_pll1 0>,
956b42d1	126	<&clk_s_d2_quadfs 0>,
3a74152c	127	<&clk_s_d2_quadfs 1>,
956b42d1 GF	128	<&clk_s_d2_quadfs 0>,
	129	<&clk_s_d2_quadfs 0>,
	130	<&clk_s_d2_quadfs 0>,
	131	<&clk_s_d2_quadfs 0>;
	132
3a74152c	133	assigned-clock-rates = <297000000>,
b9ec866d	134	<297000000>,
3a74152c GF	135	<0>,
	136	<400000000>,
	137	<400000000>;
956b42d1 GF	138
	139	ranges;
	140
	141	sti-compositor@9d11000 {
	142	compatible = "st,stih407-compositor";
	143	reg = <0x9d11000 0x1000>;
	144
	145	clock-names = "compo_main",
	146	"compo_aux",
	147	"pix_main",
	148	"pix_aux",
	149	"pix_gdp1",
	150	"pix_gdp2",
	151	"pix_gdp3",
	152	"pix_gdp4",
	153	"main_parent",
	154	"aux_parent";
	155
	156	clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
	157	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	158	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	159	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	160	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	161	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	162	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	163	<&clk_s_d2_flexgen CLK_PIX_GDP4>,
	164	<&clk_s_d2_quadfs 0>,
	165	<&clk_s_d2_quadfs 1>;
	166
	167	reset-names = "compo-main", "compo-aux";
	168	resets = <&softreset STIH407_COMPO_SOFTRESET>,
	169	<&softreset STIH407_COMPO_SOFTRESET>;
	170	st,vtg = <&vtg_main>, <&vtg_aux>;
	171	};
	172
	173	sti-tvout@8d08000 {
	174	compatible = "st,stih407-tvout";
	175	reg = <0x8d08000 0x1000>;
	176	reg-names = "tvout-reg";
	177	reset-names = "tvout";
	178	resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
	179	#address-cells = <1>;
	180	#size-cells = <1>;
	181	assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
	182	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
	183	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
	184	<&clk_s_d0_flexgen CLK_PCM_0>,
	185	<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
	186	<&clk_s_d2_flexgen CLK_HDDAC>;
	187
	188	assigned-clock-parents = <&clk_s_d2_quadfs 0>,
	189	<&clk_tmdsout_hdmi>,
	190	<&clk_s_d2_quadfs 0>,
	191	<&clk_s_d0_quadfs 0>,
	192	<&clk_s_d2_quadfs 0>,
	193	<&clk_s_d2_quadfs 0>;
79a313f5 BG	194	};
79a313f5 BG	195
24595472	196	sti_hdmi: sti-hdmi@8d04000 {
79a313f5 BG	197	compatible = "st,stih407-hdmi";
	198	reg = <0x8d04000 0x1000>;
	199	reg-names = "hdmi-reg";
	200	interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
	201	interrupt-names = "irq";
	202	clock-names = "pix",
	203	"tmds",
	204	"phy",
	205	"audio",
	206	"main_parent",
	207	"aux_parent";
	208
	209	clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
	210	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
	211	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
	212	<&clk_s_d0_flexgen CLK_PCM_0>,
	213	<&clk_s_d2_quadfs 0>,
	214	<&clk_s_d2_quadfs 1>;
	215
	216	hdmi,hpd-gpio = <&pio5 3>;
	217	reset-names = "hdmi";
	218	resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
	219	ddc = <&hdmiddc>;
	220	};
	221
	222	sti-hda@8d02000 {
	223	compatible = "st,stih407-hda";
9d65f902	224	status = "disabled";
79a313f5 BG	225	reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
	226	reg-names = "hda-reg", "video-dacs-ctrl";
	227	clock-names = "pix",
	228	"hddac",
	229	"main_parent",
	230	"aux_parent";
	231	clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
	232	<&clk_s_d2_flexgen CLK_HDDAC>,
	233	<&clk_s_d2_quadfs 0>,
	234	<&clk_s_d2_quadfs 1>;
956b42d1	235	};
241a6878 PC	236
	237	sti-hqvdp@9c000000 {
	238	compatible = "st,stih407-hqvdp";
	239	reg = <0x9C00000 0x100000>;
	240	clock-names = "hqvdp", "pix_main";
	241	clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
	242	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
	243	reset-names = "hqvdp";
	244	resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
	245	st,vtg = <&vtg_main>;
	246	};
956b42d1	247	};
79444509 FD	248
	249	bdisp0:bdisp@9f10000 {
	250	compatible = "st,stih407-bdisp";
	251	reg = <0x9f10000 0x1000>;
	252	interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
	253	clock-names = "bdisp";
	254	clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
	255	};
70bc0f3a	256
390aafe3 JCT	257	hva@8c85000 {
	258	compatible = "st,st-hva";
	259	reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
	260	reg-names = "hva_registers", "hva_esram";
	261	interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
	262	<GIC_SPI 59 IRQ_TYPE_NONE>;
	263	clock-names = "clk_hva";
	264	clocks = <&clk_s_c0_flexgen CLK_HVA>;
	265	};
	266
70bc0f3a PC	267	thermal@91a0000 {
	268	compatible = "st,stih407-thermal";
	269	reg = <0x91a0000 0x28>;
	270	clock-names = "thermal";
	271	clocks = <&clk_sysin>;
	272	interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
	273	};
b005ebf9 HF	274
	275	delta0 {
	276	compatible = "st,st-delta";
	277	clock-names = "delta",
	278	"delta-st231",
	279	"delta-flash-promip";
	280	clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
	281	<&clk_s_c0_flexgen CLK_ST231_DMU>,
	282	<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
	283	};
ed3022de BG	284
	285	sti-cec@094a087c {
	286	compatible = "st,stih-cec";
	287	reg = <0x94a087c 0x64>;
	288	clocks = <&clk_sysin>;
	289	clock-names = "cec-clk";
	290	interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
	291	interrupt-names = "cec-irq";
	292	pinctrl-names = "default";
	293	pinctrl-0 = <&pinctrl_cec0_default>;
	294	resets = <&softreset STIH407_LPM_SOFTRESET>;
	295	hdmi-phandle = <&sti_hdmi>;
	296	};
9d9f65fc	297	};
b16b77a5	298	};