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65ebcc11 SK |
1 | /* |
2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. | |
3 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | #include "stih41x.dtsi" | |
10 | #include "stih415-clock.dtsi" | |
11 | #include "stih415-pinctrl.dtsi" | |
5bbb7527 | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
6b7f06cc | 13 | #include <dt-bindings/reset-controller/stih415-resets.h> |
65ebcc11 SK |
14 | / { |
15 | ||
16 | L2: cache-controller { | |
17 | compatible = "arm,pl310-cache"; | |
18 | reg = <0xfffe2000 0x1000>; | |
19 | arm,data-latency = <3 2 2>; | |
20 | arm,tag-latency = <1 1 1>; | |
21 | cache-unified; | |
22 | cache-level = <2>; | |
23 | }; | |
24 | ||
25 | soc { | |
26 | #address-cells = <1>; | |
27 | #size-cells = <1>; | |
28 | interrupt-parent = <&intc>; | |
29 | ranges; | |
30 | compatible = "simple-bus"; | |
31 | ||
6b7f06cc SK |
32 | powerdown: powerdown-controller { |
33 | #reset-cells = <1>; | |
34 | compatible = "st,stih415-powerdown"; | |
35 | }; | |
36 | ||
fc58fcf6 SK |
37 | softreset: softreset-controller { |
38 | #reset-cells = <1>; | |
39 | compatible = "st,stih415-softreset"; | |
40 | }; | |
41 | ||
65ebcc11 SK |
42 | syscfg_sbc: sbc-syscfg@fe600000{ |
43 | compatible = "st,stih415-sbc-syscfg", "syscon"; | |
44 | reg = <0xfe600000 0xb4>; | |
45 | }; | |
46 | ||
47 | syscfg_front: front-syscfg@fee10000{ | |
48 | compatible = "st,stih415-front-syscfg", "syscon"; | |
49 | reg = <0xfee10000 0x194>; | |
50 | }; | |
51 | ||
52 | syscfg_rear: rear-syscfg@fe830000{ | |
53 | compatible = "st,stih415-rear-syscfg", "syscon"; | |
54 | reg = <0xfe830000 0x190>; | |
55 | }; | |
56 | ||
57 | /* MPE syscfgs */ | |
58 | syscfg_left: left-syscfg@fd690000{ | |
59 | compatible = "st,stih415-left-syscfg", "syscon"; | |
60 | reg = <0xfd690000 0x78>; | |
61 | }; | |
62 | ||
63 | syscfg_right: right-syscfg@fd320000{ | |
64 | compatible = "st,stih415-right-syscfg", "syscon"; | |
65 | reg = <0xfd320000 0x180>; | |
66 | }; | |
67 | ||
68 | syscfg_system: system-syscfg@fdde0000 { | |
69 | compatible = "st,stih415-system-syscfg", "syscon"; | |
70 | reg = <0xfdde0000 0x15c>; | |
71 | }; | |
72 | ||
73 | syscfg_lpm: lpm-syscfg@fe4b5100{ | |
74 | compatible = "st,stih415-lpm-syscfg", "syscon"; | |
75 | reg = <0xfe4b5100 0x08>; | |
76 | }; | |
77 | ||
78 | serial2: serial@fed32000 { | |
79 | compatible = "st,asc"; | |
80 | status = "disabled"; | |
81 | reg = <0xfed32000 0x2c>; | |
82 | interrupts = <0 197 0>; | |
83 | pinctrl-names = "default"; | |
84 | pinctrl-0 = <&pinctrl_serial2>; | |
f317e689 | 85 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
65ebcc11 SK |
86 | }; |
87 | ||
88 | /* SBC comms block ASCs in SASG1 */ | |
89 | sbc_serial1: serial@fe531000 { | |
90 | compatible = "st,asc"; | |
91 | status = "disabled"; | |
92 | reg = <0xfe531000 0x2c>; | |
93 | interrupts = <0 210 0>; | |
ed3593f9 | 94 | clocks = <&clk_sysin>; |
65ebcc11 SK |
95 | pinctrl-names = "default"; |
96 | pinctrl-0 = <&pinctrl_sbc_serial1>; | |
97 | }; | |
5bbb7527 MC |
98 | |
99 | i2c@fed40000 { | |
100 | compatible = "st,comms-ssc4-i2c"; | |
101 | reg = <0xfed40000 0x110>; | |
102 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
f317e689 | 103 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
5bbb7527 MC |
104 | clock-names = "ssc"; |
105 | clock-frequency = <400000>; | |
106 | pinctrl-names = "default"; | |
107 | pinctrl-0 = <&pinctrl_i2c0_default>; | |
108 | ||
109 | status = "disabled"; | |
110 | }; | |
111 | ||
112 | i2c@fed41000 { | |
113 | compatible = "st,comms-ssc4-i2c"; | |
114 | reg = <0xfed41000 0x110>; | |
115 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
f317e689 | 116 | clocks = <&clk_s_a0_ls CLK_ICN_REG>; |
5bbb7527 MC |
117 | clock-names = "ssc"; |
118 | clock-frequency = <400000>; | |
119 | pinctrl-names = "default"; | |
120 | pinctrl-0 = <&pinctrl_i2c1_default>; | |
121 | ||
122 | status = "disabled"; | |
123 | }; | |
124 | ||
125 | i2c@fe540000 { | |
126 | compatible = "st,comms-ssc4-i2c"; | |
127 | reg = <0xfe540000 0x110>; | |
128 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; | |
ed3593f9 | 129 | clocks = <&clk_sysin>; |
5bbb7527 MC |
130 | clock-names = "ssc"; |
131 | clock-frequency = <400000>; | |
132 | pinctrl-names = "default"; | |
133 | pinctrl-0 = <&pinctrl_sbc_i2c0_default>; | |
134 | ||
135 | status = "disabled"; | |
136 | }; | |
137 | ||
138 | i2c@fe541000 { | |
139 | compatible = "st,comms-ssc4-i2c"; | |
140 | reg = <0xfe541000 0x110>; | |
141 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; | |
ed3593f9 | 142 | clocks = <&clk_sysin>; |
5bbb7527 MC |
143 | clock-names = "ssc"; |
144 | clock-frequency = <400000>; | |
145 | pinctrl-names = "default"; | |
146 | pinctrl-0 = <&pinctrl_sbc_i2c1_default>; | |
147 | ||
148 | status = "disabled"; | |
149 | }; | |
c80fe335 SK |
150 | |
151 | ethernet0: dwmac@fe810000 { | |
152 | device_type = "network"; | |
153 | compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; | |
154 | status = "disabled"; | |
155 | ||
156 | reg = <0xfe810000 0x8000>, <0x148 0x4>; | |
157 | reg-names = "stmmaceth", "sti-ethconf"; | |
158 | ||
159 | interrupts = <0 147 0>, <0 148 0>, <0 149 0>; | |
160 | interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; | |
161 | resets = <&softreset STIH415_ETH0_SOFTRESET>; | |
162 | reset-names = "stmmaceth"; | |
163 | ||
164 | snps,pbl = <32>; | |
165 | snps,mixed-burst; | |
166 | snps,force_sf_dma_mode; | |
167 | ||
168 | st,syscon = <&syscfg_rear>; | |
169 | ||
170 | pinctrl-names = "default"; | |
171 | pinctrl-0 = <&pinctrl_mii0>; | |
172 | clock-names = "stmmaceth"; | |
f317e689 | 173 | clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; |
c80fe335 SK |
174 | }; |
175 | ||
176 | ethernet1: dwmac@fef08000 { | |
177 | device_type = "network"; | |
178 | compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; | |
179 | status = "disabled"; | |
180 | reg = <0xfef08000 0x8000>, <0x74 0x4>; | |
181 | reg-names = "stmmaceth", "sti-ethconf"; | |
182 | interrupts = <0 150 0>, <0 151 0>, <0 152 0>; | |
183 | interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; | |
184 | ||
185 | snps,pbl = <32>; | |
186 | snps,mixed-burst; | |
187 | snps,force_sf_dma_mode; | |
188 | ||
189 | st,syscon = <&syscfg_sbc>; | |
190 | ||
191 | resets = <&softreset STIH415_ETH1_SOFTRESET>; | |
192 | reset-names = "stmmaceth"; | |
193 | pinctrl-names = "default"; | |
194 | pinctrl-0 = <&pinctrl_mii1>; | |
195 | clock-names = "stmmaceth"; | |
f317e689 | 196 | clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; |
c80fe335 | 197 | }; |
8ccd3f3a SK |
198 | |
199 | rc: rc@fe518000 { | |
200 | compatible = "st,comms-irb"; | |
201 | reg = <0xfe518000 0x234>; | |
202 | interrupts = <0 203 0>; | |
ed3593f9 | 203 | clocks = <&clk_sysin>; |
8ccd3f3a SK |
204 | rx-mode = "infrared"; |
205 | pinctrl-names = "default"; | |
206 | pinctrl-0 = <&pinctrl_ir>; | |
207 | resets = <&softreset STIH415_IRB_SOFTRESET>; | |
208 | }; | |
c316d7d4 GF |
209 | |
210 | keyscan: keyscan@fe4b0000 { | |
211 | compatible = "st,sti-keyscan"; | |
212 | status = "disabled"; | |
213 | reg = <0xfe4b0000 0x2000>; | |
214 | interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; | |
ed3593f9 | 215 | clocks = <&clk_sysin>; |
c316d7d4 GF |
216 | pinctrl-names = "default"; |
217 | pinctrl-0 = <&pinctrl_keyscan>; | |
218 | resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, | |
219 | <&softreset STIH415_KEYSCAN_SOFTRESET>; | |
220 | }; | |
65ebcc11 SK |
221 | }; |
222 | }; |