[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / stih416.dtsi

/*
 * Copyright (C) 2012 STMicroelectronics Limited.
 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"

#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
	L2: cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0xfffe2000 0x1000>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		cache-unified;
		cache-level = <2>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;
		compatible	= "simple-bus";

		restart {
			compatible = "st,stih416-restart";
			st,syscfg = <&syscfg_sbc>;
			status = "okay";
		};

		powerdown: powerdown-controller {
			#reset-cells = <1>;
			compatible = "st,stih416-powerdown";
		};

		softreset: softreset-controller {
			#reset-cells = <1>;
			compatible = "st,stih416-softreset";
		};

		syscfg_sbc:sbc-syscfg@fe600000{
			compatible	= "st,stih416-sbc-syscfg", "syscon";
			reg		= <0xfe600000 0x1000>;
		};

		syscfg_front:front-syscfg@fee10000{
			compatible	= "st,stih416-front-syscfg", "syscon";
			reg		= <0xfee10000 0x1000>;
		};

		syscfg_rear:rear-syscfg@fe830000{
			compatible	= "st,stih416-rear-syscfg", "syscon";
			reg		= <0xfe830000 0x1000>;
		};

		/* MPE */
		syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
			compatible	= "st,stih416-fvdp-fe-syscfg", "syscon";
			reg		= <0xfddf0000 0x1000>;
		};

		syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
			compatible	= "st,stih416-fvdp-lite-syscfg", "syscon";
			reg		= <0xfd6a0000 0x1000>;
		};

		syscfg_cpu:cpu-syscfg@fdde0000{
			compatible	= "st,stih416-cpu-syscfg", "syscon";
			reg		= <0xfdde0000 0x1000>;
		};

		syscfg_compo:compo-syscfg@fd320000{
			compatible	= "st,stih416-compo-syscfg", "syscon";
			reg		= <0xfd320000 0x1000>;
		};

		syscfg_transport:transport-syscfg@fd690000{
			compatible	= "st,stih416-transport-syscfg", "syscon";
			reg		= <0xfd690000 0x1000>;
		};

		syscfg_lpm:lpm-syscfg@fe4b5100{
			compatible	= "st,stih416-lpm-syscfg", "syscon";
			reg		= <0xfe4b5100 0x8>;
		};

		serial2: serial@fed32000{
			compatible	= "st,asc";
			status 		= "disabled";
			reg		= <0xfed32000 0x2c>;
			interrupts	= <0 197 0>;
			clocks 		= <&clk_s_a0_ls CLK_ICN_REG>;
			pinctrl-names 	= "default";
			pinctrl-0 	= <&pinctrl_serial2 &pinctrl_serial2_oe>;
		};

		/* SBC_UART1 */
		sbc_serial1: serial@fe531000 {
			compatible	= "st,asc";
			status 		= "disabled";
			reg		= <0xfe531000 0x2c>;
			interrupts	= <0 210 0>;
			pinctrl-names 	= "default";
			pinctrl-0 	= <&pinctrl_sbc_serial1>;
			clocks		= <&clk_sysin>;
		};

		i2c@fed40000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfed40000 0x110>;
			interrupts	= <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks 		= <&clk_s_a0_ls CLK_ICN_REG>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_i2c0_default>;

			status		= "disabled";
		};

		i2c@fed41000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfed41000 0x110>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks 		= <&clk_s_a0_ls CLK_ICN_REG>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_i2c1_default>;

			status		= "disabled";
		};

		i2c@fe540000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfe540000 0x110>;
			interrupts	= <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			clocks		= <&clk_sysin>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_sbc_i2c0_default>;

			status		= "disabled";
		};

		i2c@fe541000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfe541000 0x110>;
			interrupts	= <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks		= <&clk_sysin>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_sbc_i2c1_default>;

			status		= "disabled";
		};

		ethernet0: dwmac@fe810000 {
			device_type 	= "network";
			compatible	= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
			status 		= "disabled";
			reg		= <0xfe810000 0x8000>;
			reg-names	= "stmmaceth";

			interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

			snps,pbl 	= <32>;
			snps,mixed-burst;

			st,syscon		= <&syscfg_rear 0x8bc>;
			resets			= <&softreset STIH416_ETH0_SOFTRESET>;
			reset-names		= "stmmaceth";
			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_mii0>;
			clock-names	= "stmmaceth", "sti-ethclk";
			clocks		= <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
		};

		ethernet1: dwmac@fef08000 {
			device_type = "network";
			compatible		= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
			status 		= "disabled";
			reg		= <0xfef08000 0x8000>;
			reg-names	= "stmmaceth";
			interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

			snps,pbl	= <32>;
			snps,mixed-burst;

			st,syscon	= <&syscfg_sbc 0x7f0>;

			resets		= <&softreset STIH416_ETH1_SOFTRESET>;
			reset-names	= "stmmaceth";
			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_mii1>;
			clock-names	= "stmmaceth", "sti-ethclk";
			clocks		= <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
		};

		rc: rc@fe518000 {
			compatible	= "st,comms-irb";
			reg		= <0xfe518000 0x234>;
			interrupts	=  <0 203 0>;
			rx-mode         = "infrared";
			clocks		= <&clk_sysin>;
			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_ir>;
			resets		= <&softreset STIH416_IRB_SOFTRESET>;
		};

		/* FSM */
		spifsm: spifsm@fe902000 {
			compatible	   = "st,spi-fsm";
			reg		   = <0xfe902000 0x1000>;
			pinctrl-0	   = <&pinctrl_fsm>;

			st,syscfg	   = <&syscfg_rear>;
			st,boot-device-reg = <0x958>;
			st,boot-device-spi = <0x1a>;

			status = "disabled";
		};

		keyscan: keyscan@fe4b0000 {
			compatible = "st,sti-keyscan";
			status = "disabled";
			reg = <0xfe4b0000 0x2000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
			clocks = <&clk_sysin>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_keyscan>;
			resets	= <&powerdown STIH416_KEYSCAN_POWERDOWN>,
				  <&softreset STIH416_KEYSCAN_SOFTRESET>;
		};

		temp0 {
			compatible = "st,stih416-sas-thermal";
			clock-names = "thermal";
			clocks = <&clockgen_c_vcc 14>;

			status = "okay";
		};

		temp1@fdfe8000 {
			compatible = "st,stih416-mpe-thermal";
			reg = <0xfdfe8000 0x10>;
			clocks = <&clockgen_e 3>;
			clock-names = "thermal";
			interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;

			status = "okay";
		};

		mmc0: sdhci@fe81e000 {
			compatible	= "st,sdhci";
			status		= "disabled";
			reg		= <0xfe81e000 0x1000>;
			interrupts	= <GIC_SPI 127 IRQ_TYPE_NONE>;
			interrupt-names	= "mmcirq";
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_mmc0>;
			clock-names	= "mmc";
			clocks		= <&clk_s_a1_ls 1>;
		};

		mmc1: sdhci@fe81f000 {
			compatible	= "st,sdhci";
			status		= "disabled";
			reg		= <0xfe81f000 0x1000>;
			interrupts	= <GIC_SPI 128 IRQ_TYPE_NONE>;
			interrupt-names	= "mmcirq";
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_mmc1>;
			clock-names	= "mmc";
			clocks		= <&clk_s_a1_ls 8>;
		};

		miphy365x_phy: phy@fe382000 {
			compatible      = "st,miphy365x-phy";
			st,syscfg	= <&syscfg_rear 0x824 0x828>;
			#address-cells	= <1>;
			#size-cells	= <1>;
			ranges;

			phy_port0: port@fe382000 {
				#phy-cells = <1>;
				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
				reg-names = "sata", "pcie";
			};

			phy_port1: port@fe38a000 {
				#phy-cells = <1>;
				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
				reg-names = "sata", "pcie";
			};
		};

		sata0: sata@fe380000 {
			compatible      = "st,sti-ahci";
			reg             = <0xfe380000 0x1000>;
			interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;
			interrupt-names = "hostc";
			phys	        = <&phy_port0 PHY_TYPE_SATA>;
			phy-names       = "sata-phy";
			resets	        = <&powerdown STIH416_SATA0_POWERDOWN>,
					  <&softreset STIH416_SATA0_SOFTRESET>;
			reset-names     = "pwr-dwn", "sw-rst";
			clock-names     = "ahci_clk";
			clocks	        = <&clk_s_a0_ls CLK_ICN_REG>;

			status	        = "disabled";
		};

		usb2_phy: phy@0 {
			compatible = "st,stih416-usb-phy";
			#phy-cells = <0>;
			st,syscfg = <&syscfg_rear>;
			clocks = <&clk_sysin>;
			clock-names = "osc_phy";
		};

		ehci0: usb@fe1ffe00 {
			compatible = "st,st-ehci-300x";
			reg = <0xfe1ffe00 0x100>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB0_POWERDOWN>,
				 <&softreset STIH416_USB0_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ohci0: usb@fe1ffc00 {
			compatible = "st,st-ohci-300x";
			reg = <0xfe1ffc00 0x100>;
			interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			status = "okay";
			resets = <&powerdown STIH416_USB0_POWERDOWN>,
				 <&softreset STIH416_USB0_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ehci1: usb@fe203e00 {
			compatible = "st,st-ehci-300x";
			reg = <0xfe203e00 0x100>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB1_POWERDOWN>,
				 <&softreset STIH416_USB1_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ohci1: usb@fe203c00 {
			compatible = "st,st-ohci-300x";
			reg = <0xfe203c00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB1_POWERDOWN>,
				 <&softreset STIH416_USB1_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ehci2: usb@fe303e00 {
			compatible = "st,st-ehci-300x";
			reg = <0xfe303e00 0x100>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB2_POWERDOWN>,
				 <&softreset STIH416_USB2_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ohci2: usb@fe303c00 {
			compatible = "st,st-ohci-300x";
			reg = <0xfe303c00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB2_POWERDOWN>,
				 <&softreset STIH416_USB2_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ehci3: usb@fe343e00 {
			compatible = "st,st-ehci-300x";
			reg = <0xfe343e00 0x100>;
			interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb3>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB3_POWERDOWN>,
				 <&softreset STIH416_USB3_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		ohci3: usb@fe343c00 {
			compatible = "st,st-ohci-300x";
			reg = <0xfe343c00 0x100>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
			clocks = <&clk_s_a1_ls 0>,
				 <&clockgen_b0 0>;
			clock-names = "ic", "clk48";
			phys = <&usb2_phy>;
			phy-names = "usb";
			resets = <&powerdown STIH416_USB3_POWERDOWN>,
				 <&softreset STIH416_USB3_SOFTRESET>;
			reset-names = "power", "softreset";
		};

		/* SAS PWM Module */
		pwm0: pwm@fed10000 {
			compatible	= "st,sti-pwm";
			status		= "disabled";
			#pwm-cells	= <2>;
			reg		= <0xfed10000 0x68>;

			pinctrl-names	= "default";
			pinctrl-0 = 	<&pinctrl_pwm0_chan0_default
					&pinctrl_pwm0_chan1_default
					&pinctrl_pwm0_chan2_default
					&pinctrl_pwm0_chan3_default>;

			clock-names	= "pwm";
			clocks		= <&clk_sysin>;
			st,pwm-num-chan = <4>;
		};

		/* SBC PWM Module */
		pwm1: pwm@fe510000 {
			compatible	= "st,sti-pwm";
			status		= "disabled";
			#pwm-cells	= <2>;
			reg		= <0xfe510000 0x68>;

			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_pwm1_chan0_default
					/*
					 * Shared with SBC_OBS_NOTRST.  Don't
					 * enable unless you really know what
					 * you're doing.
					 *
					 * &pinctrl_pwm1_chan1_default
					 */
					&pinctrl_pwm1_chan2_default
					&pinctrl_pwm1_chan3_default>;

			clock-names	= "pwm";
			clocks		= <&clk_sysin>;
			st,pwm-num-chan = <3>;
		};
	};
};
Commit	Line	Data
15969b45 SK	1	/*
	2	* Copyright (C) 2012 STMicroelectronics Limited.
	3	* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
	9	#include "stih41x.dtsi"
	10	#include "stih416-clock.dtsi"
	11	#include "stih416-pinctrl.dtsi"
d436a609	12
fbea230e	13	#include <dt-bindings/phy/phy.h>
f53e99a9	14	#include <dt-bindings/interrupt-controller/arm-gic.h>
da3e02a2	15	#include <dt-bindings/reset-controller/stih416-resets.h>
15969b45 SK	16	/ {
	17	L2: cache-controller {
	18	compatible = "arm,pl310-cache";
	19	reg = <0xfffe2000 0x1000>;
	20	arm,data-latency = <3 3 3>;
	21	arm,tag-latency = <2 2 2>;
	22	cache-unified;
	23	cache-level = <2>;
	24	};
	25
	26	soc {
	27	#address-cells = <1>;
	28	#size-cells = <1>;
	29	interrupt-parent = <&intc>;
	30	ranges;
	31	compatible = "simple-bus";
	32
fb54eb10 LJ	33	restart {
	34	compatible = "st,stih416-restart";
	35	st,syscfg = <&syscfg_sbc>;
	36	status = "okay";
	37	};
	38
da3e02a2 SK	39	powerdown: powerdown-controller {
	40	#reset-cells = <1>;
	41	compatible = "st,stih416-powerdown";
	42	};
	43
bef40df8 SK	44	softreset: softreset-controller {
	45	#reset-cells = <1>;
	46	compatible = "st,stih416-softreset";
	47	};
	48
15969b45 SK	49	syscfg_sbc:sbc-syscfg@fe600000{
	50	compatible = "st,stih416-sbc-syscfg", "syscon";
	51	reg = <0xfe600000 0x1000>;
	52	};
	53
	54	syscfg_front:front-syscfg@fee10000{
	55	compatible = "st,stih416-front-syscfg", "syscon";
	56	reg = <0xfee10000 0x1000>;
	57	};
	58
	59	syscfg_rear:rear-syscfg@fe830000{
	60	compatible = "st,stih416-rear-syscfg", "syscon";
	61	reg = <0xfe830000 0x1000>;
	62	};
	63
	64	/* MPE */
	65	syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
	66	compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
	67	reg = <0xfddf0000 0x1000>;
	68	};
	69
	70	syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
	71	compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
	72	reg = <0xfd6a0000 0x1000>;
	73	};
	74
	75	syscfg_cpu:cpu-syscfg@fdde0000{
	76	compatible = "st,stih416-cpu-syscfg", "syscon";
	77	reg = <0xfdde0000 0x1000>;
	78	};
	79
	80	syscfg_compo:compo-syscfg@fd320000{
	81	compatible = "st,stih416-compo-syscfg", "syscon";
	82	reg = <0xfd320000 0x1000>;
	83	};
	84
	85	syscfg_transport:transport-syscfg@fd690000{
	86	compatible = "st,stih416-transport-syscfg", "syscon";
	87	reg = <0xfd690000 0x1000>;
	88	};
	89
	90	syscfg_lpm:lpm-syscfg@fe4b5100{
	91	compatible = "st,stih416-lpm-syscfg", "syscon";
	92	reg = <0xfe4b5100 0x8>;
	93	};
	94
	95	serial2: serial@fed32000{
	96	compatible = "st,asc";
	97	status = "disabled";
	98	reg = <0xfed32000 0x2c>;
	99	interrupts = <0 197 0>;
08488e20	100	clocks = <&clk_s_a0_ls CLK_ICN_REG>;
15969b45	101	pinctrl-names = "default";
334ab91d	102	pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
15969b45 SK	103	};
	104
	105	/* SBC_UART1 */
	106	sbc_serial1: serial@fe531000 {
	107	compatible = "st,asc";
	108	status = "disabled";
	109	reg = <0xfe531000 0x2c>;
	110	interrupts = <0 210 0>;
	111	pinctrl-names = "default";
	112	pinctrl-0 = <&pinctrl_sbc_serial1>;
c66b2969	113	clocks = <&clk_sysin>;
15969b45	114	};
f53e99a9 MC	115
	116	i2c@fed40000 {
	117	compatible = "st,comms-ssc4-i2c";
	118	reg = <0xfed40000 0x110>;
	119	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
08488e20	120	clocks = <&clk_s_a0_ls CLK_ICN_REG>;
f53e99a9 MC	121	clock-names = "ssc";
	122	clock-frequency = <400000>;
	123	pinctrl-names = "default";
	124	pinctrl-0 = <&pinctrl_i2c0_default>;
	125
	126	status = "disabled";
	127	};
	128
	129	i2c@fed41000 {
	130	compatible = "st,comms-ssc4-i2c";
	131	reg = <0xfed41000 0x110>;
	132	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
08488e20	133	clocks = <&clk_s_a0_ls CLK_ICN_REG>;
f53e99a9 MC	134	clock-names = "ssc";
	135	clock-frequency = <400000>;
	136	pinctrl-names = "default";
	137	pinctrl-0 = <&pinctrl_i2c1_default>;
	138
	139	status = "disabled";
	140	};
	141
	142	i2c@fe540000 {
	143	compatible = "st,comms-ssc4-i2c";
	144	reg = <0xfe540000 0x110>;
	145	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
ed3593f9	146	clocks = <&clk_sysin>;
f53e99a9 MC	147	clock-names = "ssc";
	148	clock-frequency = <400000>;
	149	pinctrl-names = "default";
	150	pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
	151
	152	status = "disabled";
	153	};
	154
	155	i2c@fe541000 {
	156	compatible = "st,comms-ssc4-i2c";
	157	reg = <0xfe541000 0x110>;
	158	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
ed3593f9	159	clocks = <&clk_sysin>;
f53e99a9 MC	160	clock-names = "ssc";
	161	clock-frequency = <400000>;
	162	pinctrl-names = "default";
	163	pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
	164
	165	status = "disabled";
	166	};
d25ea584 SK	167
	168	ethernet0: dwmac@fe810000 {
	169	device_type = "network";
	170	compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
	171	status = "disabled";
9b1a6d36 PG	172	reg = <0xfe810000 0x8000>;
9b1a6d36 PG	173	reg-names = "stmmaceth";
d25ea584 SK	174
	175	interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
	176	interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
	177
	178	snps,pbl = <32>;
	179	snps,mixed-burst;
	180
9b1a6d36	181	st,syscon = <&syscfg_rear 0x8bc>;
d25ea584 SK	182	resets = <&softreset STIH416_ETH0_SOFTRESET>;
	183	reset-names = "stmmaceth";
	184	pinctrl-names = "default";
	185	pinctrl-0 = <&pinctrl_mii0>;
9796853e PG	186	clock-names = "stmmaceth", "sti-ethclk";
9796853e PG	187	clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
d25ea584 SK	188	};
	189
	190	ethernet1: dwmac@fef08000 {
	191	device_type = "network";
	192	compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
	193	status = "disabled";
9b1a6d36 PG	194	reg = <0xfef08000 0x8000>;
9b1a6d36 PG	195	reg-names = "stmmaceth";
d25ea584 SK	196	interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
	197	interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
	198
	199	snps,pbl = <32>;
	200	snps,mixed-burst;
	201
9b1a6d36	202	st,syscon = <&syscfg_sbc 0x7f0>;
d25ea584 SK	203
	204	resets = <&softreset STIH416_ETH1_SOFTRESET>;
	205	reset-names = "stmmaceth";
	206	pinctrl-names = "default";
	207	pinctrl-0 = <&pinctrl_mii1>;
9796853e PG	208	clock-names = "stmmaceth", "sti-ethclk";
9796853e PG	209	clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
d25ea584	210	};
e063735f SK	211
	212	rc: rc@fe518000 {
	213	compatible = "st,comms-irb";
	214	reg = <0xfe518000 0x234>;
	215	interrupts = <0 203 0>;
	216	rx-mode = "infrared";
ed3593f9	217	clocks = <&clk_sysin>;
e063735f SK	218	pinctrl-names = "default";
	219	pinctrl-0 = <&pinctrl_ir>;
	220	resets = <&softreset STIH416_IRB_SOFTRESET>;
	221	};
	222
77f8d9b7 LJ	223	/* FSM */
	224	spifsm: spifsm@fe902000 {
	225	compatible = "st,spi-fsm";
	226	reg = <0xfe902000 0x1000>;
	227	pinctrl-0 = <&pinctrl_fsm>;
	228
	229	st,syscfg = <&syscfg_rear>;
	230	st,boot-device-reg = <0x958>;
	231	st,boot-device-spi = <0x1a>;
	232
	233	status = "disabled";
	234	};
948d8ffb GF	235
	236	keyscan: keyscan@fe4b0000 {
	237	compatible = "st,sti-keyscan";
	238	status = "disabled";
	239	reg = <0xfe4b0000 0x2000>;
	240	interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
ed3593f9	241	clocks = <&clk_sysin>;
948d8ffb GF	242	pinctrl-names = "default";
	243	pinctrl-0 = <&pinctrl_keyscan>;
	244	resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
	245	<&softreset STIH416_KEYSCAN_SOFTRESET>;
	246	};
42d6f28d	247
0f6c28b7 LJ	248	temp0 {
	249	compatible = "st,stih416-sas-thermal";
	250	clock-names = "thermal";
	251	clocks = <&clockgen_c_vcc 14>;
	252
	253	status = "okay";
	254	};
	255
	256	temp1@fdfe8000 {
	257	compatible = "st,stih416-mpe-thermal";
	258	reg = <0xfdfe8000 0x10>;
	259	clocks = <&clockgen_e 3>;
	260	clock-names = "thermal";
	261	interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	262
	263	status = "okay";
	264	};
	265
42d6f28d PG	266	mmc0: sdhci@fe81e000 {
	267	compatible = "st,sdhci";
	268	status = "disabled";
	269	reg = <0xfe81e000 0x1000>;
	270	interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
	271	interrupt-names = "mmcirq";
	272	pinctrl-names = "default";
	273	pinctrl-0 = <&pinctrl_mmc0>;
	274	clock-names = "mmc";
	275	clocks = <&clk_s_a1_ls 1>;
	276	};
	277
	278	mmc1: sdhci@fe81f000 {
	279	compatible = "st,sdhci";
	280	status = "disabled";
	281	reg = <0xfe81f000 0x1000>;
	282	interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
	283	interrupt-names = "mmcirq";
	284	pinctrl-names = "default";
	285	pinctrl-0 = <&pinctrl_mmc1>;
	286	clock-names = "mmc";
	287	clocks = <&clk_s_a1_ls 8>;
	288	};
d436a609	289
3ece2c2b	290	miphy365x_phy: phy@fe382000 {
d436a609	291	compatible = "st,miphy365x-phy";
63139885	292	st,syscfg = <&syscfg_rear 0x824 0x828>;
d436a609 LJ	293	#address-cells = <1>;
	294	#size-cells = <1>;
	295	ranges;
	296
	297	phy_port0: port@fe382000 {
	298	#phy-cells = <1>;
63139885 PG	299	reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
63139885 PG	300	reg-names = "sata", "pcie";
d436a609 LJ	301	};
	302
	303	phy_port1: port@fe38a000 {
	304	#phy-cells = <1>;
63139885 PG	305	reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
63139885 PG	306	reg-names = "sata", "pcie";
d436a609 LJ	307	};
d436a609 LJ	308	};
45188b72 LJ	309
	310	sata0: sata@fe380000 {
	311	compatible = "st,sti-ahci";
	312	reg = <0xfe380000 0x1000>;
	313	interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
	314	interrupt-names = "hostc";
fbea230e	315	phys = <&phy_port0 PHY_TYPE_SATA>;
45188b72 LJ	316	phy-names = "sata-phy";
	317	resets = <&powerdown STIH416_SATA0_POWERDOWN>,
	318	<&softreset STIH416_SATA0_SOFTRESET>;
	319	reset-names = "pwr-dwn", "sw-rst";
	320	clock-names = "ahci_clk";
	321	clocks = <&clk_s_a0_ls CLK_ICN_REG>;
	322
	323	status = "disabled";
	324	};
7701677e PG	325
	326	usb2_phy: phy@0 {
	327	compatible = "st,stih416-usb-phy";
	328	#phy-cells = <0>;
	329	st,syscfg = <&syscfg_rear>;
	330	clocks = <&clk_sysin>;
	331	clock-names = "osc_phy";
	332	};
18221b82 PG	333
	334	ehci0: usb@fe1ffe00 {
	335	compatible = "st,st-ehci-300x";
	336	reg = <0xfe1ffe00 0x100>;
	337	interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
	338	pinctrl-names = "default";
	339	pinctrl-0 = <&pinctrl_usb0>;
	340	clocks = <&clk_s_a1_ls 0>,
	341	<&clockgen_b0 0>;
	342	clock-names = "ic", "clk48";
	343	phys = <&usb2_phy>;
	344	phy-names = "usb";
	345	resets = <&powerdown STIH416_USB0_POWERDOWN>,
	346	<&softreset STIH416_USB0_SOFTRESET>;
	347	reset-names = "power", "softreset";
	348	};
	349
	350	ohci0: usb@fe1ffc00 {
	351	compatible = "st,st-ohci-300x";
	352	reg = <0xfe1ffc00 0x100>;
	353	interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
	354	clocks = <&clk_s_a1_ls 0>,
	355	<&clockgen_b0 0>;
	356	clock-names = "ic", "clk48";
	357	phys = <&usb2_phy>;
	358	phy-names = "usb";
	359	status = "okay";
	360	resets = <&powerdown STIH416_USB0_POWERDOWN>,
	361	<&softreset STIH416_USB0_SOFTRESET>;
	362	reset-names = "power", "softreset";
	363	};
	364
	365	ehci1: usb@fe203e00 {
	366	compatible = "st,st-ehci-300x";
	367	reg = <0xfe203e00 0x100>;
	368	interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
	369	pinctrl-names = "default";
	370	pinctrl-0 = <&pinctrl_usb1>;
	371	clocks = <&clk_s_a1_ls 0>,
	372	<&clockgen_b0 0>;
	373	clock-names = "ic", "clk48";
	374	phys = <&usb2_phy>;
	375	phy-names = "usb";
	376	resets = <&powerdown STIH416_USB1_POWERDOWN>,
	377	<&softreset STIH416_USB1_SOFTRESET>;
	378	reset-names = "power", "softreset";
	379	};
	380
	381	ohci1: usb@fe203c00 {
	382	compatible = "st,st-ohci-300x";
	383	reg = <0xfe203c00 0x100>;
	384	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	385	clocks = <&clk_s_a1_ls 0>,
	386	<&clockgen_b0 0>;
	387	clock-names = "ic", "clk48";
	388	phys = <&usb2_phy>;
	389	phy-names = "usb";
	390	resets = <&powerdown STIH416_USB1_POWERDOWN>,
	391	<&softreset STIH416_USB1_SOFTRESET>;
	392	reset-names = "power", "softreset";
	393	};
	394
	395	ehci2: usb@fe303e00 {
	396	compatible = "st,st-ehci-300x";
397	reg = <0xfe303e00 0x100>;
398	interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
399	pinctrl-names = "default";
400	pinctrl-0 = <&pinctrl_usb2>;
401	clocks = <&clk_s_a1_ls 0>,
402	<&clockgen_b0 0>;
403	clock-names = "ic", "clk48";
404	phys = <&usb2_phy>;
405	phy-names = "usb";
406	resets = <&powerdown STIH416_USB2_POWERDOWN>,
407	<&softreset STIH416_USB2_SOFTRESET>;
408	reset-names = "power", "softreset";
409	};
410
411	ohci2: usb@fe303c00 {
412	compatible = "st,st-ohci-300x";
413	reg = <0xfe303c00 0x100>;
414	interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
415	clocks = <&clk_s_a1_ls 0>,
416	<&clockgen_b0 0>;
417	clock-names = "ic", "clk48";
418	phys = <&usb2_phy>;
419	phy-names = "usb";
420	resets = <&powerdown STIH416_USB2_POWERDOWN>,
421	<&softreset STIH416_USB2_SOFTRESET>;
422	reset-names = "power", "softreset";
423	};
424
425	ehci3: usb@fe343e00 {
426	compatible = "st,st-ehci-300x";
427	reg = <0xfe343e00 0x100>;
428	interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
429	pinctrl-names = "default";
430	pinctrl-0 = <&pinctrl_usb3>;
431	clocks = <&clk_s_a1_ls 0>,
432	<&clockgen_b0 0>;
433	clock-names = "ic", "clk48";
434	phys = <&usb2_phy>;
435	phy-names = "usb";
436	resets = <&powerdown STIH416_USB3_POWERDOWN>,
437	<&softreset STIH416_USB3_SOFTRESET>;
438	reset-names = "power", "softreset";
439	};
440
441	ohci3: usb@fe343c00 {
442	compatible = "st,st-ohci-300x";
443	reg = <0xfe343c00 0x100>;
444	interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
445	clocks = <&clk_s_a1_ls 0>,
446	<&clockgen_b0 0>;
447	clock-names = "ic", "clk48";
448	phys = <&usb2_phy>;
449	phy-names = "usb";
450	resets = <&powerdown STIH416_USB3_POWERDOWN>,
451	<&softreset STIH416_USB3_SOFTRESET>;
452	reset-names = "power", "softreset";
453	};
c66b2969 LJ	454
	455	/* SAS PWM Module */
	456	pwm0: pwm@fed10000 {
	457	compatible = "st,sti-pwm";
	458	status = "disabled";
	459	#pwm-cells = <2>;
	460	reg = <0xfed10000 0x68>;
	461
	462	pinctrl-names = "default";
	463	pinctrl-0 = <&pinctrl_pwm0_chan0_default
	464	&pinctrl_pwm0_chan1_default
	465	&pinctrl_pwm0_chan2_default
	466	&pinctrl_pwm0_chan3_default>;
	467
	468	clock-names = "pwm";
	469	clocks = <&clk_sysin>;
	470	st,pwm-num-chan = <4>;
	471	};
	472
	473	/* SBC PWM Module */
	474	pwm1: pwm@fe510000 {
	475	compatible = "st,sti-pwm";
	476	status = "disabled";
	477	#pwm-cells = <2>;
	478	reg = <0xfe510000 0x68>;
	479
	480	pinctrl-names = "default";
	481	pinctrl-0 = <&pinctrl_pwm1_chan0_default
	482	/*
	483	* Shared with SBC_OBS_NOTRST. Don't
	484	* enable unless you really know what
	485	* you're doing.
	486	*
	487	* &pinctrl_pwm1_chan1_default
	488	*/
	489	&pinctrl_pwm1_chan2_default
	490	&pinctrl_pwm1_chan3_default>;
	491
	492	clock-names = "pwm";
	493	clocks = <&clk_sysin>;
	494	st,pwm-num-chan = <3>;
	495	};
15969b45 SK	496	};
15969b45 SK	497	};