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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
63f3171d MC |
2 | /* |
3 | * Copyright (C) 2015 STMicroelectronics R&D Limited | |
63f3171d MC |
4 | */ |
5 | #include <dt-bindings/clock/stih418-clks.h> | |
6 | / { | |
cb10ca81 PC |
7 | /* |
8 | * Fixed 30MHz oscillator inputs to SoC | |
9 | */ | |
10 | clk_sysin: clk-sysin { | |
11 | #clock-cells = <0>; | |
12 | compatible = "fixed-clock"; | |
13 | clock-frequency = <30000000>; | |
14 | clock-output-names = "CLK_SYSIN"; | |
15 | }; | |
16 | ||
17 | clk_tmdsout_hdmi: clk-tmdsout-hdmi { | |
18 | #clock-cells = <0>; | |
19 | compatible = "fixed-clock"; | |
20 | clock-frequency = <0>; | |
21 | }; | |
22 | ||
63f3171d MC |
23 | clocks { |
24 | #address-cells = <1>; | |
25 | #size-cells = <1>; | |
26 | ranges; | |
27 | ||
28 | compatible = "st,stih418-clk", "simple-bus"; | |
29 | ||
63f3171d MC |
30 | /* |
31 | * A9 PLL. | |
32 | */ | |
33 | clockgen-a9@92b0000 { | |
34 | compatible = "st,clkgen-c32"; | |
35 | reg = <0x92b0000 0xffff>; | |
36 | ||
37 | clockgen_a9_pll: clockgen-a9-pll { | |
38 | #clock-cells = <1>; | |
665c8ec1 | 39 | compatible = "st,stih418-clkgen-plla9"; |
63f3171d MC |
40 | |
41 | clocks = <&clk_sysin>; | |
42 | ||
43 | clock-output-names = "clockgen-a9-pll-odf"; | |
44 | }; | |
45 | }; | |
46 | ||
47 | /* | |
48 | * ARM CPU related clocks. | |
49 | */ | |
50 | clk_m_a9: clk-m-a9@92b0000 { | |
51 | #clock-cells = <0>; | |
52 | compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; | |
53 | reg = <0x92b0000 0x10000>; | |
54 | ||
55 | clocks = <&clockgen_a9_pll 0>, | |
56 | <&clockgen_a9_pll 0>, | |
57 | <&clk_s_c0_flexgen 13>, | |
58 | <&clk_m_a9_ext2f_div2>; | |
63f3171d | 59 | |
cb10ca81 PC |
60 | /* |
61 | * ARM Peripheral clock for timers | |
62 | */ | |
63 | arm_periph_clk: clk-m-a9-periphs { | |
64 | #clock-cells = <0>; | |
65 | compatible = "fixed-factor-clock"; | |
66 | clocks = <&clk_m_a9>; | |
67 | clock-div = <2>; | |
68 | clock-mult = <1>; | |
69 | }; | |
63f3171d MC |
70 | }; |
71 | ||
8dccafaa | 72 | clockgen-a@90ff000 { |
63f3171d MC |
73 | compatible = "st,clkgen-c32"; |
74 | reg = <0x90ff000 0x1000>; | |
75 | ||
76 | clk_s_a0_pll: clk-s-a0-pll { | |
77 | #clock-cells = <1>; | |
665c8ec1 | 78 | compatible = "st,clkgen-pll0"; |
63f3171d MC |
79 | |
80 | clocks = <&clk_sysin>; | |
81 | ||
82 | clock-output-names = "clk-s-a0-pll-ofd-0"; | |
83 | }; | |
84 | ||
85 | clk_s_a0_flexgen: clk-s-a0-flexgen { | |
86 | compatible = "st,flexgen"; | |
87 | ||
88 | #clock-cells = <1>; | |
89 | ||
90 | clocks = <&clk_s_a0_pll 0>, | |
91 | <&clk_sysin>; | |
92 | ||
93 | clock-output-names = "clk-ic-lmi0", | |
94 | "clk-ic-lmi1"; | |
95 | }; | |
96 | }; | |
97 | ||
98 | clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { | |
99 | #clock-cells = <1>; | |
665c8ec1 | 100 | compatible = "st,quadfs-pll"; |
63f3171d MC |
101 | reg = <0x9103000 0x1000>; |
102 | ||
103 | clocks = <&clk_sysin>; | |
104 | ||
105 | clock-output-names = "clk-s-c0-fs0-ch0", | |
106 | "clk-s-c0-fs0-ch1", | |
107 | "clk-s-c0-fs0-ch2", | |
108 | "clk-s-c0-fs0-ch3"; | |
109 | }; | |
110 | ||
8dccafaa | 111 | clk_s_c0: clockgen-c@9103000 { |
63f3171d MC |
112 | compatible = "st,clkgen-c32"; |
113 | reg = <0x9103000 0x1000>; | |
114 | ||
115 | clk_s_c0_pll0: clk-s-c0-pll0 { | |
116 | #clock-cells = <1>; | |
665c8ec1 | 117 | compatible = "st,clkgen-pll0"; |
63f3171d MC |
118 | |
119 | clocks = <&clk_sysin>; | |
120 | ||
121 | clock-output-names = "clk-s-c0-pll0-odf-0"; | |
122 | }; | |
123 | ||
124 | clk_s_c0_pll1: clk-s-c0-pll1 { | |
125 | #clock-cells = <1>; | |
665c8ec1 | 126 | compatible = "st,clkgen-pll1"; |
63f3171d MC |
127 | |
128 | clocks = <&clk_sysin>; | |
129 | ||
130 | clock-output-names = "clk-s-c0-pll1-odf-0"; | |
131 | }; | |
132 | ||
133 | clk_s_c0_flexgen: clk-s-c0-flexgen { | |
134 | #clock-cells = <1>; | |
135 | compatible = "st,flexgen"; | |
136 | ||
137 | clocks = <&clk_s_c0_pll0 0>, | |
138 | <&clk_s_c0_pll1 0>, | |
139 | <&clk_s_c0_quadfs 0>, | |
140 | <&clk_s_c0_quadfs 1>, | |
141 | <&clk_s_c0_quadfs 2>, | |
142 | <&clk_s_c0_quadfs 3>, | |
143 | <&clk_sysin>; | |
144 | ||
145 | clock-output-names = "clk-icn-gpu", | |
146 | "clk-fdma", | |
147 | "clk-nand", | |
148 | "clk-hva", | |
149 | "clk-proc-stfe", | |
150 | "clk-tp", | |
151 | "clk-rx-icn-dmu", | |
152 | "clk-rx-icn-hva", | |
153 | "clk-icn-cpu", | |
154 | "clk-tx-icn-dmu", | |
155 | "clk-mmc-0", | |
156 | "clk-mmc-1", | |
157 | "clk-jpegdec", | |
158 | "clk-icn-reg", | |
159 | "clk-proc-bdisp-0", | |
160 | "clk-proc-bdisp-1", | |
161 | "clk-pp-dmu", | |
162 | "clk-vid-dmu", | |
163 | "clk-dss-lpc", | |
164 | "clk-st231-aud-0", | |
165 | "clk-st231-gp-1", | |
166 | "clk-st231-dmu", | |
167 | "clk-icn-lmi", | |
168 | "clk-tx-icn-1", | |
169 | "clk-icn-sbc", | |
170 | "clk-stfe-frc2", | |
171 | "clk-eth-phyref", | |
172 | "clk-eth-ref-phyclk", | |
173 | "clk-flash-promip", | |
174 | "clk-main-disp", | |
175 | "clk-aux-disp", | |
176 | "clk-compo-dvp", | |
177 | "clk-tx-icn-hades", | |
178 | "clk-rx-icn-hades", | |
179 | "clk-icn-reg-16", | |
180 | "clk-pp-hevc", | |
181 | "clk-clust-hevc", | |
182 | "clk-hwpe-hevc", | |
183 | "clk-fc-hevc", | |
184 | "clk-proc-mixer", | |
185 | "clk-proc-sc", | |
186 | "clk-avsp-hevc"; | |
cb10ca81 PC |
187 | |
188 | /* | |
189 | * ARM Peripheral clock for timers | |
190 | */ | |
191 | clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { | |
192 | #clock-cells = <0>; | |
193 | compatible = "fixed-factor-clock"; | |
194 | ||
195 | clocks = <&clk_s_c0_flexgen 13>; | |
196 | ||
197 | clock-output-names = "clk-m-a9-ext2f-div2"; | |
198 | ||
199 | clock-div = <2>; | |
200 | clock-mult = <1>; | |
201 | }; | |
63f3171d MC |
202 | }; |
203 | }; | |
204 | ||
205 | clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { | |
206 | #clock-cells = <1>; | |
665c8ec1 | 207 | compatible = "st,quadfs"; |
63f3171d MC |
208 | reg = <0x9104000 0x1000>; |
209 | ||
210 | clocks = <&clk_sysin>; | |
211 | ||
212 | clock-output-names = "clk-s-d0-fs0-ch0", | |
213 | "clk-s-d0-fs0-ch1", | |
214 | "clk-s-d0-fs0-ch2", | |
215 | "clk-s-d0-fs0-ch3"; | |
216 | }; | |
217 | ||
8dccafaa | 218 | clockgen-d0@9104000 { |
63f3171d MC |
219 | compatible = "st,clkgen-c32"; |
220 | reg = <0x9104000 0x1000>; | |
221 | ||
222 | clk_s_d0_flexgen: clk-s-d0-flexgen { | |
223 | #clock-cells = <1>; | |
97e7abdb | 224 | compatible = "st,flexgen-audio", "st,flexgen"; |
63f3171d MC |
225 | |
226 | clocks = <&clk_s_d0_quadfs 0>, | |
227 | <&clk_s_d0_quadfs 1>, | |
228 | <&clk_s_d0_quadfs 2>, | |
229 | <&clk_s_d0_quadfs 3>, | |
230 | <&clk_sysin>; | |
231 | ||
232 | clock-output-names = "clk-pcm-0", | |
233 | "clk-pcm-1", | |
234 | "clk-pcm-2", | |
235 | "clk-spdiff", | |
236 | "clk-pcmr10-master", | |
237 | "clk-usb2-phy"; | |
238 | }; | |
239 | }; | |
240 | ||
241 | clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { | |
242 | #clock-cells = <1>; | |
665c8ec1 | 243 | compatible = "st,quadfs"; |
63f3171d MC |
244 | reg = <0x9106000 0x1000>; |
245 | ||
246 | clocks = <&clk_sysin>; | |
247 | ||
248 | clock-output-names = "clk-s-d2-fs0-ch0", | |
249 | "clk-s-d2-fs0-ch1", | |
250 | "clk-s-d2-fs0-ch2", | |
251 | "clk-s-d2-fs0-ch3"; | |
252 | }; | |
253 | ||
d6d854cc | 254 | clockgen-d2@9106000 { |
63f3171d MC |
255 | compatible = "st,clkgen-c32"; |
256 | reg = <0x9106000 0x1000>; | |
257 | ||
258 | clk_s_d2_flexgen: clk-s-d2-flexgen { | |
259 | #clock-cells = <1>; | |
3b8b9f7f | 260 | compatible = "st,flexgen-video", "st,flexgen"; |
63f3171d MC |
261 | |
262 | clocks = <&clk_s_d2_quadfs 0>, | |
263 | <&clk_s_d2_quadfs 1>, | |
264 | <&clk_s_d2_quadfs 2>, | |
265 | <&clk_s_d2_quadfs 3>, | |
266 | <&clk_sysin>, | |
267 | <&clk_sysin>, | |
268 | <&clk_tmdsout_hdmi>; | |
269 | ||
270 | clock-output-names = "clk-pix-main-disp", | |
271 | "", | |
272 | "", | |
273 | "", | |
274 | "", | |
275 | "clk-tmds-hdmi-div2", | |
276 | "clk-pix-aux-disp", | |
277 | "clk-denc", | |
278 | "clk-pix-hddac", | |
279 | "clk-hddac", | |
280 | "clk-sddac", | |
281 | "clk-pix-dvo", | |
282 | "clk-dvo", | |
283 | "clk-pix-hdmi", | |
284 | "clk-tmds-hdmi", | |
285 | "clk-ref-hdmiphy", | |
286 | "", "", "", "", "", | |
287 | "", "", "", "", "", | |
288 | "", "", "", "", "", | |
289 | "", "", "", "", "", | |
290 | "", "", "", "", "", | |
291 | "", "", "", "", "", | |
292 | "", "clk-vp9"; | |
293 | }; | |
294 | }; | |
295 | ||
296 | clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { | |
297 | #clock-cells = <1>; | |
665c8ec1 | 298 | compatible = "st,quadfs"; |
63f3171d MC |
299 | reg = <0x9107000 0x1000>; |
300 | ||
301 | clocks = <&clk_sysin>; | |
302 | ||
303 | clock-output-names = "clk-s-d3-fs0-ch0", | |
304 | "clk-s-d3-fs0-ch1", | |
305 | "clk-s-d3-fs0-ch2", | |
306 | "clk-s-d3-fs0-ch3"; | |
307 | }; | |
308 | ||
309 | clockgen-d3@9107000 { | |
310 | compatible = "st,clkgen-c32"; | |
311 | reg = <0x9107000 0x1000>; | |
312 | ||
313 | clk_s_d3_flexgen: clk-s-d3-flexgen { | |
314 | #clock-cells = <1>; | |
315 | compatible = "st,flexgen"; | |
316 | ||
317 | clocks = <&clk_s_d3_quadfs 0>, | |
318 | <&clk_s_d3_quadfs 1>, | |
319 | <&clk_s_d3_quadfs 2>, | |
320 | <&clk_s_d3_quadfs 3>, | |
321 | <&clk_sysin>; | |
322 | ||
323 | clock-output-names = "clk-stfe-frc1", | |
324 | "clk-tsout-0", | |
325 | "clk-tsout-1", | |
326 | "clk-mchi", | |
327 | "clk-vsens-compo", | |
328 | "clk-frc1-remote", | |
329 | "clk-lpc-0", | |
330 | "clk-lpc-1"; | |
331 | }; | |
332 | }; | |
333 | }; | |
334 | }; |