[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / stm32f429.dtsi

/*
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
	};

	soc {
		dma-ranges = <0xc0000000 0x0 0x10000000>;

		timer2: timer@40000000 {
			compatible = "st,stm32-timer";
			reg = <0x40000000 0x400>;
			interrupts = <28>;
			clocks = <&rcc 0 128>;
			status = "disabled";
		};

		timer3: timer@40000400 {
			compatible = "st,stm32-timer";
			reg = <0x40000400 0x400>;
			interrupts = <29>;
			clocks = <&rcc 0 129>;
			status = "disabled";
		};

		timer4: timer@40000800 {
			compatible = "st,stm32-timer";
			reg = <0x40000800 0x400>;
			interrupts = <30>;
			clocks = <&rcc 0 130>;
			status = "disabled";
		};

		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc 0 131>;
		};

		timer6: timer@40001000 {
			compatible = "st,stm32-timer";
			reg = <0x40001000 0x400>;
			interrupts = <54>;
			clocks = <&rcc 0 132>;
			status = "disabled";
		};

		timer7: timer@40001400 {
			compatible = "st,stm32-timer";
			reg = <0x40001400 0x400>;
			interrupts = <55>;
			clocks = <&rcc 0 133>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			interrupts = <38>;
			clocks =  <&rcc 0 145>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			interrupts = <39>;
			clocks = <&rcc 0 146>;
			status = "disabled";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			interrupts = <52>;
			clocks = <&rcc 0 147>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			interrupts = <53>;
			clocks = <&rcc 0 148>;
			status = "disabled";
		};

		usart7: serial@40007800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40007800 0x400>;
			interrupts = <82>;
			clocks = <&rcc 0 158>;
			status = "disabled";
		};

		usart8: serial@40007c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			interrupts = <83>;
			clocks = <&rcc 0 159>;
			status = "disabled";
		};

		usart1: serial@40011000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 164>;
			status = "disabled";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			interrupts = <71>;
			clocks = <&rcc 0 165>;
			status = "disabled";
		};

		syscfg: system-config@40013800 {
			compatible = "syscon";
			reg = <0x40013800 0x400>;
		};

		exti: interrupt-controller@40013c00 {
			compatible = "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x40013C00 0x400>;
			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
		};

		pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f429-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			interrupt-parent = <&exti>;
			st,syscfg = <&syscfg 0x8>;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc 0 0>;
				st,bank-name = "GPIOA";
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x400 0x400>;
				clocks = <&rcc 0 1>;
				st,bank-name = "GPIOB";
			};

			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x800 0x400>;
				clocks = <&rcc 0 2>;
				st,bank-name = "GPIOC";
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 3>;
				st,bank-name = "GPIOD";
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 4>;
				st,bank-name = "GPIOE";
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 5>;
				st,bank-name = "GPIOF";
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 6>;
				st,bank-name = "GPIOG";
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 7>;
				st,bank-name = "GPIOH";
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 8>;
				st,bank-name = "GPIOI";
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 9>;
				st,bank-name = "GPIOJ";
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 10>;
				st,bank-name = "GPIOK";
			};

			usart1_pins_a: usart1@0 {
				pins1 {
					pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
					bias-disable;
				};
			};

			usbotg_hs_pins_a: usbotg_hs@0 {
				pins {
					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
						 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
						 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
						 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
						 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
						 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
						 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
						 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
						 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
						 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
						 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
						 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			ethernet0_mii: mii@0 {
				pins {
					pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
						 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
						 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
						 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
						 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
						 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
						 <STM32F429_PA2_FUNC_ETH_MDIO>,
						 <STM32F429_PC1_FUNC_ETH_MDC>,
						 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
						 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
						 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
						 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
						 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
						 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
					slew-rate = <2>;
				};
			};
		};

		rcc: rcc@40023810 {
			#reset-cells = <1>;
			#clock-cells = <2>;
			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>;
		};

		dma1: dma-controller@40026000 {
			compatible = "st,stm32-dma";
			reg = <0x40026000 0x400>;
			interrupts = <11>,
				     <12>,
				     <13>,
				     <14>,
				     <15>,
				     <16>,
				     <17>,
				     <47>;
			clocks = <&rcc 0 21>;
			#dma-cells = <4>;
		};

		dma2: dma-controller@40026400 {
			compatible = "st,stm32-dma";
			reg = <0x40026400 0x400>;
			interrupts = <56>,
				     <57>,
				     <58>,
				     <59>,
				     <60>,
				     <68>,
				     <69>,
				     <70>;
			clocks = <&rcc 0 22>;
			#dma-cells = <4>;
			st,mem2mem;
		};

		ethernet0: dwmac@40028000 {
			compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
			reg = <0x40028000 0x8000>;
			reg-names = "stmmaceth";
			interrupts = <61>, <62>;
			interrupt-names = "macirq", "eth_wake_irq";
			clock-names = "stmmaceth", "tx-clk", "rx-clk";
			clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
			st,syscon = <&syscfg 0x4>;
			snps,pbl = <8>;
			snps,mixed-burst;
			dma-ranges;
			status = "disabled";
		};

		usbotg_hs: usb@40040000 {
			compatible = "snps,dwc2";
			dma-ranges;
			reg = <0x40040000 0x40000>;
			interrupts = <77>;
			clocks = <&rcc 0 29>;
			clock-names = "otg";
			status = "disabled";
		};

		rng: rng@50060800 {
			compatible = "st,stm32-rng";
			reg = <0x50060800 0x400>;
			interrupts = <80>;
			clocks = <&rcc 0 38>;
		};
	};
};

&systick {
	clocks = <&rcc 1 0>;
	status = "okay";
};
Commit	Line	Data
338a6aaa MC	1	/*
	2	* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public
	20	* License along with this file; if not, write to the Free
	21	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	22	* MA 02110-1301 USA
	23	*
	24	* Or, alternatively,
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use,
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
05b23ebc	48	#include "skeleton.dtsi"
338a6aaa	49	#include "armv7-m.dtsi"
2dbd0593	50	#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
338a6aaa MC	51
	52	/ {
	53	clocks {
9dc24a2d	54	clk_hse: clk-hse {
338a6aaa MC	55	#clock-cells = <0>;
338a6aaa MC	56	compatible = "fixed-clock";
9dc24a2d	57	clock-frequency = <0>;
338a6aaa MC	58	};
	59	};
	60
	61	soc {
b2aa7f77 MC	62	dma-ranges = <0xc0000000 0x0 0x10000000>;
b2aa7f77 MC	63
338a6aaa MC	64	timer2: timer@40000000 {
	65	compatible = "st,stm32-timer";
	66	reg = <0x40000000 0x400>;
	67	interrupts = <28>;
9dc24a2d	68	clocks = <&rcc 0 128>;
338a6aaa MC	69	status = "disabled";
	70	};
	71
	72	timer3: timer@40000400 {
	73	compatible = "st,stm32-timer";
	74	reg = <0x40000400 0x400>;
	75	interrupts = <29>;
9dc24a2d	76	clocks = <&rcc 0 129>;
338a6aaa MC	77	status = "disabled";
	78	};
	79
	80	timer4: timer@40000800 {
	81	compatible = "st,stm32-timer";
	82	reg = <0x40000800 0x400>;
	83	interrupts = <30>;
9dc24a2d	84	clocks = <&rcc 0 130>;
338a6aaa MC	85	status = "disabled";
	86	};
	87
	88	timer5: timer@40000c00 {
	89	compatible = "st,stm32-timer";
	90	reg = <0x40000c00 0x400>;
	91	interrupts = <50>;
9dc24a2d	92	clocks = <&rcc 0 131>;
338a6aaa MC	93	};
	94
	95	timer6: timer@40001000 {
	96	compatible = "st,stm32-timer";
	97	reg = <0x40001000 0x400>;
	98	interrupts = <54>;
9dc24a2d	99	clocks = <&rcc 0 132>;
338a6aaa MC	100	status = "disabled";
	101	};
	102
	103	timer7: timer@40001400 {
	104	compatible = "st,stm32-timer";
	105	reg = <0x40001400 0x400>;
	106	interrupts = <55>;
9dc24a2d	107	clocks = <&rcc 0 133>;
338a6aaa MC	108	status = "disabled";
	109	};
	110
	111	usart2: serial@40004400 {
	112	compatible = "st,stm32-usart", "st,stm32-uart";
	113	reg = <0x40004400 0x400>;
	114	interrupts = <38>;
9dc24a2d	115	clocks = <&rcc 0 145>;
338a6aaa MC	116	status = "disabled";
	117	};
	118
	119	usart3: serial@40004800 {
	120	compatible = "st,stm32-usart", "st,stm32-uart";
	121	reg = <0x40004800 0x400>;
	122	interrupts = <39>;
9dc24a2d	123	clocks = <&rcc 0 146>;
338a6aaa MC	124	status = "disabled";
	125	};
	126
	127	usart4: serial@40004c00 {
	128	compatible = "st,stm32-uart";
	129	reg = <0x40004c00 0x400>;
	130	interrupts = <52>;
9dc24a2d	131	clocks = <&rcc 0 147>;
338a6aaa MC	132	status = "disabled";
	133	};
	134
	135	usart5: serial@40005000 {
	136	compatible = "st,stm32-uart";
	137	reg = <0x40005000 0x400>;
	138	interrupts = <53>;
9dc24a2d	139	clocks = <&rcc 0 148>;
338a6aaa MC	140	status = "disabled";
	141	};
	142
	143	usart7: serial@40007800 {
	144	compatible = "st,stm32-usart", "st,stm32-uart";
	145	reg = <0x40007800 0x400>;
	146	interrupts = <82>;
9dc24a2d	147	clocks = <&rcc 0 158>;
338a6aaa MC	148	status = "disabled";
	149	};
	150
	151	usart8: serial@40007c00 {
	152	compatible = "st,stm32-usart", "st,stm32-uart";
	153	reg = <0x40007c00 0x400>;
	154	interrupts = <83>;
9dc24a2d	155	clocks = <&rcc 0 159>;
338a6aaa MC	156	status = "disabled";
	157	};
	158
	159	usart1: serial@40011000 {
	160	compatible = "st,stm32-usart", "st,stm32-uart";
	161	reg = <0x40011000 0x400>;
	162	interrupts = <37>;
9dc24a2d	163	clocks = <&rcc 0 164>;
338a6aaa MC	164	status = "disabled";
	165	};
	166
	167	usart6: serial@40011400 {
	168	compatible = "st,stm32-usart", "st,stm32-uart";
	169	reg = <0x40011400 0x400>;
	170	interrupts = <71>;
9dc24a2d	171	clocks = <&rcc 0 165>;
338a6aaa MC	172	status = "disabled";
338a6aaa MC	173	};
9dc24a2d	174
e78b6555 AT	175	syscfg: system-config@40013800 {
	176	compatible = "syscon";
	177	reg = <0x40013800 0x400>;
	178	};
	179
5a79d596 AT	180	exti: interrupt-controller@40013c00 {
	181	compatible = "st,stm32-exti";
	182	interrupt-controller;
	183	#interrupt-cells = <2>;
	184	reg = <0x40013C00 0x400>;
	185	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
	186	};
	187
2dbd0593 MC	188	pin-controller {
	189	#address-cells = <1>;
	190	#size-cells = <1>;
	191	compatible = "st,stm32f429-pinctrl";
	192	ranges = <0 0x40020000 0x3000>;
ed01154f MC	193	interrupt-parent = <&exti>;
ed01154f MC	194	st,syscfg = <&syscfg 0x8>;
2dbd0593 MC	195	pins-are-numbered;
	196
	197	gpioa: gpio@40020000 {
	198	gpio-controller;
	199	#gpio-cells = <2>;
	200	reg = <0x0 0x400>;
a985b66a	201	clocks = <&rcc 0 0>;
2dbd0593 MC	202	st,bank-name = "GPIOA";
	203	};
	204
	205	gpiob: gpio@40020400 {
	206	gpio-controller;
	207	#gpio-cells = <2>;
	208	reg = <0x400 0x400>;
a985b66a	209	clocks = <&rcc 0 1>;
2dbd0593 MC	210	st,bank-name = "GPIOB";
	211	};
	212
	213	gpioc: gpio@40020800 {
	214	gpio-controller;
	215	#gpio-cells = <2>;
	216	reg = <0x800 0x400>;
a985b66a	217	clocks = <&rcc 0 2>;
2dbd0593 MC	218	st,bank-name = "GPIOC";
	219	};
	220
	221	gpiod: gpio@40020c00 {
	222	gpio-controller;
	223	#gpio-cells = <2>;
	224	reg = <0xc00 0x400>;
a985b66a	225	clocks = <&rcc 0 3>;
2dbd0593 MC	226	st,bank-name = "GPIOD";
	227	};
	228
	229	gpioe: gpio@40021000 {
	230	gpio-controller;
	231	#gpio-cells = <2>;
	232	reg = <0x1000 0x400>;
a985b66a	233	clocks = <&rcc 0 4>;
2dbd0593 MC	234	st,bank-name = "GPIOE";
	235	};
	236
	237	gpiof: gpio@40021400 {
	238	gpio-controller;
	239	#gpio-cells = <2>;
	240	reg = <0x1400 0x400>;
a985b66a	241	clocks = <&rcc 0 5>;
2dbd0593 MC	242	st,bank-name = "GPIOF";
	243	};
	244
	245	gpiog: gpio@40021800 {
	246	gpio-controller;
	247	#gpio-cells = <2>;
	248	reg = <0x1800 0x400>;
a985b66a	249	clocks = <&rcc 0 6>;
2dbd0593 MC	250	st,bank-name = "GPIOG";
	251	};
	252
	253	gpioh: gpio@40021c00 {
	254	gpio-controller;
	255	#gpio-cells = <2>;
	256	reg = <0x1c00 0x400>;
a985b66a	257	clocks = <&rcc 0 7>;
2dbd0593 MC	258	st,bank-name = "GPIOH";
	259	};
	260
	261	gpioi: gpio@40022000 {
	262	gpio-controller;
	263	#gpio-cells = <2>;
	264	reg = <0x2000 0x400>;
a985b66a	265	clocks = <&rcc 0 8>;
2dbd0593 MC	266	st,bank-name = "GPIOI";
	267	};
	268
	269	gpioj: gpio@40022400 {
	270	gpio-controller;
	271	#gpio-cells = <2>;
	272	reg = <0x2400 0x400>;
a985b66a	273	clocks = <&rcc 0 9>;
2dbd0593 MC	274	st,bank-name = "GPIOJ";
	275	};
	276
	277	gpiok: gpio@40022800 {
	278	gpio-controller;
	279	#gpio-cells = <2>;
	280	reg = <0x2800 0x400>;
a985b66a	281	clocks = <&rcc 0 10>;
2dbd0593 MC	282	st,bank-name = "GPIOK";
2dbd0593 MC	283	};
521df6f5 MC	284
	285	usart1_pins_a: usart1@0 {
	286	pins1 {
	287	pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
	288	bias-disable;
	289	drive-push-pull;
	290	slew-rate = <0>;
	291	};
	292	pins2 {
	293	pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
	294	bias-disable;
	295	};
	296	};
c8cc1b72 MC	297
	298	usbotg_hs_pins_a: usbotg_hs@0 {
	299	pins {
	300	pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
	301	<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
	302	<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
	303	<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
	304	<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
	305	<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
	306	<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
	307	<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
	308	<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
	309	<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
	310	<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
	311	<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
	312	bias-disable;
	313	drive-push-pull;
	314	slew-rate = <2>;
	315	};
	316	};
9ee33d66 AT	317
	318	ethernet0_mii: mii@0 {
	319	pins {
	320	pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
	321	<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
	322	<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
	323	<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
	324	<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
	325	<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
	326	<STM32F429_PA2_FUNC_ETH_MDIO>,
	327	<STM32F429_PC1_FUNC_ETH_MDC>,
	328	<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
	329	<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
	330	<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
	331	<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
	332	<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
	333	<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
	334	slew-rate = <2>;
	335	};
	336	};
2dbd0593 MC	337	};
2dbd0593 MC	338
9dc24a2d	339	rcc: rcc@40023810 {
9af80712	340	#reset-cells = <1>;
9dc24a2d DT	341	#clock-cells = <2>;
	342	compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
	343	reg = <0x40023800 0x400>;
	344	clocks = <&clk_hse>;
	345	};
b47c9fab	346
9ee9e281 CM	347	dma1: dma-controller@40026000 {
	348	compatible = "st,stm32-dma";
	349	reg = <0x40026000 0x400>;
	350	interrupts = <11>,
	351	<12>,
	352	<13>,
	353	<14>,
	354	<15>,
	355	<16>,
	356	<17>,
	357	<47>;
	358	clocks = <&rcc 0 21>;
	359	#dma-cells = <4>;
	360	};
	361
	362	dma2: dma-controller@40026400 {
	363	compatible = "st,stm32-dma";
	364	reg = <0x40026400 0x400>;
	365	interrupts = <56>,
	366	<57>,
	367	<58>,
	368	<59>,
	369	<60>,
	370	<68>,
	371	<69>,
	372	<70>;
	373	clocks = <&rcc 0 22>;
	374	#dma-cells = <4>;
	375	st,mem2mem;
	376	};
	377
9ee33d66 AT	378	ethernet0: dwmac@40028000 {
	379	compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
	380	reg = <0x40028000 0x8000>;
	381	reg-names = "stmmaceth";
	382	interrupts = <61>, <62>;
	383	interrupt-names = "macirq", "eth_wake_irq";
	384	clock-names = "stmmaceth", "tx-clk", "rx-clk";
	385	clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
	386	st,syscon = <&syscfg 0x4>;
	387	snps,pbl = <8>;
	388	snps,mixed-burst;
	389	dma-ranges;
	390	status = "disabled";
	391	};
	392
c8cc1b72 MC	393	usbotg_hs: usb@40040000 {
	394	compatible = "snps,dwc2";
	395	dma-ranges;
	396	reg = <0x40040000 0x40000>;
	397	interrupts = <77>;
	398	clocks = <&rcc 0 29>;
	399	clock-names = "otg";
	400	status = "disabled";
	401	};
	402
b47c9fab DT	403	rng: rng@50060800 {
	404	compatible = "st,stm32-rng";
	405	reg = <0x50060800 0x400>;
	406	interrupts = <80>;
	407	clocks = <&rcc 0 38>;
	408	};
338a6aaa MC	409	};
	410	};
	411
	412	&systick {
9dc24a2d	413	clocks = <&rcc 1 0>;
338a6aaa MC	414	status = "okay";
338a6aaa MC	415	};