[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / stm32f746.dtsi

/*
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_i2s_ckin: clk-i2s-ckin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <48000000>;
		};
	};

	soc {
		timer2: timer@40000000 {
			compatible = "st,stm32-timer";
			reg = <0x40000000 0x400>;
			interrupts = <28>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
			status = "disabled";
		};

		timer3: timer@40000400 {
			compatible = "st,stm32-timer";
			reg = <0x40000400 0x400>;
			interrupts = <29>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
			status = "disabled";
		};

		timer4: timer@40000800 {
			compatible = "st,stm32-timer";
			reg = <0x40000800 0x400>;
			interrupts = <30>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
			status = "disabled";
		};

		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
		};

		timer6: timer@40001000 {
			compatible = "st,stm32-timer";
			reg = <0x40001000 0x400>;
			interrupts = <54>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
			status = "disabled";
		};

		timer7: timer@40001400 {
			compatible = "st,stm32-timer";
			reg = <0x40001400 0x400>;
			interrupts = <55>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
			status = "disabled";
		};

		rtc: rtc@40002800 {
			compatible = "st,stm32-rtc";
			reg = <0x40002800 0x400>;
			clocks = <&rcc 1 CLK_RTC>;
			clock-names = "ck_rtc";
			assigned-clocks = <&rcc 1 CLK_RTC>;
			assigned-clock-parents = <&rcc 1 CLK_LSE>;
			interrupt-parent = <&exti>;
			interrupts = <17 1>;
			interrupt-names = "alarm";
			st,syscfg = <&pwrcfg>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40004400 0x400>;
			interrupts = <38>;
			clocks = <&rcc 1 CLK_USART2>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40004800 0x400>;
			interrupts = <39>;
			clocks = <&rcc 1 CLK_USART3>;
			status = "disabled";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32f7-uart";
			reg = <0x40004c00 0x400>;
			interrupts = <52>;
			clocks = <&rcc 1 CLK_UART4>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32f7-uart";
			reg = <0x40005000 0x400>;
			interrupts = <53>;
			clocks = <&rcc 1 CLK_UART5>;
			status = "disabled";
		};

		cec: cec@40006c00 {
			compatible = "st,stm32-cec";
			reg = <0x40006C00 0x400>;
			interrupts = <94>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
			clock-names = "cec", "hdmi-cec";
			status = "disabled";
		};

		usart7: serial@40007800 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40007800 0x400>;
			interrupts = <82>;
			clocks = <&rcc 1 CLK_UART7>;
			status = "disabled";
		};

		usart8: serial@40007c00 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40007c00 0x400>;
			interrupts = <83>;
			clocks = <&rcc 1 CLK_UART8>;
			status = "disabled";
		};

		usart1: serial@40011000 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 1 CLK_USART1>;
			status = "disabled";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40011400 0x400>;
			interrupts = <71>;
			clocks = <&rcc 1 CLK_USART6>;
			status = "disabled";
		};

		syscfg: system-config@40013800 {
			compatible = "syscon";
			reg = <0x40013800 0x400>;
		};

		exti: interrupt-controller@40013c00 {
			compatible = "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x40013C00 0x400>;
			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
		};

		pwrcfg: power-config@40007000 {
			compatible = "syscon";
			reg = <0x40007000 0x400>;
		};

		pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f746-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			interrupt-parent = <&exti>;
			st,syscfg = <&syscfg 0x8>;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
				st,bank-name = "GPIOA";
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
				st,bank-name = "GPIOB";
			};

			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
				st,bank-name = "GPIOC";
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
				st,bank-name = "GPIOD";
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
				st,bank-name = "GPIOE";
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
				st,bank-name = "GPIOF";
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
				st,bank-name = "GPIOG";
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
				st,bank-name = "GPIOH";
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
				st,bank-name = "GPIOI";
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
				st,bank-name = "GPIOJ";
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
				st,bank-name = "GPIOK";
			};

			cec_pins_a: cec@0 {
				pins {
					pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>;
					slew-rate = <0>;
					drive-open-drain;
					bias-disable;
				};
			};

			usart1_pins_a: usart1@0 {
				pins1 {
					pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
					bias-disable;
				};
			};

			usart1_pins_b: usart1@1 {
				pins1 {
					pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
					bias-disable;
				};
			};
		};

		crc: crc@40023000 {
			compatible = "st,stm32f7-crc";
			reg = <0x40023000 0x400>;
			clocks = <&rcc 0 12>;
			status = "disabled";
		};

		rcc: rcc@40023800 {
			#reset-cells = <1>;
			#clock-cells = <2>;
			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>, <&clk_i2s_ckin>;
			st,syscfg = <&pwrcfg>;
			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
			assigned-clock-rates = <1000000>;
		};

		dma1: dma@40026000 {
			compatible = "st,stm32-dma";
			reg = <0x40026000 0x400>;
			interrupts = <11>,
				     <12>,
				     <13>,
				     <14>,
				     <15>,
				     <16>,
				     <17>,
				     <47>;
			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
			#dma-cells = <4>;
			status = "disabled";
		};

		dma2: dma@40026400 {
			compatible = "st,stm32-dma";
			reg = <0x40026400 0x400>;
			interrupts = <56>,
				     <57>,
				     <58>,
				     <59>,
				     <60>,
				     <68>,
				     <69>,
				     <70>;
			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
			#dma-cells = <4>;
			st,mem2mem;
			status = "disabled";
		};
	};
};

&systick {
	clocks = <&rcc 1 0>;
	status = "okay";
};
Commit	Line	Data
ec2f9b10 AT	1	/*
	2	* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include "skeleton.dtsi"
	44	#include "armv7-m.dtsi"
	45	#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
01e435d2	46	#include <dt-bindings/clock/stm32fx-clock.h>
156fdf11	47	#include <dt-bindings/mfd/stm32f7-rcc.h>
ec2f9b10 AT	48
	49	/ {
	50	clocks {
	51	clk_hse: clk-hse {
	52	#clock-cells = <0>;
	53	compatible = "fixed-clock";
	54	clock-frequency = <0>;
	55	};
01e435d2 GF	56
	57	clk-lse {
	58	#clock-cells = <0>;
	59	compatible = "fixed-clock";
	60	clock-frequency = <32768>;
	61	};
	62
	63	clk-lsi {
	64	#clock-cells = <0>;
	65	compatible = "fixed-clock";
	66	clock-frequency = <32000>;
	67	};
	68
	69	clk_i2s_ckin: clk-i2s-ckin {
	70	#clock-cells = <0>;
	71	compatible = "fixed-clock";
	72	clock-frequency = <48000000>;
	73	};
ec2f9b10 AT	74	};
	75
	76	soc {
	77	timer2: timer@40000000 {
	78	compatible = "st,stm32-timer";
	79	reg = <0x40000000 0x400>;
	80	interrupts = <28>;
156fdf11	81	clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
ec2f9b10 AT	82	status = "disabled";
	83	};
	84
	85	timer3: timer@40000400 {
	86	compatible = "st,stm32-timer";
	87	reg = <0x40000400 0x400>;
	88	interrupts = <29>;
156fdf11	89	clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
ec2f9b10 AT	90	status = "disabled";
	91	};
	92
	93	timer4: timer@40000800 {
	94	compatible = "st,stm32-timer";
	95	reg = <0x40000800 0x400>;
	96	interrupts = <30>;
156fdf11	97	clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
ec2f9b10 AT	98	status = "disabled";
	99	};
	100
	101	timer5: timer@40000c00 {
	102	compatible = "st,stm32-timer";
	103	reg = <0x40000c00 0x400>;
	104	interrupts = <50>;
156fdf11	105	clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
ec2f9b10 AT	106	};
	107
	108	timer6: timer@40001000 {
	109	compatible = "st,stm32-timer";
	110	reg = <0x40001000 0x400>;
	111	interrupts = <54>;
156fdf11	112	clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
ec2f9b10 AT	113	status = "disabled";
	114	};
	115
	116	timer7: timer@40001400 {
	117	compatible = "st,stm32-timer";
	118	reg = <0x40001400 0x400>;
	119	interrupts = <55>;
156fdf11	120	clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
ec2f9b10 AT	121	status = "disabled";
	122	};
	123
859e2647 AD	124	rtc: rtc@40002800 {
	125	compatible = "st,stm32-rtc";
	126	reg = <0x40002800 0x400>;
	127	clocks = <&rcc 1 CLK_RTC>;
	128	clock-names = "ck_rtc";
	129	assigned-clocks = <&rcc 1 CLK_RTC>;
	130	assigned-clock-parents = <&rcc 1 CLK_LSE>;
	131	interrupt-parent = <&exti>;
	132	interrupts = <17 1>;
	133	interrupt-names = "alarm";
	134	st,syscfg = <&pwrcfg>;
ec2f9b10 AT	135	status = "disabled";
	136	};
	137
	138	usart2: serial@40004400 {
	139	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
	140	reg = <0x40004400 0x400>;
	141	interrupts = <38>;
156fdf11	142	clocks = <&rcc 1 CLK_USART2>;
ec2f9b10 AT	143	status = "disabled";
	144	};
	145
	146	usart3: serial@40004800 {
	147	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
	148	reg = <0x40004800 0x400>;
	149	interrupts = <39>;
156fdf11	150	clocks = <&rcc 1 CLK_USART3>;
ec2f9b10 AT	151	status = "disabled";
	152	};
	153
	154	usart4: serial@40004c00 {
	155	compatible = "st,stm32f7-uart";
	156	reg = <0x40004c00 0x400>;
	157	interrupts = <52>;
156fdf11	158	clocks = <&rcc 1 CLK_UART4>;
ec2f9b10 AT	159	status = "disabled";
	160	};
	161
	162	usart5: serial@40005000 {
	163	compatible = "st,stm32f7-uart";
	164	reg = <0x40005000 0x400>;
	165	interrupts = <53>;
156fdf11	166	clocks = <&rcc 1 CLK_UART5>;
ec2f9b10 AT	167	status = "disabled";
	168	};
	169
076934cc BG	170	cec: cec@40006c00 {
	171	compatible = "st,stm32-cec";
	172	reg = <0x40006C00 0x400>;
	173	interrupts = <94>;
	174	clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
	175	clock-names = "cec", "hdmi-cec";
	176	status = "disabled";
	177	};
	178
ec2f9b10 AT	179	usart7: serial@40007800 {
	180	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
	181	reg = <0x40007800 0x400>;
	182	interrupts = <82>;
156fdf11	183	clocks = <&rcc 1 CLK_UART7>;
ec2f9b10 AT	184	status = "disabled";
	185	};
	186
	187	usart8: serial@40007c00 {
	188	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
	189	reg = <0x40007c00 0x400>;
	190	interrupts = <83>;
156fdf11	191	clocks = <&rcc 1 CLK_UART8>;
ec2f9b10 AT	192	status = "disabled";
	193	};
	194
	195	usart1: serial@40011000 {
	196	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
	197	reg = <0x40011000 0x400>;
	198	interrupts = <37>;
156fdf11	199	clocks = <&rcc 1 CLK_USART1>;
ec2f9b10 AT	200	status = "disabled";
	201	};
	202
	203	usart6: serial@40011400 {
	204	compatible = "st,stm32f7-usart", "st,stm32f7-uart";
	205	reg = <0x40011400 0x400>;
	206	interrupts = <71>;
156fdf11	207	clocks = <&rcc 1 CLK_USART6>;
ec2f9b10 AT	208	status = "disabled";
	209	};
	210
	211	syscfg: system-config@40013800 {
	212	compatible = "syscon";
	213	reg = <0x40013800 0x400>;
	214	};
	215
	216	exti: interrupt-controller@40013c00 {
	217	compatible = "st,stm32-exti";
	218	interrupt-controller;
	219	#interrupt-cells = <2>;
	220	reg = <0x40013C00 0x400>;
	221	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
	222	};
	223
01e435d2 GF	224	pwrcfg: power-config@40007000 {
	225	compatible = "syscon";
	226	reg = <0x40007000 0x400>;
	227	};
	228
ec2f9b10 AT	229	pin-controller {
	230	#address-cells = <1>;
	231	#size-cells = <1>;
	232	compatible = "st,stm32f746-pinctrl";
	233	ranges = <0 0x40020000 0x3000>;
	234	interrupt-parent = <&exti>;
	235	st,syscfg = <&syscfg 0x8>;
	236	pins-are-numbered;
	237
	238	gpioa: gpio@40020000 {
	239	gpio-controller;
	240	#gpio-cells = <2>;
5489d5db AT	241	interrupt-controller;
5489d5db AT	242	#interrupt-cells = <2>;
ec2f9b10	243	reg = <0x0 0x400>;
156fdf11	244	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
ec2f9b10 AT	245	st,bank-name = "GPIOA";
	246	};
	247
	248	gpiob: gpio@40020400 {
	249	gpio-controller;
	250	#gpio-cells = <2>;
5489d5db AT	251	interrupt-controller;
5489d5db AT	252	#interrupt-cells = <2>;
ec2f9b10	253	reg = <0x400 0x400>;
156fdf11	254	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
ec2f9b10 AT	255	st,bank-name = "GPIOB";
	256	};
	257
	258	gpioc: gpio@40020800 {
	259	gpio-controller;
	260	#gpio-cells = <2>;
5489d5db AT	261	interrupt-controller;
5489d5db AT	262	#interrupt-cells = <2>;
ec2f9b10	263	reg = <0x800 0x400>;
156fdf11	264	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
ec2f9b10 AT	265	st,bank-name = "GPIOC";
	266	};
	267
	268	gpiod: gpio@40020c00 {
	269	gpio-controller;
	270	#gpio-cells = <2>;
5489d5db AT	271	interrupt-controller;
5489d5db AT	272	#interrupt-cells = <2>;
ec2f9b10	273	reg = <0xc00 0x400>;
156fdf11	274	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
ec2f9b10 AT	275	st,bank-name = "GPIOD";
	276	};
	277
	278	gpioe: gpio@40021000 {
	279	gpio-controller;
	280	#gpio-cells = <2>;
5489d5db AT	281	interrupt-controller;
5489d5db AT	282	#interrupt-cells = <2>;
ec2f9b10	283	reg = <0x1000 0x400>;
156fdf11	284	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
ec2f9b10 AT	285	st,bank-name = "GPIOE";
	286	};
	287
	288	gpiof: gpio@40021400 {
	289	gpio-controller;
	290	#gpio-cells = <2>;
5489d5db AT	291	interrupt-controller;
5489d5db AT	292	#interrupt-cells = <2>;
ec2f9b10	293	reg = <0x1400 0x400>;
156fdf11	294	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
ec2f9b10 AT	295	st,bank-name = "GPIOF";
	296	};
	297
	298	gpiog: gpio@40021800 {
	299	gpio-controller;
	300	#gpio-cells = <2>;
5489d5db AT	301	interrupt-controller;
5489d5db AT	302	#interrupt-cells = <2>;
ec2f9b10	303	reg = <0x1800 0x400>;
156fdf11	304	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
ec2f9b10 AT	305	st,bank-name = "GPIOG";
	306	};
	307
	308	gpioh: gpio@40021c00 {
	309	gpio-controller;
	310	#gpio-cells = <2>;
5489d5db AT	311	interrupt-controller;
5489d5db AT	312	#interrupt-cells = <2>;
ec2f9b10	313	reg = <0x1c00 0x400>;
156fdf11	314	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
ec2f9b10 AT	315	st,bank-name = "GPIOH";
	316	};
	317
	318	gpioi: gpio@40022000 {
	319	gpio-controller;
	320	#gpio-cells = <2>;
5489d5db AT	321	interrupt-controller;
5489d5db AT	322	#interrupt-cells = <2>;
ec2f9b10	323	reg = <0x2000 0x400>;
156fdf11	324	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
ec2f9b10 AT	325	st,bank-name = "GPIOI";
	326	};
	327
	328	gpioj: gpio@40022400 {
	329	gpio-controller;
	330	#gpio-cells = <2>;
5489d5db AT	331	interrupt-controller;
5489d5db AT	332	#interrupt-cells = <2>;
ec2f9b10	333	reg = <0x2400 0x400>;
156fdf11	334	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
ec2f9b10 AT	335	st,bank-name = "GPIOJ";
	336	};
	337
	338	gpiok: gpio@40022800 {
	339	gpio-controller;
	340	#gpio-cells = <2>;
5489d5db AT	341	interrupt-controller;
5489d5db AT	342	#interrupt-cells = <2>;
ec2f9b10	343	reg = <0x2800 0x400>;
156fdf11	344	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
ec2f9b10 AT	345	st,bank-name = "GPIOK";
	346	};
	347
076934cc BG	348	cec_pins_a: cec@0 {
	349	pins {
	350	pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>;
	351	slew-rate = <0>;
	352	drive-open-drain;
	353	bias-disable;
	354	};
	355	};
	356
ec2f9b10 AT	357	usart1_pins_a: usart1@0 {
	358	pins1 {
	359	pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
	360	bias-disable;
	361	drive-push-pull;
	362	slew-rate = <0>;
	363	};
	364	pins2 {
	365	pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
	366	bias-disable;
	367	};
	368	};
f44848b6 VM	369
	370	usart1_pins_b: usart1@1 {
	371	pins1 {
	372	pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
	373	bias-disable;
	374	drive-push-pull;
	375	slew-rate = <0>;
	376	};
	377	pins2 {
	378	pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
	379	bias-disable;
	380	};
	381	};
ec2f9b10 AT	382	};
ec2f9b10 AT	383
115d691f FD	384	crc: crc@40023000 {
	385	compatible = "st,stm32f7-crc";
	386	reg = <0x40023000 0x400>;
	387	clocks = <&rcc 0 12>;
	388	status = "disabled";
	389	};
	390
ec2f9b10	391	rcc: rcc@40023800 {
aa8f42f7	392	#reset-cells = <1>;
ec2f9b10	393	#clock-cells = <2>;
01e435d2	394	compatible = "st,stm32f746-rcc", "st,stm32-rcc";
ec2f9b10	395	reg = <0x40023800 0x400>;
01e435d2 GF	396	clocks = <&clk_hse>, <&clk_i2s_ckin>;
01e435d2 GF	397	st,syscfg = <&pwrcfg>;
91a7f89c AD	398	assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
91a7f89c AD	399	assigned-clock-rates = <1000000>;
ec2f9b10	400	};
47c8a503 PYM	401
	402	dma1: dma@40026000 {
	403	compatible = "st,stm32-dma";
	404	reg = <0x40026000 0x400>;
	405	interrupts = <11>,
	406	<12>,
	407	<13>,
	408	<14>,
	409	<15>,
	410	<16>,
	411	<17>,
	412	<47>;
	413	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
	414	#dma-cells = <4>;
	415	status = "disabled";
	416	};
	417
	418	dma2: dma@40026400 {
	419	compatible = "st,stm32-dma";
	420	reg = <0x40026400 0x400>;
	421	interrupts = <56>,
	422	<57>,
	423	<58>,
	424	<59>,
	425	<60>,
	426	<68>,
	427	<69>,
	428	<70>;
	429	clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
	430	#dma-cells = <4>;
	431	st,mem2mem;
	432	status = "disabled";
	433	};
ec2f9b10 AT	434	};
	435	};
	436
	437	&systick {
	438	clocks = <&rcc 1 0>;
	439	status = "okay";
	440	};