[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / stm32mp157c.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_off = <0x84000002>;
		cpu_on = <0x84000003>;
	};

	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
	};

	intc: interrupt-controller@a0021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xa0021000 0x1000>,
		      <0xa0022000 0x2000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&intc>;
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_csi: clk-csi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		timers2: timer@40000000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc TIM2_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@1 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <1>;
				status = "disabled";
			};
		};

		timers3: timer@40001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc TIM3_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@2 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <2>;
				status = "disabled";
			};
		};

		timers4: timer@40002000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40002000 0x400>;
			clocks = <&rcc TIM4_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@3 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <3>;
				status = "disabled";
			};
		};

		timers5: timer@40003000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40003000 0x400>;
			clocks = <&rcc TIM5_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@4 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <4>;
				status = "disabled";
			};
		};

		timers6: timer@40004000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40004000 0x400>;
			clocks = <&rcc TIM6_K>;
			clock-names = "int";
			status = "disabled";

			timer@5 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <5>;
				status = "disabled";
			};
		};

		timers7: timer@40005000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40005000 0x400>;
			clocks = <&rcc TIM7_K>;
			clock-names = "int";
			status = "disabled";

			timer@6 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <6>;
				status = "disabled";
			};
		};

		timers12: timer@40006000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40006000 0x400>;
			clocks = <&rcc TIM12_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@11 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <11>;
				status = "disabled";
			};
		};

		timers13: timer@40007000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40007000 0x400>;
			clocks = <&rcc TIM13_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@12 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <12>;
				status = "disabled";
			};
		};

		timers14: timer@40008000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40008000 0x400>;
			clocks = <&rcc TIM14_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@13 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <13>;
				status = "disabled";
			};
		};

		lptimer1: timer@40009000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x40009000 0x400>;
			clocks = <&rcc LPTIM1_K>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				#pwm-cells = <3>;
				status = "disabled";
			};

			trigger@0 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <0>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-lptimer-counter";
				status = "disabled";
			};
		};

		usart2: serial@4000e000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000e000 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
			clocks = <&rcc USART2_K>;
			status = "disabled";
		};

		usart3: serial@4000f000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000f000 0x400>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
			clocks = <&rcc USART3_K>;
			status = "disabled";
		};

		uart4: serial@40010000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40010000 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
			clocks = <&rcc UART4_K>;
			status = "disabled";
		};

		uart5: serial@40011000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
			clocks = <&rcc UART5_K>;
			status = "disabled";
		};

		i2c1: i2c@40012000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x40012000 0x400>;
			interrupt-names = "event", "error";
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C1_K>;
			resets = <&rcc I2C1_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@40013000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x40013000 0x400>;
			interrupt-names = "event", "error";
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C2_K>;
			resets = <&rcc I2C2_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@40014000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x40014000 0x400>;
			interrupt-names = "event", "error";
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C3_K>;
			resets = <&rcc I2C3_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@40015000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x40015000 0x400>;
			interrupt-names = "event", "error";
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C5_K>;
			resets = <&rcc I2C5_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dac: dac@40017000 {
			compatible = "st,stm32h7-dac-core";
			reg = <0x40017000 0x400>;
			clocks = <&rcc DAC12>;
			clock-names = "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			dac1: dac@1 {
				compatible = "st,stm32-dac";
				#io-channels-cells = <1>;
				reg = <1>;
				status = "disabled";
			};

			dac2: dac@2 {
				compatible = "st,stm32-dac";
				#io-channels-cells = <1>;
				reg = <2>;
				status = "disabled";
			};
		};

		uart7: serial@40018000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40018000 0x400>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
			clocks = <&rcc UART7_K>;
			status = "disabled";
		};

		uart8: serial@40019000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40019000 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
			clocks = <&rcc UART8_K>;
			status = "disabled";
		};

		timers1: timer@44000000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x44000000 0x400>;
			clocks = <&rcc TIM1_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@0 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <0>;
				status = "disabled";
			};
		};

		timers8: timer@44001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x44001000 0x400>;
			clocks = <&rcc TIM8_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@7 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <7>;
				status = "disabled";
			};
		};

		usart6: serial@44003000 {
			compatible = "st,stm32h7-uart";
			reg = <0x44003000 0x400>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
			clocks = <&rcc USART6_K>;
			status = "disabled";
		};

		timers15: timer@44006000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x44006000 0x400>;
			clocks = <&rcc TIM15_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@14 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <14>;
				status = "disabled";
			};
		};

		timers16: timer@44007000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x44007000 0x400>;
			clocks = <&rcc TIM16_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};
			timer@15 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <15>;
				status = "disabled";
			};
		};

		timers17: timer@44008000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x44008000 0x400>;
			clocks = <&rcc TIM17_K>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
			};

			timer@16 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <16>;
				status = "disabled";
			};
		};

		dma1: dma@48000000 {
			compatible = "st,stm32-dma";
			reg = <0x48000000 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc DMA1>;
			#dma-cells = <4>;
			st,mem2mem;
			dma-requests = <8>;
		};

		dma2: dma@48001000 {
			compatible = "st,stm32-dma";
			reg = <0x48001000 0x400>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc DMA2>;
			#dma-cells = <4>;
			st,mem2mem;
			dma-requests = <8>;
		};

		dmamux1: dma-router@48002000 {
			compatible = "st,stm32h7-dmamux";
			reg = <0x48002000 0x1c>;
			#dma-cells = <3>;
			dma-requests = <128>;
			dma-masters = <&dma1 &dma2>;
			dma-channels = <16>;
			clocks = <&rcc DMAMUX>;
		};

		rcc: rcc@50000000 {
			compatible = "st,stm32mp1-rcc", "syscon";
			reg = <0x50000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lptimer2: timer@50021000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x50021000 0x400>;
			clocks = <&rcc LPTIM2_K>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				#pwm-cells = <3>;
				status = "disabled";
			};

			trigger@1 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <1>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-lptimer-counter";
				status = "disabled";
			};
		};

		lptimer3: timer@50022000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x50022000 0x400>;
			clocks = <&rcc LPTIM3_K>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				#pwm-cells = <3>;
				status = "disabled";
			};

			trigger@2 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <2>;
				status = "disabled";
			};
		};

		lptimer4: timer@50023000 {
			compatible = "st,stm32-lptimer";
			reg = <0x50023000 0x400>;
			clocks = <&rcc LPTIM4_K>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		lptimer5: timer@50024000 {
			compatible = "st,stm32-lptimer";
			reg = <0x50024000 0x400>;
			clocks = <&rcc LPTIM5_K>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		vrefbuf: vrefbuf@50025000 {
			compatible = "st,stm32-vrefbuf";
			reg = <0x50025000 0x8>;
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <2500000>;
			clocks = <&rcc VREF>;
			status = "disabled";
		};

		cryp1: cryp@54001000 {
			compatible = "st,stm32mp1-cryp";
			reg = <0x54001000 0x400>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc CRYP1>;
			resets = <&rcc CRYP1_R>;
			status = "disabled";
		};

		rng1: rng@54003000 {
			compatible = "st,stm32-rng";
			reg = <0x54003000 0x400>;
			clocks = <&rcc RNG1_K>;
			resets = <&rcc RNG1_R>;
			status = "disabled";
		};

		mdma1: dma@58000000 {
			compatible = "st,stm32h7-mdma";
			reg = <0x58000000 0x1000>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc MDMA>;
			#dma-cells = <5>;
			dma-channels = <32>;
			dma-requests = <48>;
		};

		crc1: crc@58009000 {
			compatible = "st,stm32f7-crc";
			reg = <0x58009000 0x400>;
			clocks = <&rcc CRC1>;
			status = "disabled";
		};

		dsi: dsi@5a000000 {
			compatible = "st,stm32-dsi";
			reg = <0x5a000000 0x800>;
			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
			clock-names = "pclk", "ref", "px_clk";
			resets = <&rcc DSI_R>;
			reset-names = "apb";
			status = "disabled";
		};

		ltdc: display-controller@5a001000 {
			compatible = "st,stm32-ltdc";
			reg = <0x5a001000 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc LTDC_PX>;
			clock-names = "lcd";
			resets = <&rcc LTDC_R>;
			status = "disabled";
		};

		usart1: serial@5c000000 {
			compatible = "st,stm32h7-uart";
			reg = <0x5c000000 0x400>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
			clocks = <&rcc USART1_K>;
			status = "disabled";
		};

		i2c4: i2c@5c002000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x5c002000 0x400>;
			interrupt-names = "event", "error";
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C4_K>;
			resets = <&rcc I2C4_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c6: i2c@5c009000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x5c009000 0x400>;
			interrupt-names = "event", "error";
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C6_K>;
			resets = <&rcc I2C6_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
8471a202 LB	1	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	2	/*
	3	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	4	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	5	*/
	6	#include <dt-bindings/interrupt-controller/arm-gic.h>
3599a8af	7	#include <dt-bindings/clock/stm32mp1-clks.h>
bde22824	8	#include <dt-bindings/reset/stm32mp1-resets.h>
8471a202 LB	9
	10	/ {
	11	#address-cells = <1>;
	12	#size-cells = <1>;
	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu0: cpu@0 {
	19	compatible = "arm,cortex-a7";
	20	device_type = "cpu";
	21	reg = <0>;
	22	};
	23
	24	cpu1: cpu@1 {
	25	compatible = "arm,cortex-a7";
	26	device_type = "cpu";
	27	reg = <1>;
	28	};
	29	};
	30
	31	psci {
	32	compatible = "arm,psci";
	33	method = "smc";
	34	cpu_off = <0x84000002>;
	35	cpu_on = <0x84000003>;
	36	};
	37
	38	aliases {
	39	gpio0 = &gpioa;
	40	gpio1 = &gpiob;
	41	gpio2 = &gpioc;
	42	gpio3 = &gpiod;
	43	gpio4 = &gpioe;
	44	gpio5 = &gpiof;
	45	gpio6 = &gpiog;
	46	gpio7 = &gpioh;
	47	gpio8 = &gpioi;
	48	gpio9 = &gpioj;
	49	gpio10 = &gpiok;
	50	};
	51
	52	intc: interrupt-controller@a0021000 {
	53	compatible = "arm,cortex-a7-gic";
	54	#interrupt-cells = <3>;
	55	interrupt-controller;
	56	reg = <0xa0021000 0x1000>,
	57	<0xa0022000 0x2000>;
	58	};
	59
	60	timer {
	61	compatible = "arm,armv7-timer";
	62	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	63	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	64	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	65	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	66	interrupt-parent = <&intc>;
	67	};
	68
	69	clocks {
	70	clk_hse: clk-hse {
	71	#clock-cells = <0>;
	72	compatible = "fixed-clock";
73	clock-frequency = <24000000>;
74	};
75
8471a202 LB	76	clk_hsi: clk-hsi {
	77	#clock-cells = <0>;
	78	compatible = "fixed-clock";
	79	clock-frequency = <64000000>;
	80	};
	81
	82	clk_lse: clk-lse {
	83	#clock-cells = <0>;
	84	compatible = "fixed-clock";
	85	clock-frequency = <32768>;
	86	};
	87
	88	clk_lsi: clk-lsi {
	89	#clock-cells = <0>;
	90	compatible = "fixed-clock";
	91	clock-frequency = <32000>;
	92	};
	93
	94	clk_csi: clk-csi {
	95	#clock-cells = <0>;
	96	compatible = "fixed-clock";
	97	clock-frequency = <4000000>;
	98	};
8471a202 LB	99	};
	100
	101	soc {
	102	compatible = "simple-bus";
	103	#address-cells = <1>;
	104	#size-cells = <1>;
	105	interrupt-parent = <&intc>;
	106	ranges;
	107
61fc211c FG	108	timers2: timer@40000000 {
	109	#address-cells = <1>;
	110	#size-cells = <0>;
	111	compatible = "st,stm32-timers";
	112	reg = <0x40000000 0x400>;
	113	clocks = <&rcc TIM2_K>;
	114	clock-names = "int";
	115	status = "disabled";
	116
	117	pwm {
	118	compatible = "st,stm32-pwm";
	119	status = "disabled";
	120	};
	121
	122	timer@1 {
	123	compatible = "st,stm32h7-timer-trigger";
	124	reg = <1>;
	125	status = "disabled";
	126	};
	127	};
	128
	129	timers3: timer@40001000 {
	130	#address-cells = <1>;
	131	#size-cells = <0>;
	132	compatible = "st,stm32-timers";
	133	reg = <0x40001000 0x400>;
	134	clocks = <&rcc TIM3_K>;
	135	clock-names = "int";
	136	status = "disabled";
	137
	138	pwm {
	139	compatible = "st,stm32-pwm";
	140	status = "disabled";
	141	};
	142
	143	timer@2 {
	144	compatible = "st,stm32h7-timer-trigger";
	145	reg = <2>;
	146	status = "disabled";
	147	};
	148	};
	149
	150	timers4: timer@40002000 {
	151	#address-cells = <1>;
	152	#size-cells = <0>;
	153	compatible = "st,stm32-timers";
	154	reg = <0x40002000 0x400>;
	155	clocks = <&rcc TIM4_K>;
	156	clock-names = "int";
	157	status = "disabled";
	158
	159	pwm {
	160	compatible = "st,stm32-pwm";
	161	status = "disabled";
	162	};
	163
	164	timer@3 {
	165	compatible = "st,stm32h7-timer-trigger";
	166	reg = <3>;
	167	status = "disabled";
	168	};
	169	};
	170
	171	timers5: timer@40003000 {
172	#address-cells = <1>;
173	#size-cells = <0>;
174	compatible = "st,stm32-timers";
175	reg = <0x40003000 0x400>;
176	clocks = <&rcc TIM5_K>;
177	clock-names = "int";
178	status = "disabled";
179
180	pwm {
181	compatible = "st,stm32-pwm";
182	status = "disabled";
183	};
184
185	timer@4 {
186	compatible = "st,stm32h7-timer-trigger";
187	reg = <4>;
188	status = "disabled";
189	};
190	};
191
192	timers6: timer@40004000 {
193	#address-cells = <1>;
194	#size-cells = <0>;
195	compatible = "st,stm32-timers";
196	reg = <0x40004000 0x400>;
197	clocks = <&rcc TIM6_K>;
198	clock-names = "int";
199	status = "disabled";
200
201	timer@5 {
202	compatible = "st,stm32h7-timer-trigger";
203	reg = <5>;
204	status = "disabled";
205	};
206	};
207
208	timers7: timer@40005000 {
209	#address-cells = <1>;
210	#size-cells = <0>;
211	compatible = "st,stm32-timers";
212	reg = <0x40005000 0x400>;
213	clocks = <&rcc TIM7_K>;
214	clock-names = "int";
215	status = "disabled";
216
217	timer@6 {
218	compatible = "st,stm32h7-timer-trigger";
219	reg = <6>;
220	status = "disabled";
221	};
222	};
223
224	timers12: timer@40006000 {
225	#address-cells = <1>;
226	#size-cells = <0>;
227	compatible = "st,stm32-timers";
228	reg = <0x40006000 0x400>;
229	clocks = <&rcc TIM12_K>;
230	clock-names = "int";
231	status = "disabled";
232
233	pwm {
234	compatible = "st,stm32-pwm";
235	status = "disabled";
236	};
237
238	timer@11 {
239	compatible = "st,stm32h7-timer-trigger";
240	reg = <11>;
241	status = "disabled";
242	};
243	};
244
245	timers13: timer@40007000 {
246	#address-cells = <1>;
247	#size-cells = <0>;
248	compatible = "st,stm32-timers";
249	reg = <0x40007000 0x400>;
250	clocks = <&rcc TIM13_K>;
251	clock-names = "int";
252	status = "disabled";
253
254	pwm {
255	compatible = "st,stm32-pwm";
256	status = "disabled";
257	};
258
259	timer@12 {
260	compatible = "st,stm32h7-timer-trigger";
261	reg = <12>;
262	status = "disabled";
263	};
264	};
265
266	timers14: timer@40008000 {
267	#address-cells = <1>;
268	#size-cells = <0>;
269	compatible = "st,stm32-timers";
270	reg = <0x40008000 0x400>;
271	clocks = <&rcc TIM14_K>;
272	clock-names = "int";
273	status = "disabled";
274
275	pwm {
276	compatible = "st,stm32-pwm";
277	status = "disabled";
278	};
279
280	timer@13 {
281	compatible = "st,stm32h7-timer-trigger";
282	reg = <13>;
283	status = "disabled";
284	};
285	};
286
966ed878 FG	287	lptimer1: timer@40009000 {
	288	#address-cells = <1>;
	289	#size-cells = <0>;
	290	compatible = "st,stm32-lptimer";
	291	reg = <0x40009000 0x400>;
	292	clocks = <&rcc LPTIM1_K>;
	293	clock-names = "mux";
	294	status = "disabled";
	295
	296	pwm {
	297	compatible = "st,stm32-pwm-lp";
	298	#pwm-cells = <3>;
	299	status = "disabled";
	300	};
	301
	302	trigger@0 {
	303	compatible = "st,stm32-lptimer-trigger";
	304	reg = <0>;
	305	status = "disabled";
	306	};
	307
	308	counter {
	309	compatible = "st,stm32-lptimer-counter";
	310	status = "disabled";
	311	};
	312	};
	313
8471a202 LB	314	usart2: serial@4000e000 {
	315	compatible = "st,stm32h7-uart";
	316	reg = <0x4000e000 0x400>;
	317	interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
3599a8af	318	clocks = <&rcc USART2_K>;
8471a202 LB	319	status = "disabled";
	320	};
	321
	322	usart3: serial@4000f000 {
	323	compatible = "st,stm32h7-uart";
	324	reg = <0x4000f000 0x400>;
	325	interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
3599a8af	326	clocks = <&rcc USART3_K>;
8471a202 LB	327	status = "disabled";
	328	};
	329
	330	uart4: serial@40010000 {
	331	compatible = "st,stm32h7-uart";
	332	reg = <0x40010000 0x400>;
	333	interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
3599a8af	334	clocks = <&rcc UART4_K>;
8471a202 LB	335	status = "disabled";
	336	};
	337
	338	uart5: serial@40011000 {
	339	compatible = "st,stm32h7-uart";
	340	reg = <0x40011000 0x400>;
	341	interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
3599a8af	342	clocks = <&rcc UART5_K>;
8471a202 LB	343	status = "disabled";
	344	};
	345
d126e86f PYM	346	i2c1: i2c@40012000 {
	347	compatible = "st,stm32f7-i2c";
	348	reg = <0x40012000 0x400>;
	349	interrupt-names = "event", "error";
	350	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	351	<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	352	clocks = <&rcc I2C1_K>;
	353	resets = <&rcc I2C1_R>;
	354	#address-cells = <1>;
	355	#size-cells = <0>;
	356	status = "disabled";
	357	};
	358
	359	i2c2: i2c@40013000 {
	360	compatible = "st,stm32f7-i2c";
	361	reg = <0x40013000 0x400>;
	362	interrupt-names = "event", "error";
	363	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	364	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	365	clocks = <&rcc I2C2_K>;
	366	resets = <&rcc I2C2_R>;
	367	#address-cells = <1>;
	368	#size-cells = <0>;
	369	status = "disabled";
	370	};
	371
	372	i2c3: i2c@40014000 {
	373	compatible = "st,stm32f7-i2c";
	374	reg = <0x40014000 0x400>;
	375	interrupt-names = "event", "error";
	376	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	377	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	378	clocks = <&rcc I2C3_K>;
	379	resets = <&rcc I2C3_R>;
	380	#address-cells = <1>;
	381	#size-cells = <0>;
	382	status = "disabled";
	383	};
	384
	385	i2c5: i2c@40015000 {
	386	compatible = "st,stm32f7-i2c";
	387	reg = <0x40015000 0x400>;
	388	interrupt-names = "event", "error";
	389	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	390	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	391	clocks = <&rcc I2C5_K>;
	392	resets = <&rcc I2C5_R>;
	393	#address-cells = <1>;
	394	#size-cells = <0>;
	395	status = "disabled";
	396	};
	397
da6cddc7 FG	398	dac: dac@40017000 {
	399	compatible = "st,stm32h7-dac-core";
	400	reg = <0x40017000 0x400>;
	401	clocks = <&rcc DAC12>;
	402	clock-names = "pclk";
	403	#address-cells = <1>;
	404	#size-cells = <0>;
	405	status = "disabled";
	406
	407	dac1: dac@1 {
	408	compatible = "st,stm32-dac";
	409	#io-channels-cells = <1>;
	410	reg = <1>;
	411	status = "disabled";
	412	};
	413
	414	dac2: dac@2 {
	415	compatible = "st,stm32-dac";
	416	#io-channels-cells = <1>;
	417	reg = <2>;
	418	status = "disabled";
	419	};
	420	};
	421
8471a202 LB	422	uart7: serial@40018000 {
	423	compatible = "st,stm32h7-uart";
	424	reg = <0x40018000 0x400>;
	425	interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
3599a8af	426	clocks = <&rcc UART7_K>;
8471a202 LB	427	status = "disabled";
	428	};
	429
	430	uart8: serial@40019000 {
	431	compatible = "st,stm32h7-uart";
	432	reg = <0x40019000 0x400>;
	433	interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
3599a8af	434	clocks = <&rcc UART8_K>;
8471a202 LB	435	status = "disabled";
	436	};
	437
61fc211c FG	438	timers1: timer@44000000 {
	439	#address-cells = <1>;
	440	#size-cells = <0>;
	441	compatible = "st,stm32-timers";
	442	reg = <0x44000000 0x400>;
	443	clocks = <&rcc TIM1_K>;
	444	clock-names = "int";
	445	status = "disabled";
	446
	447	pwm {
	448	compatible = "st,stm32-pwm";
	449	status = "disabled";
	450	};
	451
	452	timer@0 {
	453	compatible = "st,stm32h7-timer-trigger";
	454	reg = <0>;
	455	status = "disabled";
	456	};
	457	};
	458
	459	timers8: timer@44001000 {
	460	#address-cells = <1>;
	461	#size-cells = <0>;
	462	compatible = "st,stm32-timers";
	463	reg = <0x44001000 0x400>;
	464	clocks = <&rcc TIM8_K>;
	465	clock-names = "int";
	466	status = "disabled";
	467
	468	pwm {
	469	compatible = "st,stm32-pwm";
	470	status = "disabled";
	471	};
	472
	473	timer@7 {
	474	compatible = "st,stm32h7-timer-trigger";
	475	reg = <7>;
	476	status = "disabled";
	477	};
	478	};
	479
8471a202 LB	480	usart6: serial@44003000 {
	481	compatible = "st,stm32h7-uart";
	482	reg = <0x44003000 0x400>;
	483	interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
3599a8af	484	clocks = <&rcc USART6_K>;
8471a202 LB	485	status = "disabled";
	486	};
	487
61fc211c FG	488	timers15: timer@44006000 {
	489	#address-cells = <1>;
	490	#size-cells = <0>;
	491	compatible = "st,stm32-timers";
	492	reg = <0x44006000 0x400>;
	493	clocks = <&rcc TIM15_K>;
	494	clock-names = "int";
	495	status = "disabled";
	496
	497	pwm {
	498	compatible = "st,stm32-pwm";
	499	status = "disabled";
	500	};
	501
	502	timer@14 {
	503	compatible = "st,stm32h7-timer-trigger";
	504	reg = <14>;
	505	status = "disabled";
	506	};
	507	};
	508
	509	timers16: timer@44007000 {
	510	#address-cells = <1>;
	511	#size-cells = <0>;
	512	compatible = "st,stm32-timers";
	513	reg = <0x44007000 0x400>;
	514	clocks = <&rcc TIM16_K>;
	515	clock-names = "int";
	516	status = "disabled";
	517
	518	pwm {
	519	compatible = "st,stm32-pwm";
	520	status = "disabled";
	521	};
	522	timer@15 {
	523	compatible = "st,stm32h7-timer-trigger";
	524	reg = <15>;
	525	status = "disabled";
	526	};
	527	};
	528
	529	timers17: timer@44008000 {
	530	#address-cells = <1>;
	531	#size-cells = <0>;
	532	compatible = "st,stm32-timers";
	533	reg = <0x44008000 0x400>;
	534	clocks = <&rcc TIM17_K>;
	535	clock-names = "int";
	536	status = "disabled";
	537
	538	pwm {
	539	compatible = "st,stm32-pwm";
	540	status = "disabled";
	541	};
	542
	543	timer@16 {
	544	compatible = "st,stm32h7-timer-trigger";
	545	reg = <16>;
	546	status = "disabled";
	547	};
	548	};
	549
ea1c404e PYM	550	dma1: dma@48000000 {
	551	compatible = "st,stm32-dma";
	552	reg = <0x48000000 0x400>;
	553	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	554	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	555	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	556	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	557	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	558	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	559	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	560	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	561	clocks = <&rcc DMA1>;
	562	#dma-cells = <4>;
	563	st,mem2mem;
1cffb560	564	dma-requests = <8>;
ea1c404e PYM	565	};
	566
	567	dma2: dma@48001000 {
	568	compatible = "st,stm32-dma";
	569	reg = <0x48001000 0x400>;
	570	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	571	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	572	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	573	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	574	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	575	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	576	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	577	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	578	clocks = <&rcc DMA2>;
	579	#dma-cells = <4>;
	580	st,mem2mem;
1cffb560 PYM	581	dma-requests = <8>;
	582	};
	583
	584	dmamux1: dma-router@48002000 {
	585	compatible = "st,stm32h7-dmamux";
	586	reg = <0x48002000 0x1c>;
	587	#dma-cells = <3>;
	588	dma-requests = <128>;
	589	dma-masters = <&dma1 &dma2>;
	590	dma-channels = <16>;
	591	clocks = <&rcc DMAMUX>;
ea1c404e PYM	592	};
ea1c404e PYM	593
3599a8af GF	594	rcc: rcc@50000000 {
	595	compatible = "st,stm32mp1-rcc", "syscon";
	596	reg = <0x50000000 0x1000>;
	597	#clock-cells = <1>;
	598	#reset-cells = <1>;
	599	};
	600
966ed878 FG	601	lptimer2: timer@50021000 {
	602	#address-cells = <1>;
	603	#size-cells = <0>;
	604	compatible = "st,stm32-lptimer";
	605	reg = <0x50021000 0x400>;
	606	clocks = <&rcc LPTIM2_K>;
	607	clock-names = "mux";
	608	status = "disabled";
	609
	610	pwm {
	611	compatible = "st,stm32-pwm-lp";
	612	#pwm-cells = <3>;
	613	status = "disabled";
	614	};
	615
	616	trigger@1 {
	617	compatible = "st,stm32-lptimer-trigger";
	618	reg = <1>;
	619	status = "disabled";
	620	};
	621
	622	counter {
	623	compatible = "st,stm32-lptimer-counter";
	624	status = "disabled";
	625	};
	626	};
	627
	628	lptimer3: timer@50022000 {
	629	#address-cells = <1>;
	630	#size-cells = <0>;
	631	compatible = "st,stm32-lptimer";
	632	reg = <0x50022000 0x400>;
	633	clocks = <&rcc LPTIM3_K>;
	634	clock-names = "mux";
	635	status = "disabled";
	636
	637	pwm {
	638	compatible = "st,stm32-pwm-lp";
	639	#pwm-cells = <3>;
	640	status = "disabled";
	641	};
	642
	643	trigger@2 {
	644	compatible = "st,stm32-lptimer-trigger";
	645	reg = <2>;
	646	status = "disabled";
	647	};
	648	};
	649
	650	lptimer4: timer@50023000 {
	651	compatible = "st,stm32-lptimer";
	652	reg = <0x50023000 0x400>;
	653	clocks = <&rcc LPTIM4_K>;
	654	clock-names = "mux";
	655	status = "disabled";
	656
	657	pwm {
	658	compatible = "st,stm32-pwm-lp";
	659	#pwm-cells = <3>;
	660	status = "disabled";
	661	};
	662	};
	663
	664	lptimer5: timer@50024000 {
665	compatible = "st,stm32-lptimer";
666	reg = <0x50024000 0x400>;
667	clocks = <&rcc LPTIM5_K>;
668	clock-names = "mux";
669	status = "disabled";
670
671	pwm {
672	compatible = "st,stm32-pwm-lp";
673	#pwm-cells = <3>;
674	status = "disabled";
675	};
676	};
677
9f790afb FG	678	vrefbuf: vrefbuf@50025000 {
	679	compatible = "st,stm32-vrefbuf";
	680	reg = <0x50025000 0x8>;
	681	regulator-min-microvolt = <1500000>;
	682	regulator-max-microvolt = <2500000>;
	683	clocks = <&rcc VREF>;
	684	status = "disabled";
	685	};
	686
fc9962c9 LD	687	cryp1: cryp@54001000 {
	688	compatible = "st,stm32mp1-cryp";
	689	reg = <0x54001000 0x400>;
	690	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	691	clocks = <&rcc CRYP1>;
	692	resets = <&rcc CRYP1_R>;
	693	status = "disabled";
	694	};
	695
6973f0a0 LD	696	rng1: rng@54003000 {
	697	compatible = "st,stm32-rng";
	698	reg = <0x54003000 0x400>;
	699	clocks = <&rcc RNG1_K>;
	700	resets = <&rcc RNG1_R>;
	701	status = "disabled";
	702	};
	703
8ecf910a PYM	704	mdma1: dma@58000000 {
	705	compatible = "st,stm32h7-mdma";
	706	reg = <0x58000000 0x1000>;
	707	interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
	708	clocks = <&rcc MDMA>;
	709	#dma-cells = <5>;
	710	dma-channels = <32>;
	711	dma-requests = <48>;
	712	};
	713
8b2820ab LD	714	crc1: crc@58009000 {
	715	compatible = "st,stm32f7-crc";
	716	reg = <0x58009000 0x400>;
	717	clocks = <&rcc CRC1>;
	718	status = "disabled";
	719	};
	720
9d603e44	721	dsi: dsi@5a000000 {
	722	compatible = "st,stm32-dsi";
	723	reg = <0x5a000000 0x800>;
	724	clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
	725	clock-names = "pclk", "ref", "px_clk";
	726	resets = <&rcc DSI_R>;
	727	reset-names = "apb";
	728	status = "disabled";
	729	};
	730
570cae63	731	ltdc: display-controller@5a001000 {
	732	compatible = "st,stm32-ltdc";
	733	reg = <0x5a001000 0x400>;
	734	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	735	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	736	clocks = <&rcc LTDC_PX>;
	737	clock-names = "lcd";
	738	resets = <&rcc LTDC_R>;
	739	status = "disabled";
	740	};
	741
8471a202 LB	742	usart1: serial@5c000000 {
	743	compatible = "st,stm32h7-uart";
	744	reg = <0x5c000000 0x400>;
	745	interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
3599a8af	746	clocks = <&rcc USART1_K>;
8471a202 LB	747	status = "disabled";
8471a202 LB	748	};
d126e86f PYM	749
	750	i2c4: i2c@5c002000 {
	751	compatible = "st,stm32f7-i2c";
	752	reg = <0x5c002000 0x400>;
	753	interrupt-names = "event", "error";
	754	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
	755	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	756	clocks = <&rcc I2C4_K>;
	757	resets = <&rcc I2C4_R>;
	758	#address-cells = <1>;
	759	#size-cells = <0>;
	760	status = "disabled";
	761	};
	762
	763	i2c6: i2c@5c009000 {
	764	compatible = "st,stm32f7-i2c";
	765	reg = <0x5c009000 0x400>;
	766	interrupt-names = "event", "error";
	767	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	768	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	769	clocks = <&rcc I2C6_K>;
	770	resets = <&rcc I2C6_R>;
	771	#address-cells = <1>;
	772	#size-cells = <0>;
	773	status = "disabled";
	774	};
8471a202 LB	775	};
8471a202 LB	776	};