projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 7423d2d8 SR |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <sr@denx.de> | |
| 4 | * | |
| 033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
| 6 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 7 | * licensing only applies to this file, and not this project as a | |
| 8 | * whole. | |
| 7423d2d8 | 9 | * |
| 033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of the | |
| 13 | * License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This library is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 033ba3d7 MR |
20 | * Or, alternatively, |
| 21 | * | |
| 22 | * b) Permission is hereby granted, free of charge, to any person | |
| 23 | * obtaining a copy of this software and associated documentation | |
| 24 | * files (the "Software"), to deal in the Software without | |
| 25 | * restriction, including without limitation the rights to use, | |
| 26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 27 | * sell copies of the Software, and to permit persons to whom the | |
| 28 | * Software is furnished to do so, subject to the following | |
| 29 | * conditions: | |
| 30 | * | |
| 31 | * The above copyright notice and this permission notice shall be | |
| 32 | * included in all copies or substantial portions of the Software. | |
| 33 | * | |
| 34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 41 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 7423d2d8 SR |
42 | */ |
| 43 | ||
| 541ce2ca | 44 | #include <dt-bindings/thermal/thermal.h> |
| 1f9f6a78 | 45 | #include <dt-bindings/dma/sun4i-a10.h> |
| 41193869 PL |
46 | #include <dt-bindings/clock/sun4i-a10-ccu.h> |
| 47 | #include <dt-bindings/reset/sun4i-a10-ccu.h> | |
| 7423d2d8 SR |
48 | |
| 49 | / { | |
| 6ab3cf04 MR |
50 | #address-cells = <1>; |
| 51 | #size-cells = <1>; | |
| 69144e3b MR |
52 | interrupt-parent = <&intc>; |
| 53 | ||
| e751cce9 EL |
54 | aliases { |
| 55 | ethernet0 = &emac; | |
| 56 | }; | |
| 57 | ||
| 5790d4ee HG |
58 | chosen { |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <1>; | |
| 61 | ranges; | |
| 62 | ||
| 71299dd4 | 63 | framebuffer-lcd0-hdmi { |
| d8cacaa3 MR |
64 | compatible = "allwinner,simple-framebuffer", |
| 65 | "simple-framebuffer"; | |
| a9f8cda3 | 66 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
| 41193869 PL |
67 | clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, |
| 68 | <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, | |
| 69 | <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; | |
| 5790d4ee HG |
70 | status = "disabled"; |
| 71 | }; | |
| 8cedd662 | 72 | |
| 71299dd4 | 73 | framebuffer-fe0-lcd0-hdmi { |
| d8cacaa3 MR |
74 | compatible = "allwinner,simple-framebuffer", |
| 75 | "simple-framebuffer"; | |
| 8cedd662 | 76 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
| 41193869 PL |
77 | clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, |
| 78 | <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, | |
| 590b0c0c | 79 | <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, |
| 41193869 PL |
80 | <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, |
| 81 | <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; | |
| 8cedd662 HG |
82 | status = "disabled"; |
| 83 | }; | |
| fd18c7ea | 84 | |
| 71299dd4 | 85 | framebuffer-fe0-lcd0 { |
| fd18c7ea HG |
86 | compatible = "allwinner,simple-framebuffer", |
| 87 | "simple-framebuffer"; | |
| 88 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
| 41193869 PL |
89 | clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, |
| 90 | <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, | |
| 590b0c0c | 91 | <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, |
| 41193869 | 92 | <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; |
| fd18c7ea HG |
93 | status = "disabled"; |
| 94 | }; | |
| 95 | ||
| 71299dd4 | 96 | framebuffer-fe0-lcd0-tve0 { |
| fd18c7ea HG |
97 | compatible = "allwinner,simple-framebuffer", |
| 98 | "simple-framebuffer"; | |
| 99 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
| 41193869 PL |
100 | clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, |
| 101 | <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, | |
| 590b0c0c | 102 | <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, |
| 41193869 PL |
103 | <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, |
| 104 | <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; | |
| fd18c7ea HG |
105 | status = "disabled"; |
| 106 | }; | |
| 5790d4ee HG |
107 | }; |
| 108 | ||
| 69144e3b | 109 | cpus { |
| 8b2efa89 AB |
110 | #address-cells = <1>; |
| 111 | #size-cells = <0>; | |
| 7294be5d | 112 | cpu0: cpu@0 { |
| 14c44aa5 | 113 | device_type = "cpu"; |
| 69144e3b | 114 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 115 | reg = <0x0>; |
| 41193869 | 116 | clocks = <&ccu CLK_CPU>; |
| 7294be5d CYT |
117 | clock-latency = <244144>; /* 8 32k periods */ |
| 118 | operating-points = < | |
| 8358aada | 119 | /* kHz uV */ |
| 7294be5d | 120 | 1008000 1400000 |
| 8358aada MR |
121 | 912000 1350000 |
| 122 | 864000 1300000 | |
| 123 | 624000 1250000 | |
| 7294be5d CYT |
124 | >; |
| 125 | #cooling-cells = <2>; | |
| 69144e3b MR |
126 | }; |
| 127 | }; | |
| 128 | ||
| 541ce2ca | 129 | thermal-zones { |
| 124d19dc | 130 | cpu-thermal { |
| 541ce2ca CYT |
131 | /* milliseconds */ |
| 132 | polling-delay-passive = <250>; | |
| 133 | polling-delay = <1000>; | |
| 134 | thermal-sensors = <&rtp>; | |
| 135 | ||
| 136 | cooling-maps { | |
| 137 | map0 { | |
| 138 | trip = <&cpu_alert0>; | |
| 139 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 140 | }; | |
| 141 | }; | |
| 142 | ||
| 143 | trips { | |
| 124d19dc | 144 | cpu_alert0: cpu-alert0 { |
| 541ce2ca CYT |
145 | /* milliCelsius */ |
| 146 | temperature = <850000>; | |
| 147 | hysteresis = <2000>; | |
| 148 | type = "passive"; | |
| 149 | }; | |
| 150 | ||
| 124d19dc | 151 | cpu_crit: cpu-crit { |
| 541ce2ca CYT |
152 | /* milliCelsius */ |
| 153 | temperature = <100000>; | |
| 154 | hysteresis = <2000>; | |
| 155 | type = "critical"; | |
| 156 | }; | |
| 157 | }; | |
| 69144e3b MR |
158 | }; |
| 159 | }; | |
| 160 | ||
| 69144e3b MR |
161 | clocks { |
| 162 | #address-cells = <1>; | |
| 163 | #size-cells = <1>; | |
| 164 | ranges; | |
| 165 | ||
| 5c58319f | 166 | osc24M: clk-24M { |
| 69144e3b | 167 | #clock-cells = <0>; |
| 41193869 | 168 | compatible = "fixed-clock"; |
| 92fd6e06 | 169 | clock-frequency = <24000000>; |
| dfb12c0c | 170 | clock-output-names = "osc24M"; |
| 69144e3b MR |
171 | }; |
| 172 | ||
| 5c58319f | 173 | osc32k: clk-32k { |
| 69144e3b MR |
174 | #clock-cells = <0>; |
| 175 | compatible = "fixed-clock"; | |
| 176 | clock-frequency = <32768>; | |
| dfb12c0c | 177 | clock-output-names = "osc32k"; |
| 69144e3b | 178 | }; |
| 69144e3b MR |
179 | }; |
| 180 | ||
| 0df4cf33 CYT |
181 | de: display-engine { |
| 182 | compatible = "allwinner,sun4i-a10-display-engine"; | |
| 183 | allwinner,pipelines = <&fe0>, <&fe1>; | |
| 184 | status = "disabled"; | |
| 185 | }; | |
| 186 | ||
| 39f8a71b | 187 | soc { |
| 69144e3b MR |
188 | compatible = "simple-bus"; |
| 189 | #address-cells = <1>; | |
| 190 | #size-cells = <1>; | |
| 69144e3b MR |
191 | ranges; |
| 192 | ||
| 37fb1f8d PK |
193 | system-control@1c00000 { |
| 194 | compatible = "allwinner,sun4i-a10-system-control"; | |
| 1fbc1517 MR |
195 | reg = <0x01c00000 0x30>; |
| 196 | #address-cells = <1>; | |
| 197 | #size-cells = <1>; | |
| 198 | ranges; | |
| 199 | ||
| 5841f6c0 | 200 | sram_a: sram@0 { |
| 1fbc1517 MR |
201 | compatible = "mmio-sram"; |
| 202 | reg = <0x00000000 0xc000>; | |
| 203 | #address-cells = <1>; | |
| 204 | #size-cells = <1>; | |
| 205 | ranges = <0 0x00000000 0xc000>; | |
| 206 | ||
| 207 | emac_sram: sram-section@8000 { | |
| 208 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
| 209 | reg = <0x8000 0x4000>; | |
| 210 | status = "disabled"; | |
| 211 | }; | |
| 212 | }; | |
| 213 | ||
| 5841f6c0 | 214 | sram_d: sram@10000 { |
| 1fbc1517 MR |
215 | compatible = "mmio-sram"; |
| 216 | reg = <0x00010000 0x1000>; | |
| 217 | #address-cells = <1>; | |
| 218 | #size-cells = <1>; | |
| 219 | ranges = <0 0x00010000 0x1000>; | |
| 220 | ||
| 5841f6c0 | 221 | otg_sram: sram-section@0 { |
| 1fbc1517 MR |
222 | compatible = "allwinner,sun4i-a10-sram-d"; |
| 223 | reg = <0x0000 0x1000>; | |
| 224 | status = "disabled"; | |
| 225 | }; | |
| 226 | }; | |
| 227 | }; | |
| 228 | ||
| 5841f6c0 | 229 | dma: dma-controller@1c02000 { |
| 1324f532 EL |
230 | compatible = "allwinner,sun4i-a10-dma"; |
| 231 | reg = <0x01c02000 0x1000>; | |
| 232 | interrupts = <27>; | |
| 41193869 | 233 | clocks = <&ccu CLK_AHB_DMA>; |
| 1324f532 EL |
234 | #dma-cells = <2>; |
| 235 | }; | |
| 236 | ||
| 5841f6c0 | 237 | nfc: nand@1c03000 { |
| cefd4860 BB |
238 | compatible = "allwinner,sun4i-a10-nand"; |
| 239 | reg = <0x01c03000 0x1000>; | |
| 240 | interrupts = <37>; | |
| 41193869 | 241 | clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; |
| cefd4860 BB |
242 | clock-names = "ahb", "mod"; |
| 243 | dmas = <&dma SUN4I_DMA_DEDICATED 3>; | |
| 244 | dma-names = "rxtx"; | |
| 245 | status = "disabled"; | |
| 246 | #address-cells = <1>; | |
| 247 | #size-cells = <0>; | |
| 248 | }; | |
| 249 | ||
| 5841f6c0 | 250 | spi0: spi@1c05000 { |
| 65918e26 MR |
251 | compatible = "allwinner,sun4i-a10-spi"; |
| 252 | reg = <0x01c05000 0x1000>; | |
| 253 | interrupts = <10>; | |
| 41193869 | 254 | clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; |
| 65918e26 | 255 | clock-names = "ahb", "mod"; |
| 1f9f6a78 MR |
256 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
| 257 | <&dma SUN4I_DMA_DEDICATED 26>; | |
| 4192ff81 | 258 | dma-names = "rx", "tx"; |
| 65918e26 MR |
259 | status = "disabled"; |
| 260 | #address-cells = <1>; | |
| 261 | #size-cells = <0>; | |
| 262 | }; | |
| 263 | ||
| 5841f6c0 | 264 | spi1: spi@1c06000 { |
| 65918e26 MR |
265 | compatible = "allwinner,sun4i-a10-spi"; |
| 266 | reg = <0x01c06000 0x1000>; | |
| 267 | interrupts = <11>; | |
| 41193869 | 268 | clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; |
| 65918e26 | 269 | clock-names = "ahb", "mod"; |
| 1f9f6a78 MR |
270 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
| 271 | <&dma SUN4I_DMA_DEDICATED 8>; | |
| 4192ff81 | 272 | dma-names = "rx", "tx"; |
| bca0d7d9 MR |
273 | pinctrl-names = "default"; |
| 274 | pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; | |
| 65918e26 MR |
275 | status = "disabled"; |
| 276 | #address-cells = <1>; | |
| 277 | #size-cells = <0>; | |
| 278 | }; | |
| 279 | ||
| 5841f6c0 | 280 | emac: ethernet@1c0b000 { |
| 1c70e099 | 281 | compatible = "allwinner,sun4i-a10-emac"; |
| e38afcb3 MR |
282 | reg = <0x01c0b000 0x1000>; |
| 283 | interrupts = <55>; | |
| 41193869 | 284 | clocks = <&ccu CLK_AHB_EMAC>; |
| 1fbc1517 | 285 | allwinner,sram = <&emac_sram 1>; |
| bca0d7d9 MR |
286 | pinctrl-names = "default"; |
| 287 | pinctrl-0 = <&emac_pins>; | |
| e38afcb3 MR |
288 | status = "disabled"; |
| 289 | }; | |
| 290 | ||
| 5841f6c0 | 291 | mdio: mdio@1c0b080 { |
| 1c70e099 | 292 | compatible = "allwinner,sun4i-a10-mdio"; |
| e38afcb3 MR |
293 | reg = <0x01c0b080 0x14>; |
| 294 | status = "disabled"; | |
| 295 | #address-cells = <1>; | |
| 296 | #size-cells = <0>; | |
| 297 | }; | |
| 298 | ||
| 0df4cf33 CYT |
299 | tcon0: lcd-controller@1c0c000 { |
| 300 | compatible = "allwinner,sun4i-a10-tcon"; | |
| 301 | reg = <0x01c0c000 0x1000>; | |
| 302 | interrupts = <44>; | |
| 303 | resets = <&ccu RST_TCON0>; | |
| 304 | reset-names = "lcd"; | |
| 305 | clocks = <&ccu CLK_AHB_LCD0>, | |
| 306 | <&ccu CLK_TCON0_CH0>, | |
| 307 | <&ccu CLK_TCON0_CH1>; | |
| 308 | clock-names = "ahb", | |
| 309 | "tcon-ch0", | |
| 310 | "tcon-ch1"; | |
| 311 | clock-output-names = "tcon0-pixel-clock"; | |
| 312 | dmas = <&dma SUN4I_DMA_DEDICATED 14>; | |
| 313 | ||
| 314 | ports { | |
| 315 | #address-cells = <1>; | |
| 316 | #size-cells = <0>; | |
| 317 | ||
| 318 | tcon0_in: port@0 { | |
| 319 | #address-cells = <1>; | |
| 320 | #size-cells = <0>; | |
| 321 | reg = <0>; | |
| 322 | ||
| 323 | tcon0_in_be0: endpoint@0 { | |
| 324 | reg = <0>; | |
| 325 | remote-endpoint = <&be0_out_tcon0>; | |
| 326 | }; | |
| 327 | ||
| 328 | tcon0_in_be1: endpoint@1 { | |
| 329 | reg = <1>; | |
| 330 | remote-endpoint = <&be1_out_tcon0>; | |
| 331 | }; | |
| 332 | }; | |
| 333 | ||
| 334 | tcon0_out: port@1 { | |
| 335 | #address-cells = <1>; | |
| 336 | #size-cells = <0>; | |
| 337 | reg = <1>; | |
| 338 | ||
| 339 | tcon0_out_hdmi: endpoint@1 { | |
| 340 | reg = <1>; | |
| 341 | remote-endpoint = <&hdmi_in_tcon0>; | |
| 342 | allwinner,tcon-channel = <1>; | |
| 343 | }; | |
| 344 | }; | |
| 345 | }; | |
| 346 | }; | |
| 347 | ||
| 348 | tcon1: lcd-controller@1c0d000 { | |
| 349 | compatible = "allwinner,sun4i-a10-tcon"; | |
| 350 | reg = <0x01c0d000 0x1000>; | |
| 351 | interrupts = <45>; | |
| 352 | resets = <&ccu RST_TCON1>; | |
| 353 | reset-names = "lcd"; | |
| 354 | clocks = <&ccu CLK_AHB_LCD1>, | |
| 355 | <&ccu CLK_TCON1_CH0>, | |
| 356 | <&ccu CLK_TCON1_CH1>; | |
| 357 | clock-names = "ahb", | |
| 358 | "tcon-ch0", | |
| 359 | "tcon-ch1"; | |
| 360 | clock-output-names = "tcon1-pixel-clock"; | |
| 361 | dmas = <&dma SUN4I_DMA_DEDICATED 15>; | |
| 362 | ||
| 363 | ports { | |
| 364 | #address-cells = <1>; | |
| 365 | #size-cells = <0>; | |
| 366 | ||
| 367 | tcon1_in: port@0 { | |
| 368 | #address-cells = <1>; | |
| 369 | #size-cells = <0>; | |
| 370 | reg = <0>; | |
| 371 | ||
| 372 | tcon1_in_be0: endpoint@0 { | |
| 373 | reg = <0>; | |
| 374 | remote-endpoint = <&be0_out_tcon1>; | |
| 375 | }; | |
| 376 | ||
| 377 | tcon1_in_be1: endpoint@1 { | |
| 378 | reg = <1>; | |
| 379 | remote-endpoint = <&be1_out_tcon1>; | |
| 380 | }; | |
| 381 | }; | |
| 382 | ||
| 383 | tcon1_out: port@1 { | |
| 384 | #address-cells = <1>; | |
| 385 | #size-cells = <0>; | |
| 386 | reg = <1>; | |
| 387 | ||
| 388 | tcon1_out_hdmi: endpoint@1 { | |
| 389 | reg = <1>; | |
| 390 | remote-endpoint = <&hdmi_in_tcon1>; | |
| 391 | allwinner,tcon-channel = <1>; | |
| 392 | }; | |
| 393 | }; | |
| 394 | }; | |
| 395 | }; | |
| 396 | ||
| 5841f6c0 | 397 | mmc0: mmc@1c0f000 { |
| b258b369 DL |
398 | compatible = "allwinner,sun4i-a10-mmc"; |
| 399 | reg = <0x01c0f000 0x1000>; | |
| 41193869 PL |
400 | clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; |
| 401 | clock-names = "ahb", "mmc"; | |
| b258b369 | 402 | interrupts = <32>; |
| bca0d7d9 MR |
403 | pinctrl-names = "default"; |
| 404 | pinctrl-0 = <&mmc0_pins>; | |
| b258b369 | 405 | status = "disabled"; |
| 4c1bb9c3 HG |
406 | #address-cells = <1>; |
| 407 | #size-cells = <0>; | |
| b258b369 DL |
408 | }; |
| 409 | ||
| 5841f6c0 | 410 | mmc1: mmc@1c10000 { |
| b258b369 DL |
411 | compatible = "allwinner,sun4i-a10-mmc"; |
| 412 | reg = <0x01c10000 0x1000>; | |
| 41193869 PL |
413 | clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; |
| 414 | clock-names = "ahb", "mmc"; | |
| b258b369 DL |
415 | interrupts = <33>; |
| 416 | status = "disabled"; | |
| 4c1bb9c3 HG |
417 | #address-cells = <1>; |
| 418 | #size-cells = <0>; | |
| b258b369 DL |
419 | }; |
| 420 | ||
| 5841f6c0 | 421 | mmc2: mmc@1c11000 { |
| b258b369 DL |
422 | compatible = "allwinner,sun4i-a10-mmc"; |
| 423 | reg = <0x01c11000 0x1000>; | |
| 41193869 PL |
424 | clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; |
| 425 | clock-names = "ahb", "mmc"; | |
| b258b369 DL |
426 | interrupts = <34>; |
| 427 | status = "disabled"; | |
| 4c1bb9c3 HG |
428 | #address-cells = <1>; |
| 429 | #size-cells = <0>; | |
| b258b369 DL |
430 | }; |
| 431 | ||
| 5841f6c0 | 432 | mmc3: mmc@1c12000 { |
| b258b369 DL |
433 | compatible = "allwinner,sun4i-a10-mmc"; |
| 434 | reg = <0x01c12000 0x1000>; | |
| 41193869 PL |
435 | clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; |
| 436 | clock-names = "ahb", "mmc"; | |
| b258b369 DL |
437 | interrupts = <35>; |
| 438 | status = "disabled"; | |
| 4c1bb9c3 HG |
439 | #address-cells = <1>; |
| 440 | #size-cells = <0>; | |
| b258b369 DL |
441 | }; |
| 442 | ||
| 5841f6c0 | 443 | usb_otg: usb@1c13000 { |
| ce65037f HG |
444 | compatible = "allwinner,sun4i-a10-musb"; |
| 445 | reg = <0x01c13000 0x0400>; | |
| 41193869 | 446 | clocks = <&ccu CLK_AHB_OTG>; |
| ce65037f HG |
447 | interrupts = <38>; |
| 448 | interrupt-names = "mc"; | |
| 449 | phys = <&usbphy 0>; | |
| 450 | phy-names = "usb"; | |
| 451 | extcon = <&usbphy 0>; | |
| 452 | allwinner,sram = <&otg_sram 1>; | |
| 453 | status = "disabled"; | |
| 454 | }; | |
| 455 | ||
| 5841f6c0 | 456 | usbphy: phy@1c13400 { |
| 6ab1ce24 RB |
457 | #phy-cells = <1>; |
| 458 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
| 459 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 460 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 41193869 | 461 | clocks = <&ccu CLK_USB_PHY>; |
| 6ab1ce24 | 462 | clock-names = "usb_phy"; |
| 41193869 PL |
463 | resets = <&ccu RST_USB_PHY0>, |
| 464 | <&ccu RST_USB_PHY1>, | |
| 465 | <&ccu RST_USB_PHY2>; | |
| 4dba4185 | 466 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; |
| 6ab1ce24 RB |
467 | status = "disabled"; |
| 468 | }; | |
| 469 | ||
| 5841f6c0 | 470 | ehci0: usb@1c14000 { |
| 6ab1ce24 RB |
471 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; |
| 472 | reg = <0x01c14000 0x100>; | |
| 473 | interrupts = <39>; | |
| 41193869 | 474 | clocks = <&ccu CLK_AHB_EHCI0>; |
| 6ab1ce24 RB |
475 | phys = <&usbphy 1>; |
| 476 | phy-names = "usb"; | |
| 477 | status = "disabled"; | |
| 478 | }; | |
| 479 | ||
| 5841f6c0 | 480 | ohci0: usb@1c14400 { |
| 6ab1ce24 RB |
481 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; |
| 482 | reg = <0x01c14400 0x100>; | |
| 483 | interrupts = <64>; | |
| 41193869 | 484 | clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; |
| 6ab1ce24 RB |
485 | phys = <&usbphy 1>; |
| 486 | phy-names = "usb"; | |
| 487 | status = "disabled"; | |
| 488 | }; | |
| 489 | ||
| 5841f6c0 | 490 | crypto: crypto-engine@1c15000 { |
| 56ba8c58 LC |
491 | compatible = "allwinner,sun4i-a10-crypto"; |
| 492 | reg = <0x01c15000 0x1000>; | |
| 493 | interrupts = <86>; | |
| 41193869 | 494 | clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; |
| 56ba8c58 LC |
495 | clock-names = "ahb", "mod"; |
| 496 | }; | |
| 497 | ||
| 0df4cf33 CYT |
498 | hdmi: hdmi@1c16000 { |
| 499 | compatible = "allwinner,sun4i-a10-hdmi"; | |
| 500 | reg = <0x01c16000 0x1000>; | |
| 501 | interrupts = <58>; | |
| 502 | clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, | |
| e17e237c CYT |
503 | <&ccu CLK_PLL_VIDEO0_2X>, |
| 504 | <&ccu CLK_PLL_VIDEO1_2X>; | |
| 0df4cf33 CYT |
505 | clock-names = "ahb", "mod", "pll-0", "pll-1"; |
| 506 | dmas = <&dma SUN4I_DMA_NORMAL 16>, | |
| 507 | <&dma SUN4I_DMA_NORMAL 16>, | |
| 508 | <&dma SUN4I_DMA_DEDICATED 24>; | |
| 509 | dma-names = "ddc-tx", "ddc-rx", "audio-tx"; | |
| 510 | status = "disabled"; | |
| 511 | ||
| 512 | ports { | |
| 513 | #address-cells = <1>; | |
| 514 | #size-cells = <0>; | |
| 515 | ||
| 516 | hdmi_in: port@0 { | |
| 517 | #address-cells = <1>; | |
| 518 | #size-cells = <0>; | |
| 519 | reg = <0>; | |
| 520 | ||
| 521 | hdmi_in_tcon0: endpoint@0 { | |
| 522 | reg = <0>; | |
| 523 | remote-endpoint = <&tcon0_out_hdmi>; | |
| 524 | }; | |
| 525 | ||
| 526 | hdmi_in_tcon1: endpoint@1 { | |
| 527 | reg = <1>; | |
| 528 | remote-endpoint = <&tcon1_out_hdmi>; | |
| 529 | }; | |
| 530 | }; | |
| 531 | ||
| 532 | hdmi_out: port@1 { | |
| 533 | #address-cells = <1>; | |
| 534 | #size-cells = <0>; | |
| 535 | reg = <1>; | |
| 536 | }; | |
| 537 | }; | |
| 538 | }; | |
| 539 | ||
| 5841f6c0 | 540 | spi2: spi@1c17000 { |
| 65918e26 MR |
541 | compatible = "allwinner,sun4i-a10-spi"; |
| 542 | reg = <0x01c17000 0x1000>; | |
| 543 | interrupts = <12>; | |
| 41193869 | 544 | clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; |
| 65918e26 | 545 | clock-names = "ahb", "mod"; |
| 1f9f6a78 MR |
546 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
| 547 | <&dma SUN4I_DMA_DEDICATED 28>; | |
| 4192ff81 | 548 | dma-names = "rx", "tx"; |
| 65918e26 MR |
549 | status = "disabled"; |
| 550 | #address-cells = <1>; | |
| 551 | #size-cells = <0>; | |
| 552 | }; | |
| 553 | ||
| 5841f6c0 | 554 | ahci: sata@1c18000 { |
| 248bd1e2 OS |
555 | compatible = "allwinner,sun4i-a10-ahci"; |
| 556 | reg = <0x01c18000 0x1000>; | |
| 557 | interrupts = <56>; | |
| 41193869 | 558 | clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; |
| 248bd1e2 OS |
559 | status = "disabled"; |
| 560 | }; | |
| 561 | ||
| 5841f6c0 | 562 | ehci1: usb@1c1c000 { |
| 6ab1ce24 RB |
563 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; |
| 564 | reg = <0x01c1c000 0x100>; | |
| 565 | interrupts = <40>; | |
| 41193869 | 566 | clocks = <&ccu CLK_AHB_EHCI1>; |
| 6ab1ce24 RB |
567 | phys = <&usbphy 2>; |
| 568 | phy-names = "usb"; | |
| 569 | status = "disabled"; | |
| 570 | }; | |
| 571 | ||
| 5841f6c0 | 572 | ohci1: usb@1c1c400 { |
| 6ab1ce24 RB |
573 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; |
| 574 | reg = <0x01c1c400 0x100>; | |
| 575 | interrupts = <65>; | |
| 41193869 | 576 | clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; |
| 6ab1ce24 RB |
577 | phys = <&usbphy 2>; |
| 578 | phy-names = "usb"; | |
| 579 | status = "disabled"; | |
| 580 | }; | |
| 581 | ||
| 5841f6c0 | 582 | spi3: spi@1c1f000 { |
| 65918e26 MR |
583 | compatible = "allwinner,sun4i-a10-spi"; |
| 584 | reg = <0x01c1f000 0x1000>; | |
| 585 | interrupts = <50>; | |
| 41193869 | 586 | clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; |
| 65918e26 | 587 | clock-names = "ahb", "mod"; |
| 1f9f6a78 MR |
588 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
| 589 | <&dma SUN4I_DMA_DEDICATED 30>; | |
| 4192ff81 | 590 | dma-names = "rx", "tx"; |
| 65918e26 MR |
591 | status = "disabled"; |
| 592 | #address-cells = <1>; | |
| 593 | #size-cells = <0>; | |
| 594 | }; | |
| 595 | ||
| 5841f6c0 | 596 | ccu: clock@1c20000 { |
| 41193869 PL |
597 | compatible = "allwinner,sun4i-a10-ccu"; |
| 598 | reg = <0x01c20000 0x400>; | |
| 599 | clocks = <&osc24M>, <&osc32k>; | |
| 600 | clock-names = "hosc", "losc"; | |
| 601 | #clock-cells = <1>; | |
| 602 | #reset-cells = <1>; | |
| 603 | }; | |
| 604 | ||
| 5841f6c0 | 605 | intc: interrupt-controller@1c20400 { |
| 09504a7d | 606 | compatible = "allwinner,sun4i-a10-ic"; |
| 69144e3b MR |
607 | reg = <0x01c20400 0x400>; |
| 608 | interrupt-controller; | |
| 609 | #interrupt-cells = <1>; | |
| 610 | }; | |
| 611 | ||
| 5841f6c0 | 612 | pio: pinctrl@1c20800 { |
| 874b4e45 MR |
613 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 614 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 615 | interrupts = <28>; |
| 41193869 | 616 | clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; |
| be7bc6b9 | 617 | clock-names = "apb", "hosc", "losc"; |
| e10911e1 | 618 | gpio-controller; |
| 39138bc6 | 619 | interrupt-controller; |
| b03e0816 | 620 | #interrupt-cells = <3>; |
| e10911e1 | 621 | #gpio-cells = <3>; |
| 581981be | 622 | |
| e53bd761 | 623 | can0_ph_pins: can0-ph-pins { |
| 908370f6 PM |
624 | pins = "PH20", "PH21"; |
| 625 | function = "can"; | |
| 626 | }; | |
| 627 | ||
| e53bd761 | 628 | emac_pins: emac0-pins { |
| 1edcd36f MR |
629 | pins = "PA0", "PA1", "PA2", |
| 630 | "PA3", "PA4", "PA5", "PA6", | |
| 631 | "PA7", "PA8", "PA9", "PA10", | |
| 632 | "PA11", "PA12", "PA13", "PA14", | |
| 633 | "PA15", "PA16"; | |
| 634 | function = "emac"; | |
| 1d5726e9 AB |
635 | }; |
| 636 | ||
| e53bd761 | 637 | i2c0_pins: i2c0-pins { |
| 1edcd36f MR |
638 | pins = "PB0", "PB1"; |
| 639 | function = "i2c0"; | |
| 581981be MR |
640 | }; |
| 641 | ||
| e53bd761 | 642 | i2c1_pins: i2c1-pins { |
| 1edcd36f MR |
643 | pins = "PB18", "PB19"; |
| 644 | function = "i2c1"; | |
| 581981be MR |
645 | }; |
| 646 | ||
| e53bd761 | 647 | i2c2_pins: i2c2-pins { |
| 1edcd36f MR |
648 | pins = "PB20", "PB21"; |
| 649 | function = "i2c2"; | |
| 581981be | 650 | }; |
| 27cce4ff | 651 | |
| e53bd761 | 652 | ir0_rx_pins: ir0-rx-pin { |
| 1edcd36f MR |
653 | pins = "PB4"; |
| 654 | function = "ir0"; | |
| 27cce4ff MR |
655 | }; |
| 656 | ||
| e53bd761 | 657 | ir0_tx_pins: ir0-tx-pin { |
| 1edcd36f MR |
658 | pins = "PB3"; |
| 659 | function = "ir0"; | |
| 27cce4ff MR |
660 | }; |
| 661 | ||
| e53bd761 | 662 | ir1_rx_pins: ir1-rx-pin { |
| 1edcd36f MR |
663 | pins = "PB23"; |
| 664 | function = "ir1"; | |
| 27cce4ff | 665 | }; |
| 496322bc | 666 | |
| e53bd761 | 667 | ir1_tx_pins: ir1-tx-pin { |
| 1edcd36f MR |
668 | pins = "PB22"; |
| 669 | function = "ir1"; | |
| b21da664 | 670 | }; |
| b5f86a3a | 671 | |
| e53bd761 | 672 | mmc0_pins: mmc0-pins { |
| 1edcd36f MR |
673 | pins = "PF0", "PF1", "PF2", |
| 674 | "PF3", "PF4", "PF5"; | |
| 675 | function = "mmc0"; | |
| 676 | drive-strength = <30>; | |
| 80ee72e7 | 677 | bias-pull-up; |
| b5f86a3a HG |
678 | }; |
| 679 | ||
| e53bd761 | 680 | ps2_ch0_pins: ps2-ch0-pins { |
| 1edcd36f MR |
681 | pins = "PI20", "PI21"; |
| 682 | function = "ps2"; | |
| a4e1099a HG |
683 | }; |
| 684 | ||
| e53bd761 | 685 | ps2_ch1_ph_pins: ps2-ch1-ph-pins { |
| 1edcd36f MR |
686 | pins = "PH12", "PH13"; |
| 687 | function = "ps2"; | |
| 469a22e6 MC |
688 | }; |
| 689 | ||
| e53bd761 | 690 | pwm0_pin: pwm0-pin { |
| 1edcd36f MR |
691 | pins = "PB2"; |
| 692 | function = "pwm"; | |
| 469a22e6 MC |
693 | }; |
| 694 | ||
| e53bd761 | 695 | pwm1_pin: pwm1-pin { |
| 1edcd36f MR |
696 | pins = "PI3"; |
| 697 | function = "pwm"; | |
| a4e1099a | 698 | }; |
| ec66d0bb | 699 | |
| e53bd761 | 700 | spdif_tx_pin: spdif-tx-pin { |
| 1edcd36f MR |
701 | pins = "PB13"; |
| 702 | function = "spdif"; | |
| 703 | bias-pull-up; | |
| 03907ab3 AM |
704 | }; |
| 705 | ||
| e53bd761 | 706 | spi0_pi_pins: spi0-pi-pins { |
| 1edcd36f MR |
707 | pins = "PI11", "PI12", "PI13"; |
| 708 | function = "spi0"; | |
| f3022c6c MR |
709 | }; |
| 710 | ||
| e53bd761 | 711 | spi0_cs0_pi_pin: spi0-cs0-pi-pin { |
| 1edcd36f MR |
712 | pins = "PI10"; |
| 713 | function = "spi0"; | |
| ec66d0bb AG |
714 | }; |
| 715 | ||
| e53bd761 | 716 | spi1_pins: spi1-pins { |
| 1edcd36f MR |
717 | pins = "PI17", "PI18", "PI19"; |
| 718 | function = "spi1"; | |
| f3022c6c MR |
719 | }; |
| 720 | ||
| e53bd761 | 721 | spi1_cs0_pin: spi1-cs0-pin { |
| 1edcd36f MR |
722 | pins = "PI16"; |
| 723 | function = "spi1"; | |
| ec66d0bb AG |
724 | }; |
| 725 | ||
| e53bd761 MR |
726 | spi2_pb_pins: spi2-pb-pins { |
| 727 | pins = "PB15", "PB16", "PB17"; | |
| 1edcd36f | 728 | function = "spi2"; |
| ec66d0bb AG |
729 | }; |
| 730 | ||
| e53bd761 MR |
731 | spi2_pc_pins: spi2-pc-pins { |
| 732 | pins = "PC20", "PC21", "PC22"; | |
| 1edcd36f | 733 | function = "spi2"; |
| f3022c6c MR |
734 | }; |
| 735 | ||
| e53bd761 MR |
736 | spi2_cs0_pb_pin: spi2-cs0-pb-pin { |
| 737 | pins = "PB14"; | |
| 1edcd36f | 738 | function = "spi2"; |
| f3022c6c MR |
739 | }; |
| 740 | ||
| e53bd761 MR |
741 | spi2_cs0_pc_pins: spi2-cs0-pc-pin { |
| 742 | pins = "PC19"; | |
| 1edcd36f | 743 | function = "spi2"; |
| ec66d0bb | 744 | }; |
| 1e8d1567 | 745 | |
| e53bd761 | 746 | uart0_pb_pins: uart0-pb-pins { |
| 1edcd36f MR |
747 | pins = "PB22", "PB23"; |
| 748 | function = "uart0"; | |
| 1e8d1567 VP |
749 | }; |
| 750 | ||
| e53bd761 | 751 | uart0_pf_pins: uart0-pf-pins { |
| 1edcd36f MR |
752 | pins = "PF2", "PF4"; |
| 753 | function = "uart0"; | |
| a4e1099a | 754 | }; |
| 79f969f0 | 755 | |
| e53bd761 | 756 | uart1_pins: uart1-pins { |
| 1edcd36f MR |
757 | pins = "PA10", "PA11"; |
| 758 | function = "uart1"; | |
| 79f969f0 | 759 | }; |
| 874b4e45 | 760 | }; |
| 89b3c99f | 761 | |
| 5841f6c0 | 762 | timer@1c20c00 { |
| b4f26440 | 763 | compatible = "allwinner,sun4i-a10-timer"; |
| 69144e3b MR |
764 | reg = <0x01c20c00 0x90>; |
| 765 | interrupts = <22>; | |
| 766 | clocks = <&osc24M>; | |
| 767 | }; | |
| 768 | ||
| 5841f6c0 | 769 | wdt: watchdog@1c20c90 { |
| ca5d04d9 | 770 | compatible = "allwinner,sun4i-a10-wdt"; |
| 69144e3b MR |
771 | reg = <0x01c20c90 0x10>; |
| 772 | }; | |
| 773 | ||
| 5841f6c0 | 774 | rtc: rtc@1c20d00 { |
| 5fc4bc89 | 775 | compatible = "allwinner,sun4i-a10-rtc"; |
| b5d905c7 CC |
776 | reg = <0x01c20d00 0x20>; |
| 777 | interrupts = <24>; | |
| 778 | }; | |
| 779 | ||
| 5841f6c0 | 780 | pwm: pwm@1c20e00 { |
| 4b57a395 AB |
781 | compatible = "allwinner,sun4i-a10-pwm"; |
| 782 | reg = <0x01c20e00 0xc>; | |
| 783 | clocks = <&osc24M>; | |
| 784 | #pwm-cells = <3>; | |
| 785 | status = "disabled"; | |
| 786 | }; | |
| 787 | ||
| 5841f6c0 | 788 | spdif: spdif@1c21000 { |
| 166db83e MC |
789 | #sound-dai-cells = <0>; |
| 790 | compatible = "allwinner,sun4i-a10-spdif"; | |
| 791 | reg = <0x01c21000 0x400>; | |
| 792 | interrupts = <13>; | |
| 41193869 | 793 | clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; |
| 166db83e MC |
794 | clock-names = "apb", "spdif"; |
| 795 | dmas = <&dma SUN4I_DMA_NORMAL 2>, | |
| 796 | <&dma SUN4I_DMA_NORMAL 2>; | |
| 797 | dma-names = "rx", "tx"; | |
| 798 | status = "disabled"; | |
| 799 | }; | |
| 800 | ||
| 5841f6c0 | 801 | ir0: ir@1c21800 { |
| a4e1099a | 802 | compatible = "allwinner,sun4i-a10-ir"; |
| 41193869 | 803 | clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; |
| a4e1099a HG |
804 | clock-names = "apb", "ir"; |
| 805 | interrupts = <5>; | |
| 806 | reg = <0x01c21800 0x40>; | |
| 807 | status = "disabled"; | |
| 808 | }; | |
| 809 | ||
| 5841f6c0 | 810 | ir1: ir@1c21c00 { |
| a4e1099a | 811 | compatible = "allwinner,sun4i-a10-ir"; |
| 41193869 | 812 | clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; |
| a4e1099a HG |
813 | clock-names = "apb", "ir"; |
| 814 | interrupts = <6>; | |
| 815 | reg = <0x01c21c00 0x40>; | |
| 816 | status = "disabled"; | |
| 817 | }; | |
| 818 | ||
| 5841f6c0 | 819 | i2s0: i2s@1c22400 { |
| d84a0c0a PL |
820 | #sound-dai-cells = <0>; |
| 821 | compatible = "allwinner,sun4i-a10-i2s"; | |
| 822 | reg = <0x01c22400 0x400>; | |
| 823 | interrupts = <16>; | |
| 824 | clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; | |
| 825 | clock-names = "apb", "mod"; | |
| 826 | dmas = <&dma SUN4I_DMA_NORMAL 3>, | |
| 827 | <&dma SUN4I_DMA_NORMAL 3>; | |
| 828 | dma-names = "rx", "tx"; | |
| 829 | status = "disabled"; | |
| 830 | }; | |
| 831 | ||
| 5841f6c0 | 832 | lradc: lradc@1c22800 { |
| b0512e15 HG |
833 | compatible = "allwinner,sun4i-a10-lradc-keys"; |
| 834 | reg = <0x01c22800 0x100>; | |
| 835 | interrupts = <31>; | |
| 836 | status = "disabled"; | |
| 837 | }; | |
| 838 | ||
| 5841f6c0 | 839 | codec: codec@1c22c00 { |
| bcf88450 MC |
840 | #sound-dai-cells = <0>; |
| 841 | compatible = "allwinner,sun4i-a10-codec"; | |
| 842 | reg = <0x01c22c00 0x40>; | |
| 843 | interrupts = <30>; | |
| 41193869 | 844 | clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; |
| bcf88450 MC |
845 | clock-names = "apb", "codec"; |
| 846 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
| 847 | <&dma SUN4I_DMA_NORMAL 19>; | |
| 848 | dma-names = "rx", "tx"; | |
| 849 | status = "disabled"; | |
| 850 | }; | |
| 851 | ||
| 5841f6c0 | 852 | sid: eeprom@1c23800 { |
| 043d56ee | 853 | compatible = "allwinner,sun4i-a10-sid"; |
| 2bad969f OS |
854 | reg = <0x01c23800 0x10>; |
| 855 | }; | |
| 856 | ||
| 5841f6c0 | 857 | rtp: rtp@1c25000 { |
| 40dd8f3b | 858 | compatible = "allwinner,sun4i-a10-ts"; |
| 57c8839c HG |
859 | reg = <0x01c25000 0x100>; |
| 860 | interrupts = <29>; | |
| 41e7afb1 | 861 | #thermal-sensor-cells = <0>; |
| 57c8839c HG |
862 | }; |
| 863 | ||
| 5841f6c0 | 864 | uart0: serial@1c28000 { |
| 89b3c99f MR |
865 | compatible = "snps,dw-apb-uart"; |
| 866 | reg = <0x01c28000 0x400>; | |
| 867 | interrupts = <1>; | |
| 868 | reg-shift = <2>; | |
| 869 | reg-io-width = <4>; | |
| 41193869 | 870 | clocks = <&ccu CLK_APB1_UART0>; |
| 89b3c99f MR |
871 | status = "disabled"; |
| 872 | }; | |
| 76f14d0a | 873 | |
| 5841f6c0 | 874 | uart1: serial@1c28400 { |
| 69144e3b MR |
875 | compatible = "snps,dw-apb-uart"; |
| 876 | reg = <0x01c28400 0x400>; | |
| 877 | interrupts = <2>; | |
| 878 | reg-shift = <2>; | |
| 879 | reg-io-width = <4>; | |
| 41193869 | 880 | clocks = <&ccu CLK_APB1_UART1>; |
| 69144e3b MR |
881 | status = "disabled"; |
| 882 | }; | |
| 883 | ||
| 5841f6c0 | 884 | uart2: serial@1c28800 { |
| 76f14d0a MR |
885 | compatible = "snps,dw-apb-uart"; |
| 886 | reg = <0x01c28800 0x400>; | |
| 887 | interrupts = <3>; | |
| 888 | reg-shift = <2>; | |
| 889 | reg-io-width = <4>; | |
| 41193869 | 890 | clocks = <&ccu CLK_APB1_UART2>; |
| 76f14d0a MR |
891 | status = "disabled"; |
| 892 | }; | |
| 893 | ||
| 5841f6c0 | 894 | uart3: serial@1c28c00 { |
| 69144e3b MR |
895 | compatible = "snps,dw-apb-uart"; |
| 896 | reg = <0x01c28c00 0x400>; | |
| 897 | interrupts = <4>; | |
| 898 | reg-shift = <2>; | |
| 899 | reg-io-width = <4>; | |
| 41193869 | 900 | clocks = <&ccu CLK_APB1_UART3>; |
| 69144e3b MR |
901 | status = "disabled"; |
| 902 | }; | |
| 903 | ||
| 5841f6c0 | 904 | uart4: serial@1c29000 { |
| 76f14d0a MR |
905 | compatible = "snps,dw-apb-uart"; |
| 906 | reg = <0x01c29000 0x400>; | |
| 907 | interrupts = <17>; | |
| 908 | reg-shift = <2>; | |
| 909 | reg-io-width = <4>; | |
| 41193869 | 910 | clocks = <&ccu CLK_APB1_UART4>; |
| 76f14d0a MR |
911 | status = "disabled"; |
| 912 | }; | |
| 913 | ||
| 5841f6c0 | 914 | uart5: serial@1c29400 { |
| 76f14d0a MR |
915 | compatible = "snps,dw-apb-uart"; |
| 916 | reg = <0x01c29400 0x400>; | |
| 917 | interrupts = <18>; | |
| 918 | reg-shift = <2>; | |
| 919 | reg-io-width = <4>; | |
| 41193869 | 920 | clocks = <&ccu CLK_APB1_UART5>; |
| 76f14d0a MR |
921 | status = "disabled"; |
| 922 | }; | |
| 923 | ||
| 5841f6c0 | 924 | uart6: serial@1c29800 { |
| 76f14d0a MR |
925 | compatible = "snps,dw-apb-uart"; |
| 926 | reg = <0x01c29800 0x400>; | |
| 927 | interrupts = <19>; | |
| 928 | reg-shift = <2>; | |
| 929 | reg-io-width = <4>; | |
| 41193869 | 930 | clocks = <&ccu CLK_APB1_UART6>; |
| 76f14d0a MR |
931 | status = "disabled"; |
| 932 | }; | |
| 933 | ||
| 5841f6c0 | 934 | uart7: serial@1c29c00 { |
| 76f14d0a MR |
935 | compatible = "snps,dw-apb-uart"; |
| 936 | reg = <0x01c29c00 0x400>; | |
| 937 | interrupts = <20>; | |
| 938 | reg-shift = <2>; | |
| 939 | reg-io-width = <4>; | |
| 41193869 | 940 | clocks = <&ccu CLK_APB1_UART7>; |
| 76f14d0a MR |
941 | status = "disabled"; |
| 942 | }; | |
| f1741fda | 943 | |
| 5841f6c0 | 944 | ps20: ps2@1c2a000 { |
| a2294bd6 PM |
945 | compatible = "allwinner,sun4i-a10-ps2"; |
| 946 | reg = <0x01c2a000 0x400>; | |
| 947 | interrupts = <62>; | |
| 41193869 | 948 | clocks = <&ccu CLK_APB1_PS20>; |
| a2294bd6 PM |
949 | status = "disabled"; |
| 950 | }; | |
| 951 | ||
| 5841f6c0 | 952 | ps21: ps2@1c2a400 { |
| a2294bd6 PM |
953 | compatible = "allwinner,sun4i-a10-ps2"; |
| 954 | reg = <0x01c2a400 0x400>; | |
| 955 | interrupts = <63>; | |
| 41193869 | 956 | clocks = <&ccu CLK_APB1_PS21>; |
| a2294bd6 PM |
957 | status = "disabled"; |
| 958 | }; | |
| 959 | ||
| 5841f6c0 | 960 | i2c0: i2c@1c2ac00 { |
| d275545e | 961 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
962 | reg = <0x01c2ac00 0x400>; |
| 963 | interrupts = <7>; | |
| 41193869 | 964 | clocks = <&ccu CLK_APB1_I2C0>; |
| bca0d7d9 MR |
965 | pinctrl-names = "default"; |
| 966 | pinctrl-0 = <&i2c0_pins>; | |
| f1741fda | 967 | status = "disabled"; |
| 60bbe316 HG |
968 | #address-cells = <1>; |
| 969 | #size-cells = <0>; | |
| f1741fda MR |
970 | }; |
| 971 | ||
| 5841f6c0 | 972 | i2c1: i2c@1c2b000 { |
| d275545e | 973 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
974 | reg = <0x01c2b000 0x400>; |
| 975 | interrupts = <8>; | |
| 41193869 | 976 | clocks = <&ccu CLK_APB1_I2C1>; |
| bca0d7d9 MR |
977 | pinctrl-names = "default"; |
| 978 | pinctrl-0 = <&i2c1_pins>; | |
| f1741fda | 979 | status = "disabled"; |
| 60bbe316 HG |
980 | #address-cells = <1>; |
| 981 | #size-cells = <0>; | |
| f1741fda MR |
982 | }; |
| 983 | ||
| 5841f6c0 | 984 | i2c2: i2c@1c2b400 { |
| d275545e | 985 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
986 | reg = <0x01c2b400 0x400>; |
| 987 | interrupts = <9>; | |
| 41193869 | 988 | clocks = <&ccu CLK_APB1_I2C2>; |
| bca0d7d9 MR |
989 | pinctrl-names = "default"; |
| 990 | pinctrl-0 = <&i2c2_pins>; | |
| f1741fda | 991 | status = "disabled"; |
| 60bbe316 HG |
992 | #address-cells = <1>; |
| 993 | #size-cells = <0>; | |
| f1741fda | 994 | }; |
| 196654ae | 995 | |
| 5841f6c0 | 996 | can0: can@1c2bc00 { |
| adb83474 PM |
997 | compatible = "allwinner,sun4i-a10-can"; |
| 998 | reg = <0x01c2bc00 0x400>; | |
| 999 | interrupts = <26>; | |
| 41193869 | 1000 | clocks = <&ccu CLK_APB1_CAN>; |
| adb83474 PM |
1001 | status = "disabled"; |
| 1002 | }; | |
| 0df4cf33 | 1003 | |
| c0476a31 SVB |
1004 | mali: gpu@1c40000 { |
| 1005 | compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; | |
| 1006 | reg = <0x01c40000 0x10000>; | |
| 1007 | interrupts = <69>, | |
| 1008 | <70>, | |
| 1009 | <71>, | |
| 1010 | <72>, | |
| 1011 | <73>; | |
| 1012 | interrupt-names = "gp", | |
| 1013 | "gpmmu", | |
| 1014 | "pp0", | |
| 1015 | "ppmmu0", | |
| 1016 | "pmu"; | |
| 1017 | clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; | |
| 1018 | clock-names = "bus", "core"; | |
| 1019 | resets = <&ccu RST_GPU>; | |
| 1020 | ||
| 1021 | assigned-clocks = <&ccu CLK_GPU>; | |
| 1022 | assigned-clock-rates = <384000000>; | |
| 1023 | }; | |
| 1024 | ||
| 0df4cf33 CYT |
1025 | fe0: display-frontend@1e00000 { |
| 1026 | compatible = "allwinner,sun4i-a10-display-frontend"; | |
| 1027 | reg = <0x01e00000 0x20000>; | |
| 1028 | interrupts = <47>; | |
| 1029 | clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, | |
| 1030 | <&ccu CLK_DRAM_DE_FE0>; | |
| 1031 | clock-names = "ahb", "mod", | |
| 1032 | "ram"; | |
| 1033 | resets = <&ccu RST_DE_FE0>; | |
| 1034 | ||
| 1035 | ports { | |
| 1036 | #address-cells = <1>; | |
| 1037 | #size-cells = <0>; | |
| 1038 | ||
| 1039 | fe0_out: port@1 { | |
| 1040 | #address-cells = <1>; | |
| 1041 | #size-cells = <0>; | |
| 1042 | reg = <1>; | |
| 1043 | ||
| 1044 | fe0_out_be0: endpoint@0 { | |
| 1045 | reg = <0>; | |
| 1046 | remote-endpoint = <&be0_in_fe0>; | |
| 1047 | }; | |
| 1048 | ||
| 1049 | fe0_out_be1: endpoint@1 { | |
| 1050 | reg = <1>; | |
| 1051 | remote-endpoint = <&be1_in_fe0>; | |
| 1052 | }; | |
| 1053 | }; | |
| 1054 | }; | |
| 1055 | }; | |
| 1056 | ||
| 1057 | fe1: display-frontend@1e20000 { | |
| 1058 | compatible = "allwinner,sun4i-a10-display-frontend"; | |
| 1059 | reg = <0x01e20000 0x20000>; | |
| 1060 | interrupts = <48>; | |
| 1061 | clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, | |
| 1062 | <&ccu CLK_DRAM_DE_FE1>; | |
| 1063 | clock-names = "ahb", "mod", | |
| 1064 | "ram"; | |
| 1065 | resets = <&ccu RST_DE_FE1>; | |
| 1066 | ||
| 1067 | ports { | |
| 1068 | #address-cells = <1>; | |
| 1069 | #size-cells = <0>; | |
| 1070 | ||
| 1071 | fe1_out: port@1 { | |
| 1072 | #address-cells = <1>; | |
| 1073 | #size-cells = <0>; | |
| 1074 | reg = <1>; | |
| 1075 | ||
| 1076 | fe1_out_be0: endpoint@0 { | |
| 1077 | reg = <0>; | |
| 1078 | remote-endpoint = <&be0_in_fe1>; | |
| 1079 | }; | |
| 1080 | ||
| 1081 | fe1_out_be1: endpoint@1 { | |
| 1082 | reg = <1>; | |
| 1083 | remote-endpoint = <&be1_in_fe1>; | |
| 1084 | }; | |
| 1085 | }; | |
| 1086 | }; | |
| 1087 | }; | |
| 1088 | ||
| 1089 | be1: display-backend@1e40000 { | |
| 1090 | compatible = "allwinner,sun4i-a10-display-backend"; | |
| 1091 | reg = <0x01e40000 0x10000>; | |
| 1092 | interrupts = <48>; | |
| 1093 | clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, | |
| 1094 | <&ccu CLK_DRAM_DE_BE1>; | |
| 1095 | clock-names = "ahb", "mod", | |
| 1096 | "ram"; | |
| 1097 | resets = <&ccu RST_DE_BE1>; | |
| 1098 | ||
| 1099 | ports { | |
| 1100 | #address-cells = <1>; | |
| 1101 | #size-cells = <0>; | |
| 1102 | ||
| 1103 | be1_in: port@0 { | |
| 1104 | #address-cells = <1>; | |
| 1105 | #size-cells = <0>; | |
| 1106 | reg = <0>; | |
| 1107 | ||
| 1108 | be1_in_fe0: endpoint@0 { | |
| 1109 | reg = <0>; | |
| 1110 | remote-endpoint = <&fe0_out_be1>; | |
| 1111 | }; | |
| 1112 | ||
| 1113 | be1_in_fe1: endpoint@1 { | |
| 1114 | reg = <1>; | |
| 1115 | remote-endpoint = <&fe1_out_be1>; | |
| 1116 | }; | |
| 1117 | }; | |
| 1118 | ||
| 1119 | be1_out: port@1 { | |
| 1120 | #address-cells = <1>; | |
| 1121 | #size-cells = <0>; | |
| 1122 | reg = <1>; | |
| 1123 | ||
| 1124 | be1_out_tcon0: endpoint@0 { | |
| 1125 | reg = <0>; | |
| bdae4470 | 1126 | remote-endpoint = <&tcon0_in_be1>; |
| 0df4cf33 CYT |
1127 | }; |
| 1128 | ||
| 1129 | be1_out_tcon1: endpoint@1 { | |
| 1130 | reg = <1>; | |
| 1131 | remote-endpoint = <&tcon1_in_be1>; | |
| 1132 | }; | |
| 1133 | }; | |
| 1134 | }; | |
| 1135 | }; | |
| 1136 | ||
| 1137 | be0: display-backend@1e60000 { | |
| 1138 | compatible = "allwinner,sun4i-a10-display-backend"; | |
| 1139 | reg = <0x01e60000 0x10000>; | |
| 1140 | interrupts = <47>; | |
| 1141 | clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, | |
| 1142 | <&ccu CLK_DRAM_DE_BE0>; | |
| 1143 | clock-names = "ahb", "mod", | |
| 1144 | "ram"; | |
| 1145 | resets = <&ccu RST_DE_BE0>; | |
| 1146 | ||
| 1147 | ports { | |
| 1148 | #address-cells = <1>; | |
| 1149 | #size-cells = <0>; | |
| 1150 | ||
| 1151 | be0_in: port@0 { | |
| 1152 | #address-cells = <1>; | |
| 1153 | #size-cells = <0>; | |
| 1154 | reg = <0>; | |
| 1155 | ||
| 1156 | be0_in_fe0: endpoint@0 { | |
| 1157 | reg = <0>; | |
| 1158 | remote-endpoint = <&fe0_out_be0>; | |
| 1159 | }; | |
| 1160 | ||
| 1161 | be0_in_fe1: endpoint@1 { | |
| 1162 | reg = <1>; | |
| 1163 | remote-endpoint = <&fe1_out_be0>; | |
| 1164 | }; | |
| 1165 | }; | |
| 1166 | ||
| 1167 | be0_out: port@1 { | |
| 1168 | #address-cells = <1>; | |
| 1169 | #size-cells = <0>; | |
| 1170 | reg = <1>; | |
| 1171 | ||
| 1172 | be0_out_tcon0: endpoint@0 { | |
| 1173 | reg = <0>; | |
| 1174 | remote-endpoint = <&tcon0_in_be0>; | |
| 1175 | }; | |
| 1176 | ||
| 1177 | be0_out_tcon1: endpoint@1 { | |
| 1178 | reg = <1>; | |
| 1179 | remote-endpoint = <&tcon1_in_be0>; | |
| 1180 | }; | |
| 1181 | }; | |
| 1182 | }; | |
| 1183 | }; | |
| 874b4e45 | 1184 | }; |
| 7423d2d8 | 1185 | }; |