[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / sun4i-a10.dtsi

/*
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&intc>;

	aliases {
		ethernet0 = &emac;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M: osc24M@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		pll4: pll4@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
		};

		pll5: pll5@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: pll6@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
		};

		axi_gates: axi_gates@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-output-names = "axi_dram";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
		};

		ahb_gates: ahb_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",
				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_mp", "ahb_mali400";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
		};

		apb0_gates: apb0_gates@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
				"apb0_ir1", "apb0_keypad";
		};

		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
		};

		apb1_gates: apb1_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_can", "apb1_scr",
				"apb1_ps20", "apb1_ps21", "apb1_uart0",
				"apb1_uart1", "apb1_uart2", "apb1_uart3",
				"apb1_uart4", "apb1_uart5", "apb1_uart6",
				"apb1_uart7";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2";
		};

		mmc3_clk: clk@01c20094 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc3";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun4i-a10-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PA10", "PA11";
				allwinner,function = "uart1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-wdt";
			reg = <0x01c20c90 0x10>;
		};

		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun4i-rtc";
			reg = <0x01c20d00 0x20>;
			interrupts = <24>;
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun4i-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun4i-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&apb1_gates 0>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&apb1_gates 1>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&apb1_gates 2>;
			clock-frequency = <100000>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
7423d2d8 SR	1	/*
	2	* Copyright 2012 Stefan Roese
	3	* Stefan Roese <sr@denx.de>
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
69144e3b	13	/include/ "skeleton.dtsi"
7423d2d8 SR	14
7423d2d8 SR	15	/ {
69144e3b MR	16	interrupt-parent = <&intc>;
69144e3b MR	17
e751cce9 EL	18	aliases {
e751cce9 EL	19	ethernet0 = &emac;
10b302a2 MR	20	serial0 = &uart0;
10b302a2 MR	21	serial1 = &uart1;
e751cce9 EL	22	};
e751cce9 EL	23
69144e3b	24	cpus {
8b2efa89 AB	25	#address-cells = <1>;
8b2efa89 AB	26	#size-cells = <0>;
69144e3b	27	cpu@0 {
14c44aa5	28	device_type = "cpu";
69144e3b	29	compatible = "arm,cortex-a8";
14c44aa5	30	reg = <0x0>;
69144e3b MR	31	};
	32	};
	33
7423d2d8 SR	34	memory {
	35	reg = <0x40000000 0x80000000>;
	36	};
874b4e45	37
69144e3b MR	38	clocks {
	39	#address-cells = <1>;
	40	#size-cells = <1>;
	41	ranges;
	42
	43	/*
	44	* This is a dummy clock, to be used as placeholder on
	45	* other mux clocks when a specific parent clock is not
	46	* yet implemented. It should be dropped when the driver
	47	* is complete.
	48	*/
	49	dummy: dummy {
	50	#clock-cells = <0>;
	51	compatible = "fixed-clock";
	52	clock-frequency = <0>;
	53	};
	54
69144e3b MR	55	osc24M: osc24M@01c20050 {
	56	#clock-cells = <0>;
	57	compatible = "allwinner,sun4i-osc-clk";
	58	reg = <0x01c20050 0x4>;
92fd6e06	59	clock-frequency = <24000000>;
69144e3b MR	60	};
	61
	62	osc32k: osc32k {
	63	#clock-cells = <0>;
	64	compatible = "fixed-clock";
	65	clock-frequency = <32768>;
	66	};
	67
	68	pll1: pll1@01c20000 {
	69	#clock-cells = <0>;
	70	compatible = "allwinner,sun4i-pll1-clk";
	71	reg = <0x01c20000 0x4>;
	72	clocks = <&osc24M>;
	73	};
	74
ec5589f7 EL	75	pll4: pll4@01c20018 {
	76	#clock-cells = <0>;
	77	compatible = "allwinner,sun4i-pll1-clk";
	78	reg = <0x01c20018 0x4>;
	79	clocks = <&osc24M>;
	80	};
	81
c3e5e66b EL	82	pll5: pll5@01c20020 {
	83	#clock-cells = <1>;
	84	compatible = "allwinner,sun4i-pll5-clk";
	85	reg = <0x01c20020 0x4>;
	86	clocks = <&osc24M>;
	87	clock-output-names = "pll5_ddr", "pll5_other";
	88	};
	89
	90	pll6: pll6@01c20028 {
	91	#clock-cells = <1>;
	92	compatible = "allwinner,sun4i-pll6-clk";
	93	reg = <0x01c20028 0x4>;
	94	clocks = <&osc24M>;
	95	clock-output-names = "pll6_sata", "pll6_other", "pll6";
	96	};
	97
69144e3b MR	98	/* dummy is 200M */
	99	cpu: cpu@01c20054 {
	100	#clock-cells = <0>;
	101	compatible = "allwinner,sun4i-cpu-clk";
	102	reg = <0x01c20054 0x4>;
	103	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
	104	};
	105
	106	axi: axi@01c20054 {
	107	#clock-cells = <0>;
	108	compatible = "allwinner,sun4i-axi-clk";
	109	reg = <0x01c20054 0x4>;
	110	clocks = <&cpu>;
	111	};
	112
	113	axi_gates: axi_gates@01c2005c {
	114	#clock-cells = <1>;
	115	compatible = "allwinner,sun4i-axi-gates-clk";
	116	reg = <0x01c2005c 0x4>;
	117	clocks = <&axi>;
	118	clock-output-names = "axi_dram";
	119	};
	120
	121	ahb: ahb@01c20054 {
	122	#clock-cells = <0>;
	123	compatible = "allwinner,sun4i-ahb-clk";
	124	reg = <0x01c20054 0x4>;
	125	clocks = <&axi>;
	126	};
	127
	128	ahb_gates: ahb_gates@01c20060 {
	129	#clock-cells = <1>;
	130	compatible = "allwinner,sun4i-ahb-gates-clk";
	131	reg = <0x01c20060 0x8>;
	132	clocks = <&ahb>;
	133	clock-output-names = "ahb_usb0", "ahb_ehci0",
	134	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
	135	"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
	136	"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
	137	"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
	138	"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
	139	"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
	140	"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
	141	"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
	142	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
	143	"ahb_de_fe1", "ahb_mp", "ahb_mali400";
	144	};
	145
	146	apb0: apb0@01c20054 {
	147	#clock-cells = <0>;
	148	compatible = "allwinner,sun4i-apb0-clk";
	149	reg = <0x01c20054 0x4>;
	150	clocks = <&ahb>;
	151	};
	152
	153	apb0_gates: apb0_gates@01c20068 {
	154	#clock-cells = <1>;
	155	compatible = "allwinner,sun4i-apb0-gates-clk";
	156	reg = <0x01c20068 0x4>;
	157	clocks = <&apb0>;
	158	clock-output-names = "apb0_codec", "apb0_spdif",
	159	"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
	160	"apb0_ir1", "apb0_keypad";
	161	};
162
69144e3b MR	163	apb1_mux: apb1_mux@01c20058 {
	164	#clock-cells = <0>;
	165	compatible = "allwinner,sun4i-apb1-mux-clk";
	166	reg = <0x01c20058 0x4>;
c3e5e66b	167	clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
69144e3b MR	168	};
	169
	170	apb1: apb1@01c20058 {
	171	#clock-cells = <0>;
	172	compatible = "allwinner,sun4i-apb1-clk";
	173	reg = <0x01c20058 0x4>;
	174	clocks = <&apb1_mux>;
	175	};
	176
	177	apb1_gates: apb1_gates@01c2006c {
	178	#clock-cells = <1>;
	179	compatible = "allwinner,sun4i-apb1-gates-clk";
	180	reg = <0x01c2006c 0x4>;
	181	clocks = <&apb1>;
	182	clock-output-names = "apb1_i2c0", "apb1_i2c1",
	183	"apb1_i2c2", "apb1_can", "apb1_scr",
	184	"apb1_ps20", "apb1_ps21", "apb1_uart0",
	185	"apb1_uart1", "apb1_uart2", "apb1_uart3",
	186	"apb1_uart4", "apb1_uart5", "apb1_uart6",
	187	"apb1_uart7";
	188	};
4b756ffb EL	189
	190	nand_clk: clk@01c20080 {
	191	#clock-cells = <0>;
	192	compatible = "allwinner,sun4i-mod0-clk";
	193	reg = <0x01c20080 0x4>;
	194	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	195	clock-output-names = "nand";
	196	};
	197
	198	ms_clk: clk@01c20084 {
	199	#clock-cells = <0>;
	200	compatible = "allwinner,sun4i-mod0-clk";
	201	reg = <0x01c20084 0x4>;
	202	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	203	clock-output-names = "ms";
	204	};
	205
	206	mmc0_clk: clk@01c20088 {
	207	#clock-cells = <0>;
	208	compatible = "allwinner,sun4i-mod0-clk";
	209	reg = <0x01c20088 0x4>;
	210	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	211	clock-output-names = "mmc0";
	212	};
	213
	214	mmc1_clk: clk@01c2008c {
	215	#clock-cells = <0>;
	216	compatible = "allwinner,sun4i-mod0-clk";
	217	reg = <0x01c2008c 0x4>;
	218	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	219	clock-output-names = "mmc1";
	220	};
	221
	222	mmc2_clk: clk@01c20090 {
	223	#clock-cells = <0>;
	224	compatible = "allwinner,sun4i-mod0-clk";
	225	reg = <0x01c20090 0x4>;
	226	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	227	clock-output-names = "mmc2";
	228	};
	229
	230	mmc3_clk: clk@01c20094 {
	231	#clock-cells = <0>;
	232	compatible = "allwinner,sun4i-mod0-clk";
	233	reg = <0x01c20094 0x4>;
	234	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	235	clock-output-names = "mmc3";
	236	};
	237
	238	ts_clk: clk@01c20098 {
	239	#clock-cells = <0>;
	240	compatible = "allwinner,sun4i-mod0-clk";
	241	reg = <0x01c20098 0x4>;
	242	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	243	clock-output-names = "ts";
	244	};
	245
	246	ss_clk: clk@01c2009c {
	247	#clock-cells = <0>;
	248	compatible = "allwinner,sun4i-mod0-clk";
	249	reg = <0x01c2009c 0x4>;
	250	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	251	clock-output-names = "ss";
	252	};
253
254	spi0_clk: clk@01c200a0 {
255	#clock-cells = <0>;
256	compatible = "allwinner,sun4i-mod0-clk";
257	reg = <0x01c200a0 0x4>;
258	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259	clock-output-names = "spi0";
260	};
261
262	spi1_clk: clk@01c200a4 {
263	#clock-cells = <0>;
264	compatible = "allwinner,sun4i-mod0-clk";
265	reg = <0x01c200a4 0x4>;
266	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267	clock-output-names = "spi1";
268	};
269
270	spi2_clk: clk@01c200a8 {
271	#clock-cells = <0>;
272	compatible = "allwinner,sun4i-mod0-clk";
273	reg = <0x01c200a8 0x4>;
274	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275	clock-output-names = "spi2";
276	};
277
278	pata_clk: clk@01c200ac {
279	#clock-cells = <0>;
280	compatible = "allwinner,sun4i-mod0-clk";
281	reg = <0x01c200ac 0x4>;
282	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283	clock-output-names = "pata";
284	};
285
286	ir0_clk: clk@01c200b0 {
287	#clock-cells = <0>;
288	compatible = "allwinner,sun4i-mod0-clk";
289	reg = <0x01c200b0 0x4>;
290	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291	clock-output-names = "ir0";
292	};
293
294	ir1_clk: clk@01c200b4 {
295	#clock-cells = <0>;
296	compatible = "allwinner,sun4i-mod0-clk";
297	reg = <0x01c200b4 0x4>;
298	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299	clock-output-names = "ir1";
300	};
301
302	spi3_clk: clk@01c200d4 {
303	#clock-cells = <0>;
304	compatible = "allwinner,sun4i-mod0-clk";
305	reg = <0x01c200d4 0x4>;
306	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307	clock-output-names = "spi3";
308	};
69144e3b MR	309	};
69144e3b MR	310
b74aec1a	311	soc@01c00000 {
69144e3b MR	312	compatible = "simple-bus";
	313	#address-cells = <1>;
	314	#size-cells = <1>;
69144e3b MR	315	ranges;
69144e3b MR	316
e38afcb3 MR	317	emac: ethernet@01c0b000 {
	318	compatible = "allwinner,sun4i-emac";
	319	reg = <0x01c0b000 0x1000>;
	320	interrupts = <55>;
	321	clocks = <&ahb_gates 17>;
	322	status = "disabled";
	323	};
	324
	325	mdio@01c0b080 {
	326	compatible = "allwinner,sun4i-mdio";
	327	reg = <0x01c0b080 0x14>;
	328	status = "disabled";
	329	#address-cells = <1>;
	330	#size-cells = <0>;
	331	};
	332
69144e3b	333	intc: interrupt-controller@01c20400 {
6def126d	334	compatible = "allwinner,sun4i-ic";
69144e3b MR	335	reg = <0x01c20400 0x400>;
	336	interrupt-controller;
	337	#interrupt-cells = <1>;
	338	};
	339
e10911e1	340	pio: pinctrl@01c20800 {
874b4e45 MR	341	compatible = "allwinner,sun4i-a10-pinctrl";
874b4e45 MR	342	reg = <0x01c20800 0x400>;
39138bc6	343	interrupts = <28>;
36386d6e	344	clocks = <&apb0_gates 5>;
e10911e1	345	gpio-controller;
39138bc6	346	interrupt-controller;
874b4e45 MR	347	#address-cells = <1>;
874b4e45 MR	348	#size-cells = <0>;
e10911e1	349	#gpio-cells = <3>;
581981be MR	350
	351	uart0_pins_a: uart0@0 {
	352	allwinner,pins = "PB22", "PB23";
	353	allwinner,function = "uart0";
	354	allwinner,drive = <0>;
	355	allwinner,pull = <0>;
	356	};
	357
	358	uart0_pins_b: uart0@1 {
	359	allwinner,pins = "PF2", "PF4";
	360	allwinner,function = "uart0";
	361	allwinner,drive = <0>;
	362	allwinner,pull = <0>;
	363	};
	364
	365	uart1_pins_a: uart1@0 {
	366	allwinner,pins = "PA10", "PA11";
	367	allwinner,function = "uart1";
	368	allwinner,drive = <0>;
	369	allwinner,pull = <0>;
	370	};
27cce4ff MR	371
	372	i2c0_pins_a: i2c0@0 {
	373	allwinner,pins = "PB0", "PB1";
	374	allwinner,function = "i2c0";
	375	allwinner,drive = <0>;
	376	allwinner,pull = <0>;
	377	};
	378
	379	i2c1_pins_a: i2c1@0 {
	380	allwinner,pins = "PB18", "PB19";
	381	allwinner,function = "i2c1";
	382	allwinner,drive = <0>;
	383	allwinner,pull = <0>;
	384	};
	385
	386	i2c2_pins_a: i2c2@0 {
	387	allwinner,pins = "PB20", "PB21";
	388	allwinner,function = "i2c2";
	389	allwinner,drive = <0>;
	390	allwinner,pull = <0>;
	391	};
496322bc	392
b21da664 MR	393	emac_pins_a: emac0@0 {
	394	allwinner,pins = "PA0", "PA1", "PA2",
	395	"PA3", "PA4", "PA5", "PA6",
	396	"PA7", "PA8", "PA9", "PA10",
	397	"PA11", "PA12", "PA13", "PA14",
	398	"PA15", "PA16";
	399	allwinner,function = "emac";
	400	allwinner,drive = <0>;
	401	allwinner,pull = <0>;
	402	};
874b4e45	403	};
89b3c99f	404
69144e3b	405	timer@01c20c00 {
b6e1a53b	406	compatible = "allwinner,sun4i-timer";
69144e3b MR	407	reg = <0x01c20c00 0x90>;
	408	interrupts = <22>;
	409	clocks = <&osc24M>;
	410	};
	411
	412	wdt: watchdog@01c20c90 {
0b19b7c2	413	compatible = "allwinner,sun4i-wdt";
69144e3b MR	414	reg = <0x01c20c90 0x10>;
	415	};
	416
b5d905c7 CC	417	rtc: rtc@01c20d00 {
	418	compatible = "allwinner,sun4i-rtc";
	419	reg = <0x01c20d00 0x20>;
	420	interrupts = <24>;
	421	};
	422
2bad969f OS	423	sid: eeprom@01c23800 {
	424	compatible = "allwinner,sun4i-sid";
	425	reg = <0x01c23800 0x10>;
	426	};
	427
57c8839c HG	428	rtp: rtp@01c25000 {
	429	compatible = "allwinner,sun4i-ts";
	430	reg = <0x01c25000 0x100>;
	431	interrupts = <29>;
	432	};
	433
89b3c99f MR	434	uart0: serial@01c28000 {
	435	compatible = "snps,dw-apb-uart";
	436	reg = <0x01c28000 0x400>;
	437	interrupts = <1>;
	438	reg-shift = <2>;
	439	reg-io-width = <4>;
9ff49ec7	440	clocks = <&apb1_gates 16>;
89b3c99f MR	441	status = "disabled";
89b3c99f MR	442	};
76f14d0a	443
69144e3b MR	444	uart1: serial@01c28400 {
	445	compatible = "snps,dw-apb-uart";
	446	reg = <0x01c28400 0x400>;
	447	interrupts = <2>;
	448	reg-shift = <2>;
	449	reg-io-width = <4>;
	450	clocks = <&apb1_gates 17>;
	451	status = "disabled";
	452	};
	453
76f14d0a MR	454	uart2: serial@01c28800 {
	455	compatible = "snps,dw-apb-uart";
	456	reg = <0x01c28800 0x400>;
	457	interrupts = <3>;
	458	reg-shift = <2>;
	459	reg-io-width = <4>;
9ff49ec7	460	clocks = <&apb1_gates 18>;
76f14d0a MR	461	status = "disabled";
	462	};
	463
69144e3b MR	464	uart3: serial@01c28c00 {
	465	compatible = "snps,dw-apb-uart";
	466	reg = <0x01c28c00 0x400>;
	467	interrupts = <4>;
	468	reg-shift = <2>;
	469	reg-io-width = <4>;
	470	clocks = <&apb1_gates 19>;
	471	status = "disabled";
	472	};
	473
76f14d0a MR	474	uart4: serial@01c29000 {
	475	compatible = "snps,dw-apb-uart";
	476	reg = <0x01c29000 0x400>;
	477	interrupts = <17>;
	478	reg-shift = <2>;
	479	reg-io-width = <4>;
9ff49ec7	480	clocks = <&apb1_gates 20>;
76f14d0a MR	481	status = "disabled";
	482	};
	483
	484	uart5: serial@01c29400 {
	485	compatible = "snps,dw-apb-uart";
	486	reg = <0x01c29400 0x400>;
	487	interrupts = <18>;
	488	reg-shift = <2>;
	489	reg-io-width = <4>;
9ff49ec7	490	clocks = <&apb1_gates 21>;
76f14d0a MR	491	status = "disabled";
	492	};
	493
	494	uart6: serial@01c29800 {
	495	compatible = "snps,dw-apb-uart";
	496	reg = <0x01c29800 0x400>;
	497	interrupts = <19>;
	498	reg-shift = <2>;
	499	reg-io-width = <4>;
9ff49ec7	500	clocks = <&apb1_gates 22>;
76f14d0a MR	501	status = "disabled";
	502	};
	503
	504	uart7: serial@01c29c00 {
	505	compatible = "snps,dw-apb-uart";
	506	reg = <0x01c29c00 0x400>;
	507	interrupts = <20>;
	508	reg-shift = <2>;
	509	reg-io-width = <4>;
9ff49ec7	510	clocks = <&apb1_gates 23>;
76f14d0a MR	511	status = "disabled";
76f14d0a MR	512	};
f1741fda MR	513
	514	i2c0: i2c@01c2ac00 {
	515	compatible = "allwinner,sun4i-i2c";
	516	reg = <0x01c2ac00 0x400>;
	517	interrupts = <7>;
	518	clocks = <&apb1_gates 0>;
	519	clock-frequency = <100000>;
	520	status = "disabled";
	521	};
	522
	523	i2c1: i2c@01c2b000 {
	524	compatible = "allwinner,sun4i-i2c";
	525	reg = <0x01c2b000 0x400>;
	526	interrupts = <8>;
	527	clocks = <&apb1_gates 1>;
	528	clock-frequency = <100000>;
	529	status = "disabled";
	530	};
	531
	532	i2c2: i2c@01c2b400 {
	533	compatible = "allwinner,sun4i-i2c";
	534	reg = <0x01c2b400 0x400>;
	535	interrupts = <9>;
	536	clocks = <&apb1_gates 2>;
	537	clock-frequency = <100000>;
	538	status = "disabled";
	539	};
874b4e45	540	};
7423d2d8	541	};