[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun4i-a10.dtsi

/*
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M: osc24M@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
		};

		axi_gates: axi_gates@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-output-names = "axi_dram";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
		};

		ahb_gates: ahb_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",
				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_mp", "ahb_mali400";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
		};

		apb0_gates: apb0_gates@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
				"apb0_ir1", "apb0_keypad";
		};

		/* dummy is pll62 */
		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&dummy>, <&osc32k>;
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
		};

		apb1_gates: apb1_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_can", "apb1_scr",
				"apb1_ps20", "apb1_ps21", "apb1_uart0",
				"apb1_uart1", "apb1_uart2", "apb1_uart3",
				"apb1_uart4", "apb1_uart5", "apb1_uart6",
				"apb1_uart7";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun4i-a10-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PA10", "PA11";
				allwinner,function = "uart1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-wdt";
			reg = <0x01c20c90 0x10>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&apb1_gates 0>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&apb1_gates 1>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&apb1_gates 2>;
			clock-frequency = <100000>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
7423d2d8 SR	1	/*
	2	* Copyright 2012 Stefan Roese
	3	* Stefan Roese <sr@denx.de>
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
69144e3b	13	/include/ "skeleton.dtsi"
7423d2d8 SR	14
7423d2d8 SR	15	/ {
69144e3b MR	16	interrupt-parent = <&intc>;
	17
	18	cpus {
8b2efa89 AB	19	#address-cells = <1>;
8b2efa89 AB	20	#size-cells = <0>;
69144e3b	21	cpu@0 {
14c44aa5	22	device_type = "cpu";
69144e3b	23	compatible = "arm,cortex-a8";
14c44aa5	24	reg = <0x0>;
69144e3b MR	25	};
	26	};
	27
7423d2d8 SR	28	memory {
	29	reg = <0x40000000 0x80000000>;
	30	};
874b4e45	31
69144e3b MR	32	clocks {
	33	#address-cells = <1>;
	34	#size-cells = <1>;
	35	ranges;
	36
	37	/*
	38	* This is a dummy clock, to be used as placeholder on
	39	* other mux clocks when a specific parent clock is not
	40	* yet implemented. It should be dropped when the driver
	41	* is complete.
	42	*/
	43	dummy: dummy {
	44	#clock-cells = <0>;
	45	compatible = "fixed-clock";
	46	clock-frequency = <0>;
	47	};
	48
69144e3b MR	49	osc24M: osc24M@01c20050 {
	50	#clock-cells = <0>;
	51	compatible = "allwinner,sun4i-osc-clk";
	52	reg = <0x01c20050 0x4>;
92fd6e06	53	clock-frequency = <24000000>;
69144e3b MR	54	};
	55
	56	osc32k: osc32k {
	57	#clock-cells = <0>;
	58	compatible = "fixed-clock";
	59	clock-frequency = <32768>;
	60	};
	61
	62	pll1: pll1@01c20000 {
	63	#clock-cells = <0>;
	64	compatible = "allwinner,sun4i-pll1-clk";
	65	reg = <0x01c20000 0x4>;
	66	clocks = <&osc24M>;
	67	};
	68
	69	/* dummy is 200M */
	70	cpu: cpu@01c20054 {
	71	#clock-cells = <0>;
	72	compatible = "allwinner,sun4i-cpu-clk";
	73	reg = <0x01c20054 0x4>;
	74	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
	75	};
	76
	77	axi: axi@01c20054 {
	78	#clock-cells = <0>;
	79	compatible = "allwinner,sun4i-axi-clk";
	80	reg = <0x01c20054 0x4>;
	81	clocks = <&cpu>;
	82	};
	83
	84	axi_gates: axi_gates@01c2005c {
	85	#clock-cells = <1>;
	86	compatible = "allwinner,sun4i-axi-gates-clk";
	87	reg = <0x01c2005c 0x4>;
	88	clocks = <&axi>;
	89	clock-output-names = "axi_dram";
	90	};
	91
	92	ahb: ahb@01c20054 {
	93	#clock-cells = <0>;
	94	compatible = "allwinner,sun4i-ahb-clk";
	95	reg = <0x01c20054 0x4>;
	96	clocks = <&axi>;
	97	};
	98
	99	ahb_gates: ahb_gates@01c20060 {
	100	#clock-cells = <1>;
	101	compatible = "allwinner,sun4i-ahb-gates-clk";
	102	reg = <0x01c20060 0x8>;
	103	clocks = <&ahb>;
	104	clock-output-names = "ahb_usb0", "ahb_ehci0",
	105	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
	106	"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
	107	"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
	108	"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
	109	"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
	110	"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
	111	"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
	112	"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
	113	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
	114	"ahb_de_fe1", "ahb_mp", "ahb_mali400";
	115	};
	116
	117	apb0: apb0@01c20054 {
118	#clock-cells = <0>;
119	compatible = "allwinner,sun4i-apb0-clk";
120	reg = <0x01c20054 0x4>;
121	clocks = <&ahb>;
122	};
123
124	apb0_gates: apb0_gates@01c20068 {
125	#clock-cells = <1>;
126	compatible = "allwinner,sun4i-apb0-gates-clk";
127	reg = <0x01c20068 0x4>;
128	clocks = <&apb0>;
129	clock-output-names = "apb0_codec", "apb0_spdif",
130	"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
131	"apb0_ir1", "apb0_keypad";
132	};
133
134	/* dummy is pll62 */
135	apb1_mux: apb1_mux@01c20058 {
136	#clock-cells = <0>;
137	compatible = "allwinner,sun4i-apb1-mux-clk";
138	reg = <0x01c20058 0x4>;
139	clocks = <&osc24M>, <&dummy>, <&osc32k>;
140	};
141
142	apb1: apb1@01c20058 {
143	#clock-cells = <0>;
144	compatible = "allwinner,sun4i-apb1-clk";
145	reg = <0x01c20058 0x4>;
146	clocks = <&apb1_mux>;
147	};
148
149	apb1_gates: apb1_gates@01c2006c {
150	#clock-cells = <1>;
151	compatible = "allwinner,sun4i-apb1-gates-clk";
152	reg = <0x01c2006c 0x4>;
153	clocks = <&apb1>;
154	clock-output-names = "apb1_i2c0", "apb1_i2c1",
155	"apb1_i2c2", "apb1_can", "apb1_scr",
156	"apb1_ps20", "apb1_ps21", "apb1_uart0",
157	"apb1_uart1", "apb1_uart2", "apb1_uart3",
158	"apb1_uart4", "apb1_uart5", "apb1_uart6",
159	"apb1_uart7";
160	};
161	};
162
b74aec1a	163	soc@01c00000 {
69144e3b MR	164	compatible = "simple-bus";
	165	#address-cells = <1>;
	166	#size-cells = <1>;
69144e3b MR	167	ranges;
69144e3b MR	168
e38afcb3 MR	169	emac: ethernet@01c0b000 {
	170	compatible = "allwinner,sun4i-emac";
	171	reg = <0x01c0b000 0x1000>;
	172	interrupts = <55>;
	173	clocks = <&ahb_gates 17>;
	174	status = "disabled";
	175	};
	176
	177	mdio@01c0b080 {
	178	compatible = "allwinner,sun4i-mdio";
	179	reg = <0x01c0b080 0x14>;
	180	status = "disabled";
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183	};
	184
69144e3b	185	intc: interrupt-controller@01c20400 {
6def126d	186	compatible = "allwinner,sun4i-ic";
69144e3b MR	187	reg = <0x01c20400 0x400>;
	188	interrupt-controller;
	189	#interrupt-cells = <1>;
	190	};
	191
e10911e1	192	pio: pinctrl@01c20800 {
874b4e45 MR	193	compatible = "allwinner,sun4i-a10-pinctrl";
874b4e45 MR	194	reg = <0x01c20800 0x400>;
39138bc6	195	interrupts = <28>;
36386d6e	196	clocks = <&apb0_gates 5>;
e10911e1	197	gpio-controller;
39138bc6	198	interrupt-controller;
874b4e45 MR	199	#address-cells = <1>;
874b4e45 MR	200	#size-cells = <0>;
e10911e1	201	#gpio-cells = <3>;
581981be MR	202
	203	uart0_pins_a: uart0@0 {
	204	allwinner,pins = "PB22", "PB23";
	205	allwinner,function = "uart0";
	206	allwinner,drive = <0>;
	207	allwinner,pull = <0>;
	208	};
	209
	210	uart0_pins_b: uart0@1 {
	211	allwinner,pins = "PF2", "PF4";
	212	allwinner,function = "uart0";
	213	allwinner,drive = <0>;
	214	allwinner,pull = <0>;
	215	};
	216
	217	uart1_pins_a: uart1@0 {
	218	allwinner,pins = "PA10", "PA11";
	219	allwinner,function = "uart1";
	220	allwinner,drive = <0>;
	221	allwinner,pull = <0>;
	222	};
27cce4ff MR	223
	224	i2c0_pins_a: i2c0@0 {
	225	allwinner,pins = "PB0", "PB1";
	226	allwinner,function = "i2c0";
	227	allwinner,drive = <0>;
	228	allwinner,pull = <0>;
	229	};
	230
	231	i2c1_pins_a: i2c1@0 {
	232	allwinner,pins = "PB18", "PB19";
	233	allwinner,function = "i2c1";
	234	allwinner,drive = <0>;
	235	allwinner,pull = <0>;
	236	};
	237
	238	i2c2_pins_a: i2c2@0 {
	239	allwinner,pins = "PB20", "PB21";
	240	allwinner,function = "i2c2";
	241	allwinner,drive = <0>;
	242	allwinner,pull = <0>;
	243	};
496322bc	244
b21da664 MR	245	emac_pins_a: emac0@0 {
	246	allwinner,pins = "PA0", "PA1", "PA2",
	247	"PA3", "PA4", "PA5", "PA6",
	248	"PA7", "PA8", "PA9", "PA10",
	249	"PA11", "PA12", "PA13", "PA14",
	250	"PA15", "PA16";
	251	allwinner,function = "emac";
	252	allwinner,drive = <0>;
	253	allwinner,pull = <0>;
	254	};
874b4e45	255	};
89b3c99f	256
69144e3b	257	timer@01c20c00 {
b6e1a53b	258	compatible = "allwinner,sun4i-timer";
69144e3b MR	259	reg = <0x01c20c00 0x90>;
	260	interrupts = <22>;
	261	clocks = <&osc24M>;
	262	};
	263
	264	wdt: watchdog@01c20c90 {
0b19b7c2	265	compatible = "allwinner,sun4i-wdt";
69144e3b MR	266	reg = <0x01c20c90 0x10>;
	267	};
	268
89b3c99f MR	269	uart0: serial@01c28000 {
	270	compatible = "snps,dw-apb-uart";
	271	reg = <0x01c28000 0x400>;
	272	interrupts = <1>;
	273	reg-shift = <2>;
	274	reg-io-width = <4>;
9ff49ec7	275	clocks = <&apb1_gates 16>;
89b3c99f MR	276	status = "disabled";
89b3c99f MR	277	};
76f14d0a	278
69144e3b MR	279	uart1: serial@01c28400 {
	280	compatible = "snps,dw-apb-uart";
	281	reg = <0x01c28400 0x400>;
	282	interrupts = <2>;
	283	reg-shift = <2>;
	284	reg-io-width = <4>;
	285	clocks = <&apb1_gates 17>;
	286	status = "disabled";
	287	};
	288
76f14d0a MR	289	uart2: serial@01c28800 {
	290	compatible = "snps,dw-apb-uart";
	291	reg = <0x01c28800 0x400>;
	292	interrupts = <3>;
	293	reg-shift = <2>;
	294	reg-io-width = <4>;
9ff49ec7	295	clocks = <&apb1_gates 18>;
76f14d0a MR	296	status = "disabled";
	297	};
	298
69144e3b MR	299	uart3: serial@01c28c00 {
	300	compatible = "snps,dw-apb-uart";
	301	reg = <0x01c28c00 0x400>;
	302	interrupts = <4>;
	303	reg-shift = <2>;
	304	reg-io-width = <4>;
	305	clocks = <&apb1_gates 19>;
	306	status = "disabled";
	307	};
	308
76f14d0a MR	309	uart4: serial@01c29000 {
	310	compatible = "snps,dw-apb-uart";
	311	reg = <0x01c29000 0x400>;
	312	interrupts = <17>;
	313	reg-shift = <2>;
	314	reg-io-width = <4>;
9ff49ec7	315	clocks = <&apb1_gates 20>;
76f14d0a MR	316	status = "disabled";
	317	};
	318
	319	uart5: serial@01c29400 {
	320	compatible = "snps,dw-apb-uart";
	321	reg = <0x01c29400 0x400>;
	322	interrupts = <18>;
	323	reg-shift = <2>;
	324	reg-io-width = <4>;
9ff49ec7	325	clocks = <&apb1_gates 21>;
76f14d0a MR	326	status = "disabled";
	327	};
	328
	329	uart6: serial@01c29800 {
	330	compatible = "snps,dw-apb-uart";
	331	reg = <0x01c29800 0x400>;
	332	interrupts = <19>;
	333	reg-shift = <2>;
	334	reg-io-width = <4>;
9ff49ec7	335	clocks = <&apb1_gates 22>;
76f14d0a MR	336	status = "disabled";
	337	};
	338
	339	uart7: serial@01c29c00 {
	340	compatible = "snps,dw-apb-uart";
	341	reg = <0x01c29c00 0x400>;
	342	interrupts = <20>;
	343	reg-shift = <2>;
	344	reg-io-width = <4>;
9ff49ec7	345	clocks = <&apb1_gates 23>;
76f14d0a MR	346	status = "disabled";
76f14d0a MR	347	};
f1741fda MR	348
	349	i2c0: i2c@01c2ac00 {
	350	compatible = "allwinner,sun4i-i2c";
	351	reg = <0x01c2ac00 0x400>;
	352	interrupts = <7>;
	353	clocks = <&apb1_gates 0>;
	354	clock-frequency = <100000>;
	355	status = "disabled";
	356	};
	357
	358	i2c1: i2c@01c2b000 {
	359	compatible = "allwinner,sun4i-i2c";
	360	reg = <0x01c2b000 0x400>;
	361	interrupts = <8>;
	362	clocks = <&apb1_gates 1>;
	363	clock-frequency = <100000>;
	364	status = "disabled";
	365	};
	366
	367	i2c2: i2c@01c2b400 {
	368	compatible = "allwinner,sun4i-i2c";
	369	reg = <0x01c2b400 0x400>;
	370	interrupts = <9>;
	371	clocks = <&apb1_gates 2>;
	372	clock-frequency = <100000>;
	373	status = "disabled";
	374	};
874b4e45	375	};
7423d2d8	376	};